CN212183509U - Frequency synthesis circuit of ultrahigh frequency broadband phase-locked system - Google Patents
Frequency synthesis circuit of ultrahigh frequency broadband phase-locked system Download PDFInfo
- Publication number
- CN212183509U CN212183509U CN202021153657.9U CN202021153657U CN212183509U CN 212183509 U CN212183509 U CN 212183509U CN 202021153657 U CN202021153657 U CN 202021153657U CN 212183509 U CN212183509 U CN 212183509U
- Authority
- CN
- China
- Prior art keywords
- resistor
- phase
- capacitor
- output
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 23
- 238000003786 synthesis reaction Methods 0.000 title claims abstract description 23
- 239000003990 capacitor Substances 0.000 claims description 31
- 230000003068 static effect Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 238000001514 detection method Methods 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000013256 coordination polymer Substances 0.000 description 2
- 230000001629 suppression Effects 0.000 description 1
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The utility model discloses an ultrahigh frequency broadband phase-locked system frequency synthesis circuit, including the phase discriminator, loop filter, voltage-controlled oscillator, preset frequency divider, first matching attenuator, amplifier and second matching attenuator, the phase discriminator is provided with clock signal input pin, control data input pin, latch signal input pin, reference source input pin, phase discrimination signal input pin and phase discrimination signal output pin, phase discrimination signal output pin is connected with voltage-controlled oscillator's input through loop filter, voltage-controlled oscillator's output is used for the synthetic signal of output frequency; the preset frequency divider, the first matching attenuator, the amplifier and the second matching attenuator are sequentially connected to form a feedback loop, and a frequency synthesis signal output by the voltage-controlled oscillator is also sent to a phase discrimination signal input pin of the phase discriminator through the feedback loop. The effect is as follows: the output impedance of the preset frequency divider can be effectively matched with the condition that the output impedance changes, phase noise is reduced, and the stability of the performance at high and low temperatures is ensured.
Description
Technical Field
The utility model relates to a frequency synthesis technique, more specifically say, relate to a hyperfrequency broadband phase-locked system frequency synthesis circuit.
Background
The phase-locked system frequency synthesis technology is a high-precision and high-stability frequency synthesis technology, mainly comprises a reference source, a phase discriminator, a loop filter, a preset frequency divider, a voltage-controlled oscillator and the like, and a circuit is designed in a general situation as shown in figure 1.
Based on the circuit shown in fig. 1, there are several problems in the implementation process:
(1) the phase detector has a certain requirement range for the input power of the phase detection input signal Fp, when the range is inappropriate, the phase noise of the output signal is seriously influenced, even the whole circuit cannot work, the output power of the general preset frequency divider is low, and particularly under the high-temperature condition, the power is obviously reduced along with the rise of the working frequency, so that the deterioration of the output signal is even caused, and the output signal cannot work.
(2) When the phase-locked loop is used for broadband frequency synthesis, the output impedance of the preset frequency divider can be changed to a certain extent, impedance mismatching is caused when the output impedance is serious, technical indexes of phase noise, stray suppression and the like of output signals are influenced, and even the phase-locked loop cannot work.
Disclosure of Invention
In order to solve the above technical problem, the utility model provides a hyperfrequency broadband phase-locked system frequency synthesis circuit. The synthesizer circuit mainly improves a feedback loop of a phase-locked loop, so that the high-temperature and low-temperature performance stability in a cross-octave frequency synthesis scheme is ensured, and the technical index deterioration is little or even no deterioration occurs.
In order to achieve the above object, the present invention adopts the following specific technical solutions:
the utility model provides an ultrahigh frequency broadband phase-locked system frequency synthesis circuit, includes phase discriminator, loop filter, voltage controlled oscillator and preset frequency divider, and its key lies in: the phase discriminator is provided with a clock signal input pin, a control data input pin, a latch signal input pin, a reference source input pin, a phase discrimination signal input pin and a phase discrimination signal output pin, the phase discrimination signal output pin is connected with the input end of the voltage-controlled oscillator through the loop filter, and the output end of the voltage-controlled oscillator is used for outputting a frequency synthesis signal;
the preset frequency divider, the first matching attenuator, the amplifier and the second matching attenuator are sequentially connected to form a feedback loop, and a frequency synthesis signal output by the voltage-controlled oscillator is also sent to a phase discrimination signal input pin of the phase discriminator through the feedback loop.
Optionally, the first matched attenuator includes a resistor R14, a resistor R17, and a resistor R18, one end of the resistor R14 is used as an input end of the first matched attenuator, the other end of the resistor R14 is used as an output end of the first matched attenuator, the input end of the first matched attenuator is further grounded through a resistor R18, and the output end of the first matched attenuator is further grounded through a resistor R17.
Optionally, the second matched attenuator includes a resistor R13, a resistor R15, and a resistor R16, one end of the resistor R13 is used as an input end of the second matched attenuator, the other end of the resistor R13 is used as an output end of the second matched attenuator, the input end of the second matched attenuator is further grounded through a resistor R16, and the output end of the second matched attenuator is further grounded through a resistor R15.
Optionally, the amplifier adopts an operational amplifier module with the model of the HMC 342.
Optionally, the preset frequency divider is a low-noise static frequency divider with a model number of HMC 432.
Optionally, the phase detector adopts a chip model of ADF4153 BR.
Optionally, the loop filter includes a resistor R1, a resistor R5, a capacitor C9, a capacitor C10, and a capacitor C13, one end of the resistor R1 is used as an input end of the loop filter, the other end of the resistor R1 is used as an output end of the loop filter, the input end of the loop filter is grounded through the capacitor C9, the output end of the loop filter is grounded through the capacitor C10, and the resistor R5 and the capacitor C13 further form a series branch connected between the input end and the ground end of the loop filter.
Optionally, the output end of the voltage-controlled oscillator is further provided with a matching circuit, the matching circuit includes a resistor R2, a resistor R3, a resistor R6, a capacitor C7, and a capacitor C14, one side of a frequency synthesized signal output by the voltage-controlled oscillator passes through the resistor R2 and then enters a series branch formed by the resistor R3 and the capacitor C7 to be output to the outside, and the other side of the frequency synthesized signal passes through a series branch formed by the resistor R6 and the capacitor C14 and then is sent to the feedback loop.
The utility model discloses a show the effect and be:
the utility model provides a hyperfrequency broadband phase-locked system frequency synthesis circuit through having increased two matching attenuators and an amplifier in feedback loop, can effectively match the condition that the output impedance that presets the frequency divider changes, reduces phase noise, ensures at high low temperature stable performance.
Drawings
The invention will be further explained with reference to the drawings and examples, wherein:
fig. 1 is a schematic circuit diagram of a conventional frequency synthesizer;
FIG. 2 is a schematic block diagram of the circuit of the present invention;
fig. 3 is a circuit schematic of the phase detector and loop filter of fig. 2;
FIG. 4 is a circuit schematic of the voltage controlled oscillator of FIG. 2;
fig. 5 is a schematic circuit diagram of a feedback loop according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following detailed description is made with reference to the accompanying drawings and specific embodiments, and it should be understood that the specific embodiments described herein are only used for explaining the present invention, and are not used for limiting the present invention.
The present embodiment provides a frequency synthesis circuit of an ultrahigh frequency broadband phase-locked system, as shown in fig. 2 to 5, including a phase discriminator, a loop filter, a voltage-controlled oscillator, a preset frequency divider, a first matched attenuator, an amplifier, and a second matched attenuator;
as can be seen from fig. 3, the phase detector has a chip model of ADF4153BR, which is labeled as U2 in the figure, the module is powered by 12V and 3.3V dc power supplies, a clock signal input pin CLK, a control DATA input pin DATA, a latch signal input pin LE, a reference source input pin REFin, a phase detection signal input pin RFin, and a phase detection signal output pin CP are disposed in the module, and the phase detection signal output pin CP is connected to the input terminal of the voltage-controlled oscillator through the loop filter.
The loop filter comprises a resistor R1, a resistor R5, a capacitor C9, a capacitor C10 and a capacitor C13, one end of the resistor R1 serves as the input end of the loop filter, the other end of the resistor R1 serves as the output end of the loop filter, the input end of the loop filter is grounded through the capacitor C9, the output end of the loop filter is grounded through the capacitor C10, and the resistor R5 and the capacitor C13 further form a series branch which is connected between the input end and the ground end of the loop filter.
As can be seen from fig. 4, in the implementation process, the chip type of the voltage-controlled oscillator is UMZ-527-D16, the voltage-controlled oscillator is powered by a 12V dc power supply, the output terminal of the voltage-controlled oscillator is further provided with a matching circuit, the matching circuit includes a resistor R2, a resistor R3, a resistor R6, a capacitor C7 and a capacitor C14, one side of a frequency synthesized signal output by the voltage-controlled oscillator passes through the resistor R2 and then enters a series branch formed by the resistor R3 and the capacitor C7 to realize radio frequency output, and the other side of the frequency synthesized signal passes through a series branch formed by the resistor R6 and the capacitor C14 and then is sent to a feedback loop.
As can also be seen from fig. 3, the rf output port is further configured with a matching attenuation circuit formed by a resistor R4, a resistor R8, a resistor R9, and a capacitor C8.
As shown in fig. 5, the preset frequency divider, the first matching attenuator, the amplifier, and the second matching attenuator are sequentially connected to form a feedback loop, and the frequency synthesized signal output by the voltage-controlled oscillator is further sent to the phase detection signal input pin of the phase detector through the feedback loop.
Wherein: the preset frequency divider adopts a low-noise static frequency divider with the model of HMC 432;
the first matching attenuator comprises a resistor R14, a resistor R17 and a resistor R18, one end of the resistor R14 is used as the input end of the first matching attenuator, the other end of the resistor R14 is used as the output end of the first matching attenuator, the input end of the first matching attenuator is grounded through a resistor R18, and the output end of the first matching attenuator is grounded through a resistor R17.
The amplifier adopts an operational amplifier module with the model of HMC 342;
the second matching attenuator comprises a resistor R13, a resistor R15 and a resistor R16, one end of the resistor R13 is used as the input end of the second matching attenuator, the other end of the resistor R13 is used as the output end of the second matching attenuator, the input end of the second matching attenuator is grounded through a resistor R16, and the output end of the second matching attenuator is grounded through a resistor R15.
Based on the frequency synthesis circuit of the ultrahigh frequency broadband phase-locked system provided by the embodiment, stable output in high and low temperature environments during cross-octave frequency synthesis can be effectively ensured, technical index deterioration is reduced, output impedance change of a preset frequency divider is adapted, impedance matching is ensured, and signal phase noise is reduced.
Finally, it should be noted that the above-mentioned embodiments of the present invention are described in connection with the accompanying drawings, but the present invention is not limited to the above-mentioned embodiments, which are only illustrative and not restrictive, and those skilled in the art can make many forms without departing from the spirit and scope of the present invention, which is protected by the following claims.
Claims (8)
1. The utility model provides an ultrahigh frequency broadband phase-locked system frequency synthesis circuit, includes phase discriminator, loop filter, voltage controlled oscillator and preset frequency divider, its characterized in that: the phase discriminator is provided with a clock signal input pin, a control data input pin, a latch signal input pin, a reference source input pin, a phase discrimination signal input pin and a phase discrimination signal output pin, the phase discrimination signal output pin is connected with the input end of the voltage-controlled oscillator through the loop filter, and the output end of the voltage-controlled oscillator is used for outputting a frequency synthesis signal;
the preset frequency divider, the first matching attenuator, the amplifier and the second matching attenuator are sequentially connected to form a feedback loop, and a frequency synthesis signal output by the voltage-controlled oscillator is also sent to a phase discrimination signal input pin of the phase discriminator through the feedback loop.
2. The UHF wideband phase-locked loop frequency synthesizer circuit of claim 1, further comprising: the first matching attenuator comprises a resistor R14, a resistor R17 and a resistor R18, one end of the resistor R14 is used as the input end of the first matching attenuator, the other end of the resistor R14 is used as the output end of the first matching attenuator, the input end of the first matching attenuator is grounded through a resistor R18, and the output end of the first matching attenuator is grounded through a resistor R17.
3. The UHF wideband phase-locked loop frequency synthesizer circuit of claim 1, further comprising: the second matching attenuator comprises a resistor R13, a resistor R15 and a resistor R16, one end of the resistor R13 is used as the input end of the second matching attenuator, the other end of the resistor R13 is used as the output end of the second matching attenuator, the input end of the second matching attenuator is grounded through a resistor R16, and the output end of the second matching attenuator is grounded through a resistor R15.
4. The UHF wideband phase-locked loop frequency synthesizer circuit as claimed in any one of claims 1-3, wherein: the amplifier adopts an operational amplifier module with the model of HMC 342.
5. The UHF wideband phase-locked loop frequency synthesizer circuit of claim 4, further comprising: the preset frequency divider adopts a low-noise static frequency divider with the model of HMC 432.
6. The UHF wideband phase-locked loop frequency synthesizer circuit of claim 1, further comprising: the phase detector adopts a chip model of ADF4153 BR.
7. The UHF wideband phase-locked loop frequency synthesizer circuit of claim 1, further comprising: the loop filter comprises a resistor R1, a resistor R5, a capacitor C9, a capacitor C10 and a capacitor C13, one end of the resistor R1 serves as the input end of the loop filter, the other end of the resistor R1 serves as the output end of the loop filter, the input end of the loop filter is grounded through the capacitor C9, the output end of the loop filter is grounded through the capacitor C10, and the resistor R5 and the capacitor C13 further form a series branch which is connected between the input end and the ground end of the loop filter.
8. The UHF wideband phase-locked loop frequency synthesizer circuit of claim 1, further comprising: the output end of the voltage-controlled oscillator is also provided with a matching circuit which comprises a resistor R2, a resistor R3, a resistor R6, a capacitor C7 and a capacitor C14, one side of a frequency synthesis signal output by the voltage-controlled oscillator passes through the resistor R2 and then enters a series branch formed by the resistor R3 and the capacitor C7 to be output outwards, and the other side of the frequency synthesis signal passes through a series branch formed by the resistor R6 and the capacitor C14 and then is sent into the feedback loop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021153657.9U CN212183509U (en) | 2020-06-20 | 2020-06-20 | Frequency synthesis circuit of ultrahigh frequency broadband phase-locked system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021153657.9U CN212183509U (en) | 2020-06-20 | 2020-06-20 | Frequency synthesis circuit of ultrahigh frequency broadband phase-locked system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212183509U true CN212183509U (en) | 2020-12-18 |
Family
ID=73760653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021153657.9U Active CN212183509U (en) | 2020-06-20 | 2020-06-20 | Frequency synthesis circuit of ultrahigh frequency broadband phase-locked system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212183509U (en) |
-
2020
- 2020-06-20 CN CN202021153657.9U patent/CN212183509U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2289345C (en) | Inverted super regenerative receiver | |
| CN103795410A (en) | Broadband frequency agility frequency source based on double phase-locked loops | |
| CN110445491B (en) | Phase-locked loop based on preset frequency and dynamic loop bandwidth | |
| CN212183509U (en) | Frequency synthesis circuit of ultrahigh frequency broadband phase-locked system | |
| US20030103591A1 (en) | Phase locked loop circuit and clock reproduction circuit | |
| CN101888244B (en) | Low-power consumption phase-locked loop circuit | |
| CN108169720B (en) | X-band low-phase noise navigation frequency modulation continuous wave radar transmitting system | |
| CN116647232A (en) | Frequency source synthesis circuit for improving frequency hopping time | |
| CN111884652A (en) | Phase-locked loop circuit with function of quickly locking frequency | |
| US6380810B1 (en) | Reduced lock time for a phase locked loop | |
| CN111404544A (en) | Internal and external reference signal self-adaptive Ku-band low-phase noise frequency source | |
| CN207625538U (en) | A kind of New Solid radio-frequency power system | |
| CN212660148U (en) | Voltage-controlled oscillator and frequency generator | |
| CN112165324A (en) | Low-jitter ultra-narrow pulse width local oscillator signal generating device and method of sampler | |
| CN204481795U (en) | A kind of Low phase noise Microwave Frequency Source phase lock circuitry and equipment | |
| Li et al. | Design of x-band low phase noise and low spurious frequency source based on HMC778 | |
| CN105934011A (en) | Integrated radio frequency signal control circuit and method | |
| CN111859459A (en) | Block chain data security management platform | |
| GB2312578A (en) | Amplifier and loop filter arrangement for a PLL using a charge pump | |
| CN104202047A (en) | Monolithic integration frequency synthesizer based on VHF (very high frequency) band | |
| CN116760366B (en) | Low-noise fractional frequency multiplication circuit and implementation method thereof | |
| CN209593404U (en) | A kind of wideband degree high performance frequency synthesizer | |
| CN109889193A (en) | The phase demodulation of low phase demodulation frequency phaselocked loop is inhibited to reveal spuious loop filter circuit | |
| CN214675163U (en) | Ultra-wideband signal generating device | |
| CN218162451U (en) | Radio frequency receiving circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |