CN212136445U - Packaging structure of chip - Google Patents
Packaging structure of chip Download PDFInfo
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- CN212136445U CN212136445U CN202020941163.0U CN202020941163U CN212136445U CN 212136445 U CN212136445 U CN 212136445U CN 202020941163 U CN202020941163 U CN 202020941163U CN 212136445 U CN212136445 U CN 212136445U
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- chip
- circuit board
- substrate
- hole
- circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
The utility model discloses a chip packaging structure, which comprises a first circuit board, a substrate, a first chip, a first metal ball, a second circuit board, a second chip and a second metal ball, wherein the first circuit board comprises a first surface and a second surface which are oppositely arranged, and a through hole which runs through the first surface and the second surface; the substrate is positioned on the first surface and covers the through hole; the first chip is positioned on one side of the substrate facing the through hole and extends towards the through hole; the first metal ball is connected with the substrate and the first surface; the second circuit board is positioned on the second surface and covers the through hole; the second chip is positioned on one side of the second circuit board facing the through hole and extends towards the through hole; the second metal ball is connected with the second circuit board and the second surface. The utility model discloses a first metal ball and second metal ball not only can effectively adjust the distance between first chip and the second chip, can also realize signal transmission simultaneously.
Description
Technical Field
The utility model relates to a chip package technical field especially relates to a packaging structure of chip.
Background
With the continuous development of science and technology, more and more electronic devices are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present.
The main component of the electronic device for realizing the preset function is a chip, along with the continuous progress of the integrated circuit technology, the integration level of the chip is higher and higher, the function of the chip is stronger and stronger, and the size of the chip is smaller and smaller, so that the chip needs to form a packaging structure through packaging so as to be electrically connected with an external circuit board.
In the prior art, referring to fig. 1, the package structure 100 includes a first chip 11 and a second chip 12, and a distance between the first chip 11 and the second chip 12 needs to be precisely controlled to achieve a precise function between the first chip 11 and the second chip 12.
For example, the first chip 11 is an emitter, and here, for example, a laser emitter is taken as an example, which has optical characteristics such as high brightness, good directivity, good monochromaticity, good coherence, and in particular, due to the good directivity of the laser, the laser becomes the preferred light source for barcode scanning.
In the bar code scanning process, besides the laser chip, a scanning device for scanning the emergent light of the laser chip is also required, and the second chip 12 is a diffractive optical element playing a role in scanning.
In the prior art, the first chip 11 is fixed on the frame 13, the second chip 12 is fixed on the substrate 14, and the end of the frame 13 is fixed to the substrate 14 through the glue 15, at this time, the distance B between the first chip 11 and the second chip 12 is mainly adjusted by controlling the thickness of the glue 15, and the adjustment mode needs to use special equipment and materials, so that the cost is high, the processing time is long, and the yield is low.
Disclosure of Invention
An object of the utility model is to provide a can improve optical accuracy, packaging efficiency, reduce cost's chip's packaging structure.
In order to realize one of the above objects of the present invention, an embodiment of the present invention provides a chip packaging structure, including:
the first circuit board comprises a first surface, a second surface and a through hole, wherein the first surface and the second surface are oppositely arranged, and the through hole penetrates through the first surface and the second surface;
the substrate is positioned on the first surface and covers the through hole;
the first chip is positioned on one side, facing the through hole, of the substrate and extends towards the through hole;
a first metal ball connecting the substrate and the first surface;
the second circuit board is positioned on the second surface and covers the through hole;
the second chip is positioned on one side, facing the through hole, of the second circuit board and extends towards the through hole;
and the second metal ball is connected with the second circuit board and the second surface.
As a further improvement of an embodiment of the present invention, the first metal ball and the second metal ball are gold balls.
As a further improvement of an embodiment of the present invention, the first chip includes an emitter, and the second chip includes a diffractive optical element.
As a further improvement of an embodiment of the present invention, the package structure further includes a first sealing adhesive connected to the side edge of the substrate and the first surface, and a second sealing adhesive connected to the side edge of the second circuit board and the second surface.
As a further improvement of an embodiment of the present invention, the substrate is a transparent substrate.
As an embodiment of the utility model provides a further improvement, the base plate towards one side of through-hole is equipped with the metal lines layer, first circuit board includes first interconnection circuit, the second circuit board includes second interconnection circuit and third interconnection circuit, first chip is through first routing electric connection the metal lines layer, the metal lines layer passes through first metal ball electric connection first interconnection circuit, first interconnection circuit passes through second metal ball electric connection the second interconnection circuit, the second chip passes through second routing electric connection the third interconnection circuit.
As an improvement of an embodiment of the present invention, the metal circuit layer includes a protection layer, a redistribution layer and a solder resist layer which are connected in sequence, the one end electric connection of the first metal ball is connected to the solder resist layer, and the first chip is connected to the redistribution layer through the first wire bonding.
As an improvement of an embodiment of the present invention, the second circuit board is kept away from one side of the through-hole is provided with a second connection terminal and a third connection terminal, the second connection terminal is conducted to the second interconnection line, the third connection terminal is conducted to the third interconnection line, the second circuit board is passed through the second connection terminal reaches the third connection terminal electric connection external circuit board.
As a further improvement of an embodiment of the present invention, the first circuit board and the second circuit board are printed circuit boards.
As a further improvement of an embodiment of the present invention, the first chip and the second chip are aligned in a vertical direction, and the vertical direction is defined as a stacking direction of the substrate, the first circuit board and the second circuit board.
Compared with the prior art, the beneficial effects of the utility model reside in that: the height of the first metal ball and the height of the second metal ball of an embodiment of the present invention can be effectively controlled by the welding force, that is, the height of the first metal ball and the height of the second metal ball can be effectively controlled by adjusting the welding force, so as to effectively control the distance between the first chip and the second chip, greatly improve the optical precision between the first chip and the second chip, greatly improve the assembly efficiency, and reduce the cost; in addition, signal transmission among the substrate, the first circuit board and the second circuit board can be directly realized through the first metal balls and the second metal balls, in other words, the first metal balls and the second metal balls can effectively adjust the distance between the first chip and the second chip, and meanwhile signal transmission can be realized.
Drawings
FIG. 1 is a schematic diagram of a package structure in the prior art;
fig. 2 is a schematic diagram of a package structure according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating steps of a packaging method according to an embodiment of the present invention;
fig. 4 to 13 are schematic diagrams of steps of a packaging method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. However, these embodiments are not intended to limit the present invention, and structural, methodical, or functional changes that may be made by one of ordinary skill in the art based on these embodiments are all included in the scope of the present invention.
In the various drawings of the present invention, certain dimensions of structures or portions may be exaggerated relative to other structures or portions for ease of illustration, and thus, are used only to illustrate the basic structure of the subject matter of the present invention.
Referring to fig. 2, a schematic diagram of a chip package structure 200 according to an embodiment of the present invention is shown.
The package structure 200 includes a first circuit board 20, a substrate 30, a first chip 31, first metal balls 32, a second circuit board 40, a second chip 41, and second metal balls 42.
The first circuit board 20 includes a first surface 21 and a second surface 22 disposed opposite to each other, and a through hole 23 penetrating the first surface 21 and the second surface 22.
The substrate 30 is located on the first surface 21 and covers the through hole 23.
The first chip 31 is located on a side of the substrate 30 facing the through hole 23, and the first chip 31 extends toward the through hole 23.
The first metal balls 32 are connected to the substrate 30 and the first surface 21.
The second circuit board 40 is located on the second surface 22 and covers the through-hole 23.
The second chip 41 is located on a side of the second circuit board 40 facing the through hole 23, and the second chip 41 extends toward the through hole 23.
The second metal balls 42 connect the second circuit board 40 and the second surface 22.
Here, the substrate 30 is connected to the first circuit board 20 through the first metal ball 32, the second circuit board 40 is connected to the first circuit board 20 through the second metal ball 42, and the heights of the first metal ball 32 and the second metal ball 42 can be effectively controlled through the welding force, that is, the heights of the first metal ball 32 and the second metal ball 42 can be effectively controlled through adjusting the welding force, so as to effectively control the distance between the first chip 31 and the second chip 41, thereby greatly improving the optical precision between the first chip 31 and the second chip 41, and greatly improving the assembly efficiency and reducing the cost.
In addition, the substrate 30 and the first circuit board 20, and the first circuit board 20 and the second circuit board 40 are respectively connected by the first metal balls 32 and the second metal balls 42 having conductive properties, and signal transmission among the substrate 30, the first circuit board 20 and the second circuit board 40 can be directly realized by the first metal balls 32 and the second metal balls 42, in other words, the first metal balls 32 and the second metal balls 42 can not only effectively adjust the distance between the first chip 31 and the second chip 41, but also can realize signal transmission.
It should be noted that the first chip 31 and the second chip 41 are aligned in a vertical direction X, so that light can be transmitted between the first chip 31 and the second chip 41, and the vertical direction X is defined as a stacking direction of the substrate 30, the first circuit board 20, and the second circuit board 40.
In addition, the phrase "the first metal balls 32 are connected to the substrate 30" means that the first metal balls 32 are located on one side of the substrate 30, and the first metal balls 32 and the substrate 30 may be directly connected or indirectly connected, in other words, one component is connected, fixed or located on the other component in this embodiment, and the first metal balls 32 and the substrate are directly connected or indirectly connected.
In the present embodiment, the first chip 31 includes the emitter 31, the second chip 41 includes a Diffractive Optical Element (DOE) 41, and the first chip 31 and the second chip 41 cooperate with each other to realize barcode scanning, but not limited thereto.
After the diffractive optical element 41 receives the downward scanning light beam sent by the emitter 31, the diffractive optical element 41 divides the scanning light beam into a plurality of scanning light beams to achieve a scanning effect, at this time, a distance between an emitting surface of the emitter 31 and a receiving surface of the diffractive optical element 41 needs to be effectively controlled so that the diffractive optical element 41 can completely receive the scanning light beam, that is, a target distance H between the first active surface 311 of the first chip 31 and the second active surface 411 of the second chip 41 needs to be controlled, and the present embodiment can achieve effective control of the target distance H through the first metal ball 32 and the second metal ball 42.
In the present embodiment, the substrate 30 is a transparent substrate, so that the plurality of scanning beams emitted by the diffractive optical element 41 can be transmitted to the outside of the package structure 100.
The first metal balls 32 and the second metal balls 42 are gold balls, which can effectively improve the signal transmission performance.
The first circuit board 20 and the second circuit board 40 are printed circuit boards, so as to ensure the overall strength of the package structure 100 and the accuracy of the adjustment process of the target distance H.
In the present embodiment, the first circuit board 20 includes a first interconnection 201, the first interconnection 201 is a circuit carried by the first circuit board 20 itself, and the first interconnection 201 extends to the first surface 21 and the second surface 22 of the first circuit board 20 respectively; the second circuit board 40 includes a second interconnection 401 and a third interconnection 402, the second interconnection 401 and the third interconnection 402 are circuits of the second circuit board 40, and the second interconnection 401 and the third interconnection 402 extend to the upper surface 43 and the lower surface 44 of the second circuit board 40, respectively.
A second connection terminal 4011 and a third connection terminal 4021 are disposed on a side of the second circuit board 40 (i.e., the lower surface 44 of the second circuit board 40) away from the through hole 23, the second connection terminal 4011 connects the second interconnection 401, the third connection terminal 4021 connects the third interconnection 402, and the second circuit board 40 is electrically connected to an external circuit board, such as a system control board, through the second connection terminal 4011 and the third connection terminal 4021.
A metal circuit layer 33 is disposed on a side of the substrate 30 facing the through hole 23, and the first chip 31 is electrically connected to the metal circuit layer 33 through a first wire 34.
Here, the metal circuit layer 33 includes a protection layer 301, a redistribution layer 302 and a solder resist layer 303 sequentially connected to the substrate 30, and a thermal expansion coefficient of the protection layer 301 may be between the substrate 30 and the redistribution layer 302, but not limited thereto, the protection layer 301 may be disposed to prevent the redistribution layer 301 and the substrate 30 from being separated from each other under stress pulling.
One end of the first metal ball 32 is electrically connected to the solder mask layer 303, and the first chip 31 is electrically connected to the redistribution layer 302 through the first wire bond 34.
The metal circuit layer 33 is electrically connected to the first interconnection 201 through the first metal ball 32, and the first interconnection 201 is electrically connected to the second interconnection 401 through the second metal ball 42, so that the first chip 31 can be electrically connected to the external circuit board sequentially through the first wire 34, the metal circuit layer 33, the first metal ball 32, the first interconnection 201, the second interconnection 401, and the second connection terminal 4011, and thus the control of the first chip 31, for example, the power-on operation of the first chip 31 can be controlled through the external circuit board.
The second chip 41 is electrically connected to the third interconnection 402 through the second wire bond 45, so that the second chip 41 can be electrically connected to the external circuit board through the second wire bond 45, the third interconnection 402 and the third connection terminal 4021 in sequence, and thus the control of the second chip 41, for example, the scanning direction and the scanning range of the second chip 41 can be controlled through the external circuit board.
It can be seen that in the present embodiment, the first metal balls 32 and the second metal balls 42 can achieve conduction between the substrate 30, the first circuit board 20 and the second circuit board 40, so that the first chip 31 and the second chip 41 can be electrically connected to an external circuit board, and the control of the chips can be achieved through a simple structure.
In this embodiment, the package structure 100 further includes a first package adhesive 35 connecting the side edge 304 of the substrate 30 and the first surface 21 of the first circuit board 20, and a second package adhesive 46 connecting the side edge 403 of the second circuit board 40 and the second surface 22, the first package adhesive 35 can improve the stability of the matching between the substrate 30 and the first circuit board 20, and similarly, the second package adhesive 46 can improve the stability of the matching between the second circuit board 40 and the first circuit board 20.
An embodiment of the present invention further provides a chip packaging method, which combines the description of the foregoing packaging structure 100 and fig. 3 to 13, and the chip packaging method includes the steps of:
s1: referring to fig. 4 to 7, the first chip 31 is fixed to the substrate 30, and the first metal balls 32 are formed on the substrate 30 to form a first portion P1;
step S1 specifically includes:
forming a metal wiring layer 33 on the substrate 30;
here, the metal wiring layer 33 includes a protective layer 301, a rewiring layer 302, and a solder resist layer 303 that are connected to the substrate 30 in this order.
Fixing the first chip 31 on the side of the substrate 30 provided with the metal circuit layer 33 by a die bonding process;
electrically connecting the first chip 31 and the metal circuit layer 33 by a wire bonding process;
here, the first chip 31 is electrically connected to the redistribution layer 302 by a first wire bond 34.
The first metal balls 32 electrically connected to the metal wiring layer 33 are formed to constitute a first portion P1.
Here, one end of the first metal ball 32 is electrically connected to the solder resist layer 303, and the first portion P1 includes the substrate 30, the first chip 31, the first metal ball 32, the metal circuit layer 33, and the first wire 34.
S3: referring to fig. 8 and 9, a second chip 41 is fixed to the second circuit board 40, and second metal balls 42 are formed on the second circuit board 40 to form a second portion P2;
step S3 specifically includes:
fixing the second chip 41 to the second circuit board 40 by a die bonding process;
here, the second chip 41 is fixed to the upper surface 43 of the second circuit board 40.
Electrically connecting the second chip 41 and the third interconnection 402 in the second circuit board 40 by a wire bonding process;
here, the second chip 41 is electrically connected to the third interconnection 402 through the second wire bond 45.
The second metal balls 42 electrically connected to the second interconnection lines 401 in the second circuit board 40 are formed to be constructed as a second portion P2.
Here, one end of the second metal ball 42 is electrically connected to the second interconnection 401, and the second portion P2 includes the second circuit board 40, the second chip 41, the second metal ball 42 and the second wire bond 45.
S5: with reference to fig. 10, a through hole 23 is formed on the first circuit board 20 and penetrates through the first surface 21 and the second surface 22 of the first circuit board 20;
s7: referring to fig. 11, the first portion P1 is bonded to the first surface 21 of the first circuit board 20 by a flip-chip process, the first chip 31 extending toward the through-hole 23;
s9: referring to fig. 12, the second portion P2 is bonded to the second surface 22 of the first circuit board 20 through a flip-chip process, and the second chip 41 extends toward the through-hole 23.
Specifically, the steps S7 and S9 are: the first metal balls 32 are electrically connected to the first interconnection lines 201 of the first circuit board 20 by a flip-chip process, and similarly, the second metal balls 42 are electrically connected to the first interconnection lines 201 of the first circuit board 20 and the second interconnection lines 401 of the second circuit board 40 by a flip-chip process, so that the interconnection of the first portion P1 and the first circuit board 20 and the interconnection of the second portion P2 and the first circuit board 20 are realized.
Here, it should be noted that, in order to improve the stability of the fit between the substrate 30 and the first circuit board 20 and improve the stability of the fit between the first circuit board 20 and the second circuit board 40, the steps S7 and S9 further include:
the first sealing adhesive 35 is formed to connect the side edge 304 of the substrate 30 and the first surface 21 of the first circuit board 20, and the second sealing adhesive 46 is formed to connect the side edge 403 of the second circuit board 40 and the second surface 22.
The specific operation flow of steps S7 and S9 is:
acquiring a first distance H1 between the second surface 22 of the first circuit board 20 far away from the first part P1 and the first active surface 311 of the first chip 31 far away from the substrate 30, and acquiring a desired height H' of the second metal balls 42 according to a target distance H between the second active surface 411 of the second chip 41 and the first active surface 311 of the first chip 31 and the first distance H1;
the molding height of the second metal balls 42 is made to be a desired height H' by controlling the bonding force during the flip-chip process.
Here, assuming that the distance between the first active surface 311 of the first chip 31 and the surface of the substrate 30 close to the through hole 23 is H2, the distance between the first metal balls 32 and the surface of the substrate 30 close to the through hole 23 is H3, and the thickness of the first circuit board 20 is H4, the first distance H1 is H4+ H3-H2, the distances H1 and H2 can be effectively controlled by controlling the process, the material, the welding strength, and the like, and then the thickness H4 is obtained by selecting the first circuit board 20 of a certain specification, so that the first distance H1 can be obtained.
Then, according to different package structures 100, the target distance H between the second active surface 411 of the second chip 41 and the first active surface 311 of the first chip 31 is different, and at this time, the target distance H corresponding to the package structure 100 can be obtained in advance, and the desired height H' of the second metal ball 42 can be obtained according to the target distance H and the first distance H1.
Here, assuming that the distance between the second active surface 411 of the second chip 41 and the upper surface 43 of the second circuit board 40 is H5, the desired height H 'of the second metal ball 42 is H + H5-H1, in practical applications, the distance H5 may be a fixed value through a certain process, material, etc., and then the desired height H' of the second metal ball 42 may be directly obtained according to the obtained first distance H1.
After obtaining the desired height H 'of the second metal ball 42, the bonding force may be controlled in the flip-chip process of step S9 to make the molding height of the second metal ball 42 be the desired height H', so as to ensure that the distance between the second active surface 411 of the second chip 41 and the first active surface 311 of the first chip 31 is the desired target distance H.
In addition, the process method of the embodiment further includes the steps of:
s11: referring to fig. 13, a second connection terminal 4011 for connecting the second interconnection line 401 and a third connection terminal 4021 for connecting the third interconnection line 402 are formed on a side of the second circuit board 40 away from the through hole 23.
It can be seen that the substrate 30 is connected to the first circuit board 20 through the first metal balls 32, the second circuit board 40 is connected to the first circuit board 20 through the second metal balls 42, and the desired height H' of the second metal balls 42 can be effectively controlled by adjusting the soldering force, so that the target distance H between the first chip 31 and the second chip 41 can be effectively controlled, the optical precision between the first chip 31 and the second chip 41 can be greatly improved, the assembly efficiency can be greatly improved, and the cost can be reduced.
In addition, the first chip 31 can be electrically connected to the external circuit board sequentially through the first wire bond 34, the metal circuit layer 33, the first metal ball 32, the first interconnection 201, the second interconnection 401 and the second connection terminal 4011, so that the first chip 31 can be controlled by the external circuit board, for example, the power-on/off operation of the first chip 31 is controlled, the second chip 41 is electrically connected to the third interconnection 402 through the second wire bond 45, so that the second chip 41 can be electrically connected to the external circuit board sequentially through the second wire bond 45, the third interconnection 402 and the third connection terminal 4021, so that the second chip 41 can be controlled by the external circuit board, for example, the scanning direction, the scanning range and the like of the second chip 41 are controlled, in this embodiment, the substrate 30, the first circuit board 20 and the second circuit board 40 can be electrically connected through the first metal ball 32 and the second metal ball 42, therefore, the first chip 31 and the second chip 41 can be electrically connected to an external circuit board, and the control of the chips is realized through a simple structure.
For other descriptions of the process of the present embodiment, reference may be made to the description of the package structure 100, which is not repeated herein.
It should be emphasized that the above-mentioned step numbers S1, S3, S5, S7, S9, and S11 do not actually limit the front-to-back relationship of the steps, for example, the step S3 of forming the second portion P2 may be located before the step S1 of forming the first portion P1, and the target distance H between the first chip 31 and the second chip 41 may be controlled by first bonding the second portion P2 to the first circuit board 20 and then controlling the height of the first metal balls 32 by adjusting the soldering force.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above list of details is only for the practical implementation of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent implementations or modifications that do not depart from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (10)
1. A chip package structure, comprising:
the first circuit board comprises a first surface, a second surface and a through hole, wherein the first surface and the second surface are oppositely arranged, and the through hole penetrates through the first surface and the second surface;
the substrate is positioned on the first surface and covers the through hole;
the first chip is positioned on one side, facing the through hole, of the substrate and extends towards the through hole;
a first metal ball connecting the substrate and the first surface;
the second circuit board is positioned on the second surface and covers the through hole;
the second chip is positioned on one side, facing the through hole, of the second circuit board and extends towards the through hole;
and the second metal ball is connected with the second circuit board and the second surface.
2. The package structure of claim 1, wherein the first metal balls and the second metal balls are gold balls.
3. The package structure of claim 1, wherein the first chip comprises an emitter and the second chip comprises a diffractive optical element.
4. The package structure of claim 1, further comprising a first encapsulant coupling the side edge of the substrate and the first surface, and a second encapsulant coupling the side edge of the second circuit board and the second surface.
5. The package structure of claim 1, wherein the substrate is a transparent substrate.
6. The package structure according to claim 1, wherein a metal circuit layer is disposed on a side of the substrate facing the through hole, the first circuit board includes a first interconnection circuit, the second circuit board includes a second interconnection circuit and a third interconnection circuit, the first chip is electrically connected to the metal circuit layer through a first wire, the metal circuit layer is electrically connected to the first interconnection circuit through the first metal ball, the first interconnection circuit is electrically connected to the second interconnection circuit through the second metal ball, and the second chip is electrically connected to the third interconnection circuit through the second wire.
7. The package structure according to claim 6, wherein the metal circuit layer comprises a passivation layer, a redistribution layer and a solder resist layer sequentially connected to the substrate, one end of the first metal ball is electrically connected to the solder resist layer, and the first chip is electrically connected to the redistribution layer through the first wire bonding.
8. The package structure according to claim 6, wherein a second connection terminal and a third connection terminal are disposed on a side of the second circuit board away from the through hole, the second connection terminal connects the second interconnection line, the third connection terminal connects the third interconnection line, and the second circuit board is electrically connected to an external circuit board through the second connection terminal and the third connection terminal.
9. The package structure of claim 1, wherein the first circuit board and the second circuit board are both printed circuit boards.
10. The package structure according to claim 1, wherein the first chip and the second chip are aligned in a vertical direction, and the vertical direction is defined as a stacking direction of the substrate, the first circuit board, and the second circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020941163.0U CN212136445U (en) | 2020-05-28 | 2020-05-28 | Packaging structure of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020941163.0U CN212136445U (en) | 2020-05-28 | 2020-05-28 | Packaging structure of chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212136445U true CN212136445U (en) | 2020-12-11 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020941163.0U Active CN212136445U (en) | 2020-05-28 | 2020-05-28 | Packaging structure of chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212136445U (en) |
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2020
- 2020-05-28 CN CN202020941163.0U patent/CN212136445U/en active Active
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