CN212113707U - High-density packaging lead frame structure and high-density packaging structure with same - Google Patents
High-density packaging lead frame structure and high-density packaging structure with same Download PDFInfo
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- CN212113707U CN212113707U CN202020140882.2U CN202020140882U CN212113707U CN 212113707 U CN212113707 U CN 212113707U CN 202020140882 U CN202020140882 U CN 202020140882U CN 212113707 U CN212113707 U CN 212113707U
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- lead frame
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model discloses a high-density packaging lead frame structure, which comprises a bottom frame, at least one lead frame and a plurality of pads or bulges which are used for installing chips and have conductivity, wherein the bottom frame, the at least one lead frame and the plurality of pads or bulges are sequentially stacked; each lead frame comprises a buffer layer and an RDL line layer which are sequentially stacked from the top surface of the bottom frame, and the bonding pad or the bulge is arranged on the upper surface of the RDL line layer of the lead frame which is farthest away from the bottom frame; the buffer layer is a low CTE insulating material layer, and the RDL line layer is connected to the surface of the bottom frame through a conducting structure. The utility model discloses a set up the lead frame structure of cermet mixed type, greatly solved because the too big problem that can not high density installation chip of silica-based and metal substrate coefficient of expansion difference, can overcome warpage and homogeneity simultaneously and be not enough these defects.
Description
Technical Field
The utility model relates to a semiconductor package technical field, in particular to high density encapsulation lead frame structure and have its high density packaging structure.
Background
The lead frame is a base material of semiconductor package, is used as a chip carrier of an integrated circuit, realizes the electrical connection between the leading-out end of an internal circuit of the chip and an external lead by means of bonding materials (gold wires, aluminum wires and copper wires), forms a key structural member of an electrical circuit, and plays a role of a bridge connected with an external lead. Its main functions are circuit connection, heat dissipation and mechanical support.
The history of semiconductor package development proves that the packaging material has a decisive role in the updating process of packaging technology, and basically forms a development fixed form of the generation of packaging and the generation of materials. Different lead frames are required to be adopted for different semiconductor packaging modes, so the development trend of the semiconductor packaging mode determines the development trend of the lead frames.
Generally, the semiconductor package is affected by the surface mounting technology, and the package is gradually developed toward thinning and miniaturization in recent years, so that the package has the advantages of high density, multiple functions, excellent performance, small volume, low power consumption, high speed, smaller delay, continuously reduced cost and the like. But a simple product form and process are always lacked, the advantages of QFN, QFP, BGA, FC (Flip chip), COL (chip On lead), CSP and the like can be integrated, and meanwhile, the flexibility of packaging design, high I/O, high chip-to-packaging volume ratio, good heat dissipation and conductivity and excellent reliability and quality are met; a brand new packaging metal ceramic substrate based on a frame base material is provided, and has the capacity of mass production.
However, conventional EMC pre-molded packages are easily layered with the metal frame; the density of the traditional etching lead frame or MIS lead frame is limited, and the line width spacing of 75um is achieved at the limit, so that the RDL design of a chip PAD is required; for system-in-package, because the CTE value of metal is much larger than that of silicon substrate, the chip is easy to generate cracks, leakage, short circuit and other defects due to stress pulling caused by temperature change or extreme working environment during packaging, particularly, the ceramic capacitor resistor needs to be layered due to expansion and shrinkage of metal, and if the BT substrate is adopted, the problems of heat dissipation, cost and the like are large; the cost of the ceramic substrate is much higher than that of the metal substrate, and in addition, the ceramic substrate is limited by the size and is relatively brittle; the metal ceramic frame is a revolutionary innovative technology, breaks through the constraint of the traditional packaging form, integrates various advantageous characteristics, has strong impact on the traditional QFN, QFP and BGA products, and can be closely combined with various industry trends of COL, FC, copper wire ball bonding and the like; the MIS material itself is relatively thin. However, the substrate is prone to warpage and uniformity problems during the packaging process.
It is therefore highly desirable to have a new package lead frame that ensures high chip bonding density while overcoming the warpage and uniformity problems.
SUMMERY OF THE UTILITY MODEL
In order to solve the problems of the prior art, in one aspect, an embodiment of the present invention provides a high-density package lead frame structure, which includes a bottom frame, at least one lead frame, and a plurality of pads or bumps for mounting a chip and having electrical conductivity, which are stacked in sequence; each lead frame comprises a buffer layer and an RDL line layer which are sequentially stacked from the top surface of the bottom frame, and the bonding pad or the bulge is arranged on the upper surface of the RDL line layer of the lead frame which is farthest away from the bottom frame; the buffer layer is a low CTE insulating material layer, and the RDL line layer is connected to the surface of the bottom frame through a conducting structure.
In a further improvement of the embodiment of the present invention, the material of the buffer layer is a ceramic epoxy resin or a silica resin with a low CTE value.
As the utility model discloses embodiment's further improvement, conducting structure is including filling copper thick liquid conducting hole, filling heat conduction insulating material's conducting hole or copper post.
As a further improvement of the embodiment of the present invention, the bottom frame is a discontinuous structure from the nearest buffer layer, and the bottom frame forms a step inside the frame.
As a further improvement of the embodiment of the present invention, the bottom frame is away from the surface of the buffer layer is provided with a pad layer for connecting the bottom frame and the substrate.
As a further improvement of the embodiment of the present invention, the surface of the pad layer is coated with a nickel layer, a nickel palladium gold layer, an OSP layer, a silver layer, a nickel silver gold layer, a nickel lead tin alloy, or a tin silver alloy.
As a further improvement of the embodiment of the present invention, the at least one lead frame further includes an air guide groove, and an air flow passage formed by the air guide groove communicates with the bottom frame and the mounted chip.
As a further improvement of the embodiment of the present invention, the bottom frame is a metal copper frame, an FR4 material circuit board or a BT substrate.
On the other hand, the utility model also discloses a high-density packaging structure, which comprises a substrate, a high-density packaging lead frame structure and a chip which are arranged in sequence; the chip is connected to the substrate through the high-density packaging lead frame structure, and the electric connection is realized through the bonding pad or the protrusion.
As a further improvement of the embodiment of the present invention, the substrate is a ceramic epoxy resin or a silica resin, or a silica PI.
The utility model discloses following beneficial effect has:
1. the utility model adopts the metal ceramic mixed frame, and the ceramic substrate with the similar BGA structure formed by multilayer masking, exposure, pre-filling, pressing, drilling, electroplating, secondary exposure, secondary etching and surface treatment on the metal carrier plate can realize the advantages of the I/O quantity and density higher than those of the traditional substrate;
2. the utility model can realize the line width spacing up to 15 um; if laser forming and direct copper electroplating are used, the ceramic or silicon dioxide material can be used for a multilayer substrate with the line width and the line distance of 12/12 mu m, so that two-layer, three-layer and four-layer multilayer packaging can be realized.
3. The utility model adopts the metal ceramic mixed type frame, which greatly solves the problem of overlarge difference between the expansion coefficients of the silicon substrate and the metal substrate, and is convenient for the flip chip; adopting an additive long copper column, covering a low CTE insulating material to manufacture a multilayer superfine circuit, ensuring that the CTE value of a substrate approaches to the silicon-based CTE value of a chip, and ensuring the reliability of the chip and a ceramic passive component;
4. the chip does not need RDL design when being combined with the chip, and does not need a conventional packaging substrate, thereby simplifying the chip manufacturing link and reducing the production cost;
5. the insulating layer and the base plate of the ceramic resin or the silicon dioxide resin used by the utility model solve the problems of warping, flatness and overlarge expansion coefficient;
6. the I/O number of the chip is up to 1000, and the I/O number of the chip is realized in the same packaging form, so that the problem of low I/O pin number of the traditional lead frame is further solved;
7. the utility model not only guides out heat through each chip pin, but also can directly radiate heat through the insulating layer, thus greatly improving the uniformity of heat radiation, and being beneficial to solving the problems of heat radiation and heavy current of high-power chips; the structure has the advantages that the heat capacity of the copper column and the lead frame is large, the heat dissipation effect is good, the heat dissipation coefficient of the ceramic material is high, and the high-frequency performance is good; EMC materials have heat dissipation effect, high frequency performance and reliability which are far different from those of ceramic materials;
8. the utility model discloses a packaging structure adopts PNL type fan-out structure, and the inlayer fan-in design is showing and is shortening bonding wire length, and the encapsulation efficiency is high, and is higher than other types of fan-out type packaging structure intensity, and stability is good, and is with low costs simultaneously;
9. the lead frame package of the utility model firstly obtains the BGA ball mounting capability, and supports WB, FC and COL mounting, chip stacking and package stacking designs;
10. the structure of the utility model can be realized on other materials, such as FR4 material circuit board, BT substrate, and has wide application range; the process is simple and the processing time is short.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts;
fig. 1 is a schematic diagram of a high-density package lead frame according to an embodiment of the present invention;
the examples in the figures are represented as:
1-a bottom frame; 2-a lead frame; 3-a buffer layer; 4-RDL line layer; 5-bulge; 6-conducting structure; 7-step; 8-a pad layer; 9-a substrate; 10-a chip; 11-a ceramic device; 12-air guide groove.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the following description will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
The embodiment of the utility model provides a high-density packaging lead frame, as shown in figure 1, comprising a bottom frame 1, a lead frame 2 and a plurality of pads or bumps 5 which are used for installing chips and have conductivity, which are stacked in sequence; each lead frame 2 comprises a buffer layer 3 and an RDL line layer 4 which are sequentially stacked from the top surface of the bottom frame 1, and a pad or a bump 5 is arranged on the upper surface of the RDL line layer 4 of the lead frame 2 farthest from the bottom frame 1.
The bottom frame 1 is a metal copper frame; in other alternative embodiments, the bottom frame may also be an FR4 material circuit board or a BT-type substrate.
It should be noted that, in other alternative embodiments, the number of the lead frames 2 may be two or more, and correspondingly, the high-density package lead frame includes a bottom frame, a first lead frame, a second lead frame, and a plurality of bumps for mounting a chip and having conductivity, which are sequentially stacked; the first lead frame comprises a first buffer layer and a first RDL line layer which are arranged on the top surface of the bottom frame, the second lead frame comprises a second buffer layer and a second RDL line layer which are arranged on the top surface of the bottom frame, namely the high-density packaging lead frame comprises the bottom frame, the first buffer layer, the first RDL line layer, the second buffer layer, the second RDL line layer and a plurality of bulges which are used for installing chips and have conductivity, wherein the bottom frame, the first buffer layer, the first RDL line layer, the second buffer layer, the second RDL line layer and the bulges are.
The buffer layer 3 is a low CTE insulating material layer, and the RDL line layer 4 is connected to the surface of the bottom frame 1 through the via structure 6.
The buffer layer 3 is made of a ceramic epoxy resin or a silica resin having a low CTE value.
Specifically, the via structure 6 is a copper pillar, and in other alternative embodiments, the via structure may be selected from a via hole filled with copper paste and a via hole filled with a thermal conductive insulating material.
Specifically, a step 7 as shown in fig. 1 is formed in the frame interior of the bottom frame 1 in a direction extending to the buffer layer 3, and the buffer layer 3 on the upper surface of the bottom frame 1 is of a discontinuous structure for the purpose of reducing warpage and delamination caused by the CTE value mismatch between metallic copper and the buffer layer.
In other implementations, when the number of the lead frames is two or more, and the high-density package lead frame has a multi-layer structure, a step is formed between the bottom frame and the buffer layer of the lead frame closest to the bottom frame.
A pad layer 8 is arranged on the surface of the bottom frame 1 of the high-density package lead frame structure away from the buffer layer 3, and is used for connecting the bottom frame 1 and the substrate 9.
Further, the surface of the pad layer 8 is coated with a nickel layer, a nickel palladium gold layer, an OSP layer, a silver layer, a nickel silver gold layer, a nickel lead tin alloy, or a tin silver alloy.
Preferably, the lead frame 2 further includes air guide grooves 12, and air flow channels formed by the air guide grooves 12 communicate the bottom frame 1 and the mounted chips 10.
On the other hand, the utility model also discloses a high-density packaging structure, which comprises a substrate 9, the high-density packaging lead frame structure and a chip 10 which are arranged in sequence; the chip 10 is connected to the substrate 9 through the high-density package lead frame structure, and is electrically connected through the bonding pad or bump 5.
In alternative embodiments, the chip 10 may be a logic chip, an analog chip, a memory chip; the substrate 9 and the ceramic device 11 can also be connected by the above-described lead frame structure.
In the embodiment of the present invention, the substrate is an EMC or ceramic epoxy resin or silica resin, or silica PI.
The utility model discloses following beneficial effect has:
1. the utility model adopts the metal ceramic mixed frame, and the ceramic substrate with the similar BGA structure formed by multilayer masking, exposure, pre-filling, pressing, drilling, electroplating, secondary exposure, secondary etching and surface treatment on the metal carrier plate can realize the advantages of the I/O quantity and density higher than those of the traditional substrate;
2. the utility model can realize the line width spacing up to 15 um; if laser forming and direct copper electroplating are used, the ceramic or silicon dioxide material can be used for a multilayer substrate with the line width and the line distance of 12/12 mu m, so that two-layer, three-layer and four-layer multilayer packaging can be realized.
3. The utility model adopts the metal ceramic mixed type frame, which greatly solves the problem of overlarge difference between the expansion coefficients of the silicon substrate and the metal substrate, and is convenient for the flip chip; adopting an additive long copper column, covering a low CTE insulating material to manufacture a multilayer superfine circuit, ensuring that the CTE value of a substrate approaches to the silicon-based CTE value of a chip, and ensuring the reliability of the chip and a ceramic passive component;
4. the chip does not need RDL design when being combined with the chip, and does not need a conventional packaging substrate, thereby simplifying the chip manufacturing link and reducing the production cost;
5. the insulating layer and the base plate of the ceramic resin or the silicon dioxide resin used by the utility model solve the problems of warping, flatness and overlarge expansion coefficient;
6. the I/O number of the chip is up to 1000, and the I/O number of the chip is realized in the same packaging form, so that the problem of low I/O pin number of the traditional lead frame is further solved;
7. the utility model not only guides out heat through each chip pin, but also can directly radiate heat through the insulating layer, thus greatly improving the uniformity of heat radiation, and being beneficial to solving the problems of heat radiation and heavy current of high-power chips; the structure has the advantages that the heat capacity of the copper column and the lead frame is large, the heat dissipation effect is good, the heat dissipation coefficient of the ceramic material is high, and the high-frequency performance is good; EMC materials have heat dissipation effect, high frequency performance and reliability which are far different from those of ceramic materials;
8. the utility model discloses a packaging structure adopts PNL type fan-out structure, and the inlayer fan-in design is showing and is shortening bonding wire length, and the encapsulation efficiency is high, and is higher than other types of fan-out type packaging structure intensity, and stability is good, and is with low costs simultaneously;
9. the lead frame package of the utility model firstly obtains the BGA ball mounting capability, and supports WB, FC and COL mounting, chip stacking and package stacking designs;
10. the structure of the utility model can be realized on other materials, such as FR4 material circuit board, BT substrate, and has wide application range; the process is simple and the processing time is short.
Above-mentioned all optional technical scheme can adopt arbitrary combination to form the optional embodiment of this utility model, and the repeated description is no longer given here.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the present invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention.
Claims (10)
1. A high-density packaging lead frame structure is characterized by comprising a bottom frame, at least one lead frame and a plurality of pads or bulges which are used for mounting chips and have conductivity, wherein the bottom frame, the at least one lead frame and the plurality of pads or bulges are sequentially stacked; each lead frame comprises a buffer layer and an RDL line layer which are sequentially stacked from the top surface of the bottom frame, and the bonding pad or the bulge is arranged on the upper surface of the RDL line layer of the lead frame which is farthest away from the bottom frame; the buffer layer is a low CTE insulating material layer, and the RDL line layer is connected to the surface of the bottom frame through a conducting structure.
2. The high-density package lead frame structure according to claim 1, wherein the buffer layer is made of a low CTE ceramic-based epoxy resin or a silicon dioxide-based resin.
3. The high-density package lead frame structure of claim 1, wherein the via structure comprises a copper paste filled via, a thermally conductive and insulating material filled via, or a copper pillar.
4. The high-density package lead frame structure of claim 1, wherein the buffer layer closest to the bottom frame is a discontinuous structure, and the bottom frame forms a step inside the frame.
5. The high-density package lead frame structure according to claim 1, wherein the bottom frame is provided with a pad layer on a surface away from the buffer layer for connecting the bottom frame and the substrate.
6. The high-density package lead frame structure of claim 5, wherein the surface of the pad layer is coated with a nickel-gold layer, a nickel-palladium-gold layer, an OSP layer, a silver layer, a nickel-silver-gold layer, a nickel-lead-tin alloy, or a tin-silver alloy.
7. The high-density package lead frame structure of claim 1, wherein the bottom frame is a copper frame, an FR4 board or a BT substrate.
8. The high-density package lead frame structure of claim 1, wherein the at least one lead frame further comprises air-guiding grooves, the air-guiding grooves forming air flow channels communicating the bottom frame and the mounted chips.
9. A high-density package structure, comprising a substrate, the high-density package lead frame structure of any one of claims 1 to 8, and a chip, which are sequentially disposed; the chip is connected to the substrate through the high-density packaging lead frame structure, and the electric connection is realized through the bonding pad or the protrusion.
10. The high-density package structure according to claim 9, wherein the substrate is a ceramic-based epoxy resin or a silica-based resin, or a silica-based PI.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020140882.2U CN212113707U (en) | 2020-01-21 | 2020-01-21 | High-density packaging lead frame structure and high-density packaging structure with same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020140882.2U CN212113707U (en) | 2020-01-21 | 2020-01-21 | High-density packaging lead frame structure and high-density packaging structure with same |
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| Publication Number | Publication Date |
|---|---|
| CN212113707U true CN212113707U (en) | 2020-12-08 |
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| CN202020140882.2U Active CN212113707U (en) | 2020-01-21 | 2020-01-21 | High-density packaging lead frame structure and high-density packaging structure with same |
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| Country | Link |
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| CN (1) | CN212113707U (en) |
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- 2020-01-21 CN CN202020140882.2U patent/CN212113707U/en active Active
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| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: High density packaging lead frame structure and high density packaging structure with it Effective date of registration: 20210926 Granted publication date: 20201208 Pledgee: Shenzhen hi tech investment small loan Co.,Ltd. Pledgor: SHENZHEN SUNSHINE CIRCUIT TECHNOLOGY Co.,Ltd. Registration number: Y2021980009918 |
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| PE01 | Entry into force of the registration of the contract for pledge of patent right |