CN212034106U

CN212034106U - Wiegand interface circuit and communication equipment

Info

Publication number: CN212034106U
Application number: CN202020648062.4U
Authority: CN
Inventors: 方志军
Original assignee: Shenzhen Sensetime Technology Co Ltd
Current assignee: Nanjing Manhou Network Technology Co ltd
Priority date: 2020-04-24
Filing date: 2020-04-24
Publication date: 2020-11-27
Anticipated expiration: 2030-04-24

Abstract

The embodiment of the application provides a wiegand interface circuit and communication equipment, wherein the wiegand interface circuit comprises a first interface circuit and a second interface circuit, and the first interface circuit comprises a first driving signal source, a first level conversion module, a first control module and a first sending module; the second interface circuit comprises a second driving signal source, a second level conversion module, a second control module and a second sending module; and under the condition that the duty ratio of the signal pulse output by the first driving signal source is greater than a first threshold value and the signal pulse output by the first driving signal source is at a continuous high level in a first data transmission period, the first control module and the first level conversion module control the output end of the first sending module to be in a weakly-driven high level state in the first data transmission period. The bus leakage problem of the Wiegand interface circuit can be solved.

Description

Wiegand interface circuit and communication equipment

Technical Field

The application relates to the technical field of terminals, in particular to a wiegand interface circuit and communication equipment.

Background

At present, in a security access control system, a Wiegand interface is widely applied to data communication between access control card reading devices. The safety of the circuit design of the wiegand interface is related to the safety and the reliability of the security access control system. Meanwhile, the Wiegand interface is widely applied to other products such as consumer electronics, industrial electronics and the like.

The wiegand interface signal standard specifies that the wiegand interface bus is in an idle state and is in a high level state when no data is transmitted. In the traditional circuit, the bus of the wiegand interface is in a strong-driving pull-up state, the driving current is large, and when the wiegand interfaces among the devices are connected with each other, the bus of the wiegand interface leaks electricity.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a wiegand interface circuit and a communication device, and the bus electric leakage problem of the wiegand interface circuit can be solved.

A first aspect of an embodiment of the present application provides a wiegand interface circuit, including a first interface circuit and a second interface circuit, where the first interface circuit includes a first driving signal source, a first level conversion module, a first control module, and a first sending module; the second interface circuit comprises a second driving signal source, a second level conversion module, a second control module and a second sending module;

the positive electrode of the first driving signal source is connected with the input end of the first level conversion module and the first input end of the first control module, the control end of the first level conversion module is connected with the second input end of the first control module, the output end of the first control module is connected with the first control end of the first sending module, and the output end of the first level conversion module is connected with the second control end of the first sending module; under the condition that the duty ratio of the signal pulse output by the first driving signal source is greater than a first threshold value and the signal pulse output by the first driving signal source is at a continuous high level in a first data transmission period, the first control module and the first level conversion module control the output end of the first sending module to be in a weakly-driven high level state in the first data transmission period;

the positive electrode of the second driving signal source is connected with the input end of the second level conversion module and the first input end of the second control module, the control end of the second level conversion module is connected with the second input end of the second control module, the output end of the second control module is connected with the first control end of the second sending module, and the output end of the second level conversion module is connected with the second control end of the second sending module; when the duty ratio of the signal pulse output by the second driving signal source is greater than a second threshold and the signal pulse output by the second driving signal source is at a continuous high level in the first data transmission period, the second control module and the second level conversion module control the output end of the second sending module to be in a weakly-driven high level state in the first data transmission period; the wiegand interface circuit is in an idle state in the first data transmission period.

Optionally, when the duty ratio of the signal pulse output by the first driving signal source is smaller than the first threshold and the signal pulse output by the first driving signal source is at a continuous high level in the first data transmission period, the first control module and the first level shift module control the output end of the first sending module to be in a high level state of strong driving in the first data transmission period; when the duty ratio of the signal pulse output by the second driving signal source is smaller than the second threshold and the signal pulse output by the second driving signal source has a low-level pulse period in the first data transmission cycle, the second control module and the second level conversion module control the output end of the second sending module to be in a low-level state of strong driving in the low-level pulse period of the first data transmission cycle; and the wiegand interface circuit transmits a high-level signal in the first data transmission period.

Optionally, when the duty ratio of the signal pulse output by the first driving signal source is smaller than the first threshold and the signal pulse output by the first driving signal source has a low-level pulse period in the first data transmission cycle, the first control module and the first level shift module control the output end of the first sending module to be in a low-level state of strong driving in the low-level pulse period of the first data transmission cycle; when the duty ratio of the signal pulse output by the second driving signal source is smaller than a second threshold and the signal pulse output by the second driving signal source is at a continuous high level in the first data transmission period, the second control module and the second level conversion module control the output end of the second sending module to be in a high level state of strong driving in the first data transmission period; and the wiegand interface circuit transmits a low-level signal in the first data transmission period.

Optionally, the first sending module includes a first voltage source, a first diode, a first switching tube, a second switching tube, a first resistor, a second resistor, and a third resistor;

the anode of the first driving signal source is connected with the input end of the first level conversion module and the input end of the first control module, the output end of the first level conversion module is connected with the control end of the second switch tube, the output end of the first control module is connected with the control end of the first switch tube, the anode of the first voltage source is connected with the anode of the first diode, the cathode of the first diode is connected with the first end of the first switch tube and the first end of the first resistor, the second end of the first switch tube is connected with the first end of the second resistor, the second end of the second resistor is connected with the first end of the third resistor and the first end of the second switch tube, the second end of the second switch tube is grounded, and the second end of the third resistor and the second end of the first resistor are connected with the output end of the first sending module; the resistance value of the second resistor is smaller than that of the first resistor;

the first control module and the first level conversion module control the output end of the first sending module to be in a weakly-driven high level state in the first data transmission period, specifically:

the first control module controls the first switching tube to be cut off under the condition that the duty ratio of the signal pulse output by the first driving signal source is larger than the first threshold value, if the signal pulse output by the first driving signal source is in a continuous high level in the first data transmission period, the first level conversion module controls the second switching tube to be cut off in the first data transmission period, and the output end of the first sending module is in a weakly-driven high level state in the first data transmission period.

Optionally, the first control module and the first level shift module control the output end of the first sending module to be in a high-level state of strong driving in the first data transmission period, specifically:

the first control module controls the first switching tube to be conducted under the condition that the duty ratio of signal pulses output by the first driving signal source is smaller than the first threshold value; if the signal pulse output by the first driving signal source is in a continuous high level in the first data transmission period, the first level conversion module controls the second switch tube to be cut off, and the output end of the first sending module is in a high level state of strong driving in the first data transmission period.

Optionally, the first control module and the first level shift module control the output end of the first sending module to be in a low-level state of strong driving in a low-level pulse period of the first data transmission cycle, specifically:

the first control module controls the first switching tube to be conducted under the condition that the duty ratio of signal pulses output by the first driving signal source is smaller than the first threshold value; if the signal pulse output by the first driving signal source has a low level pulse time period in the first data transmission cycle, the first level conversion module controls the second switch tube to be conducted in the low level pulse time period in the first data transmission cycle, and the output end of the first sending module is in a strong-driving low level state in the low level pulse time period in the first data transmission cycle.

Optionally, the first level shift module includes a second voltage source, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and a third switching tube; wherein:

the positive pole of the second voltage source is connected with the first end of the fourth resistor, the second end of the fourth resistor is connected with the positive pole of the driving signal source and the first end of the fifth resistor, the second end of the fifth resistor is connected with the control end of the third switching tube, the first end of the third switching tube is connected with the first end of the sixth resistor and the first end of the seventh resistor, the second end of the sixth resistor is connected with the negative pole of the first diode, the second end of the third switching tube is grounded, and the second end of the seventh resistor is connected with the control end of the second switching tube.

Optionally, the first control module includes a second diode, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a first capacitor, a fourth switching tube, and a fifth switching tube, where:

the anode of the second diode is connected to the anode of the first driving signal source and the first end of the eighth resistor, the cathode of the second diode is connected to the second end of the eighth resistor, the first end of the first capacitor and the first end of the ninth resistor, the second end of the first capacitor is grounded, the second end of the ninth resistor is connected to the first end of the tenth resistor and the control end of the fourth switching tube, the second end of the tenth resistor and the second end of the fourth switching tube are grounded, the first end of the fourth switching tube is connected to the first end of the eleventh resistor and the control end of the fifth switching tube, the second end of the eleventh resistor is connected to the first end of the twelfth resistor and the cathode of the first diode, and the second end of the twelfth resistor is connected to the first end of the thirteenth resistor and the first end of the fifth switching tube, the second end of the fifth switching tube is connected with the first end of the third switching tube, and the second end of the thirteenth resistor is connected with the control end of the first switching tube.

Optionally, when the output of the first driving signal source is turned from a low level to a high level, the voltage at the second end of the fourth resistor drives the third switching tube to turn on through the fifth resistor, so that the voltage at the first end of the third switching tube is turned from the high level to the low level, the voltage at the first end of the third switching tube drives the second switching tube to turn off through the seventh resistor, and the voltage at the first end of the second switching tube is turned from the low level to the high level;

when the output of the first driving signal source is turned over from a high level to a low level, the voltage of the second end of the fourth resistor drives the third switching tube to be cut off through the fifth resistor, so that the voltage of the first end of the third switching tube is turned over from the low level to the high level, the voltage of the first end of the third switching tube drives the second switching tube to be conducted through the seventh resistor, and the voltage of the first end of the second switching tube is turned over from the high level to the low level.

Optionally, in a power-on phase of the first driving signal source, a voltage at the second end of the fourth resistor is pulled up to the anode of the second voltage source through the fourth resistor.

Optionally, when the duty ratio of the signal pulse output by the first driving signal source is greater than a first threshold, the voltage of the first end of the first capacitor controls the fourth switching tube to be turned on through the ninth resistor, so that the fifth switching tube is turned off, and the voltage of the first end of the fifth switching tube controls the first switching tube to be turned off through the thirteenth resistor;

when the duty ratio of the signal pulse output by the first driving signal source is smaller than the first threshold and the signal pulse output by the first driving signal source is in a high-level period, the voltage of the first end of the first capacitor controls the fourth switching tube to be turned off through the ninth resistor, so that the fifth switching tube is turned on, and the voltage of the first end of the fifth switching tube controls the first switching tube to be turned on through the thirteenth resistor;

when the duty ratio of the signal pulse output by the first driving signal source is smaller than the first threshold and the signal pulse output by the first driving signal source is in a low level period, the voltage of the first end of the first capacitor controls the fourth switching tube to be switched off through the ninth resistor, so that the fifth switching tube is switched on, and the voltage of the first end of the fifth switching tube controls the first switching tube to be switched off through the thirteenth resistor.

Optionally, the first switch tube includes a first triode, the second switch tube includes a second triode, the third switch tube includes a third triode, the fourth switch tube includes a fourth triode, and the fifth switch tube includes a first metal oxide semiconductor field effect transistor.

Optionally, a voltage corresponding to the high level of the first driving signal source is equal to a voltage of the second voltage source;

the voltage of the first voltage source is greater than the voltage corresponding to the high level of the first driving signal source, and the voltage of the first voltage source is greater than the voltage of the second voltage source.

A second aspect of the embodiments of the present application provides a communication device, including a driver chip and the wiegand interface circuit according to the first aspect of the embodiments of the present application, where a first driver signal source and a second driver signal source in the wiegand interface circuit are provided by the driver chip.

In the wiegand interface circuit in the embodiment of the application, under the condition that the duty ratio of the signal pulse output by the first driving signal source is greater than the first threshold value and the duty ratio of the signal pulse output by the second driving signal source is greater than the second threshold value, the wiegand interface circuit is driven to be in the idle state, so that the output end of the first sending module and the output end of the second sending module are in the high-level state of weak driving, the situation that the wiegand interface circuit is in the high-level state of weak driving in the idle state is ensured, the driving current is low, and when wiegand interfaces between devices are connected with each other, the bus leakage problem of the wiegand interface circuit can be avoided.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a wiegand interface circuit provided in an embodiment of the present application;

FIG. 2 is a schematic output diagram of a Wiegand interface circuit provided in an embodiment of the present application;

fig. 3 is a schematic structural diagram of a first interface circuit according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a signal pulse provided by an embodiment of the present application;

fig. 5 is a schematic structural diagram of another first interface circuit provided in the embodiment of the present application;

FIG. 6a is a schematic diagram of a specific device parameter including a first interface circuit provided on the basis of FIG. 5;

FIG. 6b is a schematic diagram of signal pulses output by a first driving signal source of the first interface circuit shown in FIG. 6 a;

FIG. 6c is a simulated graph of one output signal pulse of the first interface circuit shown in FIG. 6a and a corresponding simulated graph of a signal pulse of the output of the first drive signal source;

FIG. 7a is a schematic diagram of another specific device parameter configuration including a first interface circuit provided on the basis of FIG. 5;

FIG. 7b is a schematic diagram of signal pulses output by another first driving signal source of the first interface circuit shown in FIG. 6 a;

fig. 8 is a schematic structural diagram of a communication device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may alternatively include other steps or elements not expressly listed or inherent to such process, system, article, or apparatus.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the specification. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The communication devices involved in the embodiments of the present application may include various handheld devices, vehicle-mounted devices, wearable devices, computing devices or other processing devices connected to a wireless modem with wireless communication functions, as well as various forms of User Equipment (UE), Mobile Stations (MS), terminal equipment (terminal device), and so on. For convenience of description, the above-mentioned devices are collectively referred to as a communication device.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a wiegand interface circuit according to an embodiment of the present disclosure. As shown in fig. 1, the wiegand interface circuit 100 may include a first interface circuit 10 and a second interface circuit 20, where the first interface circuit 10 includes a first driving signal source 11, a first level conversion module 12, a first control module 13, and a first sending module 14; the second interface circuit 20 includes a second driving signal source 21, a second level conversion module 22, a second control module 23 and a second sending module 24;

the positive electrode 111 of the first driving signal source 11 is connected to the input end 121 of the first level shift module 12 and the first input end 131 of the first control module 13, the control end 123 of the first level shift module 12 is connected to the second input end 133 of the first control module 13, the output end 132 of the first control module 13 is connected to the first control end 141 of the first sending module 14, and the output end 122 of the first level shift module 12 is connected to the second control end 142 of the first sending module 14; the anode 211 of the second driving signal source 21 is connected to the input end 221 of the second level shift module 22 and the first input end 231 of the second control module 23, the control end 223 of the second level shift module 22 is connected to the second input end 233 of the second control module 23, the output end 232 of the second control module 23 is connected to the first control end 241 of the second sending module 24, and the output end 222 of the second level shift module 22 is connected to the second control end 242 of the second sending module 24;

when the duty ratio of the signal pulse output by the first driving signal source 11 is greater than a first threshold and the signal pulse output by the first driving signal source 11 is at a continuously high level in a first data transmission period, the first control module 13 and the first level shift module 12 control the output terminal 143 of the first sending module 14 to be in a weakly driven high level state in the first data transmission period; when the duty ratio of the signal pulse output by the second driving signal source 21 is greater than a second threshold and the signal pulse output by the second driving signal source 21 is at a continuously high level in the first data transmission period, the second control module 23 and the second level shift module 22 control the output end 243 of the second sending module 24 to be in a weakly driven high level state in the first data transmission period; the wiegand interface circuit 100 is in an idle state during the first data transmission period.

In the embodiment of the present application, the output of the wiegand interface circuit 100 is composed of a DATA line 1(DATA1) and a DATA line 2(DATA 2). Data line 1 is the output 143 of the first sending module 14, and data line 2 is the output 243 of the second sending module 24. When the wiegand interface circuit 100 outputs data "0", a low-level pulse (i.e., a negative pulse) appears on the data line 1. When the wiegand interface circuit 100 outputs data "1", a low-level pulse (i.e., a negative pulse) appears on the data line 2. When the wiegand interface circuit 100 is in an idle state, the data lines 1 and 2 are both at a high level.

Referring to fig. 2, fig. 2 is a schematic output diagram of a wiegand interface circuit according to an embodiment of the present disclosure. As shown in FIG. 2, DATA1 and DATA2 may output signal pulses periodically. The wiegand interface circuit 100 in fig. 2 outputs data "1011" during 4 consecutive data transmission periods (e.g., the first data transmission period TW1, the second data transmission period TW2, the third data transmission period TW3, and the fourth data transmission period TW4 shown in fig. 2).

Specifically, during the transmission period TW1, DATA1 is at a high level, DATA2 is at a low level pulse with a duration TP1, and at this time, the wiegand interface circuit 100 outputs DATA "1". During the transmission period TW2, DATA1 occurs as a low pulse with duration TP2, DATA2 is at a sustained high level, and at this time, the Wiegand interface circuit 100 outputs DATA "0". During the transmission period TW3, DATA1 is high, DATA2 is a low pulse with duration TP3, and at this time, the Wiegand interface circuit 100 outputs DATA "1". During the transmission period TW4, DATA1 is high, DATA2 is a low pulse with duration TP4, and at this time, the Wiegand interface circuit 100 outputs DATA "1". Wherein, the time lengths of TP1, TP2, TP3 and TP4 can be the same. The durations of TW1, TW2, TW3, TW4 may be the same. In the wiegand interface circuit in the embodiment of the application, under the condition that the duty ratio of the signal pulse output by the first driving signal source is greater than the first threshold value and the duty ratio of the signal pulse output by the second driving signal source is greater than the second threshold value, the wiegand interface circuit is driven to be in the idle state, so that the output end of the first sending module and the output end of the second sending module are in the high-level state of weak driving, the situation that the wiegand interface circuit is in the high-level state of weak driving in the idle state is ensured, the driving current is low, and when wiegand interfaces between devices are connected with each other, the bus leakage problem of the wiegand interface circuit can be avoided.

Optionally, when the duty ratio of the signal pulse output by the first driving signal source 11 is smaller than the first threshold, and the signal pulse output by the first driving signal source 11 is at a continuously high level in the first data transmission period, the first control module 13 and the first level shift module 12 control the output 143 of the first sending module 14 to be in a high level state of strong driving in the first data transmission period; in the case that the duty ratio of the signal pulse output by the second driving signal source 21 is smaller than the second threshold, and the signal pulse output by the second driving signal source 21 has a low level pulse period in the first data transmission cycle, the second control module 23 and the second level shift module 22 control the output end 243 of the second sending module 24 to be in a low level state of strong driving in the low level pulse period of the first data transmission cycle; the wiegand interface circuit 100 transmits a high level signal in the first data transmission period.

In the wiegand interface circuit in the embodiment of the application, when the duty ratio of the signal pulse output by the first driving signal source is smaller than a first threshold, the signal pulse output by the first driving signal source is at a continuous high level in a first data transmission period, the duty ratio of the signal pulse output by the second driving signal source is smaller than a second threshold, and the signal pulse output by the second driving signal source has a low-level pulse period in the first data transmission period, the wiegand interface circuit is driven to transmit a high-level signal in the first data transmission period.

Optionally, in a case that a duty ratio of a signal pulse output by the first driving signal source 11 is smaller than the first threshold, and a low level pulse period exists in the first data transmission cycle of the signal pulse output by the first driving signal source 11, the first control module 13 and the first level shift module 12 control the output terminal 143 of the first sending module 14 to be in a low level state of strong driving in the low level pulse period of the first data transmission cycle; when the duty ratio of the signal pulse output by the second driving signal source 21 is smaller than a second threshold and the signal pulse output by the second driving signal source 21 is at a continuously high level in the first data transmission period, the second control module 23 and the second level shift module 22 control the output end 243 of the second sending module 24 to be in a high level state of strong driving in the first data transmission period; the wiegand interface circuit 100 transmits a low level signal in the first data transmission period.

In the wiegand interface circuit in the embodiment of the application, when the duty ratio of a signal pulse output by a first driving signal source is smaller than a first threshold, a low-level pulse period exists in the signal pulse output by the first driving signal source in a first data transmission period, and the duty ratio of a signal pulse output by a second driving signal source is smaller than a second threshold, and when the signal pulse output by the second driving signal source is at a continuous high level in the first data transmission period, the wiegand interface circuit is driven to transmit a low-level signal in the first data transmission period.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a first interface circuit according to an embodiment of the present disclosure. As shown in fig. 3, the first interface circuit 10 includes a first driving signal source 11, a first level shift module 12, a first control module 13, and a first transmitting module 14; the positive electrode 111 of the first driving signal source 11 is connected to the input end 121 of the first level shift module 12 and the first input end 131 of the first control module 13, the control end 123 of the first level shift module 12 is connected to the second input end 133 of the first control module 13, the output end 132 of the first control module 13 is connected to the first control end 141 of the first sending module 14, and the output end 122 of the first level shift module 12 is connected to the second control end 142 of the first sending module 14;

when the duty ratio of the signal pulse output by the first driving signal source 11 is greater than a first threshold and the signal pulse output by the first driving signal source 11 is at a continuously high level in a first data transmission period, the first control module 13 and the first level shift module 12 control the output terminal 143 of the first sending module 14 to be in a weakly driven high level state in the first data transmission period.

The first transmitting module 14 comprises a first voltage source V1, a first diode D1, a first switch tube Q1, a second switch tube Q2, a first resistor R1, a second resistor R2 and a third resistor R3;

the positive electrode of the first driving signal source 11 is connected to the input end 121 of the first level shift module 12 and the input end 131 of the first control module 13, the output end 122 of the first level shift module 12 is connected to the control end of the second switch tube Q2, the output end 132 of the first control module 13 is connected to the control end of the first switch tube Q1, the positive electrode of the first voltage source V1 is connected to the positive electrode of the first diode D1, the negative electrode of the first diode D1 is connected to the first end of the first switch tube Q1 and the first end of the first resistor R1, the second end of the first switch tube Q1 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the first end of the third resistor R3 and the first end of the second switch tube Q2, the second end of the second switch tube Q2 is grounded, the second end of the third resistor R3 and the first end of the first resistor R1 are connected to the first end of the output module Q14 End 143; the resistance value of the second resistor R2 is smaller than that of the first resistor R1;

the first control module 13 and the first level shift module 12 control the output 143 of the first sending module 14 to be in a weakly driven high level state in the first data transmission period, specifically:

when the duty ratio of the signal pulse output by the first driving signal source 11 is greater than the first threshold, the first control module 13 controls the first switch Q1 to turn off, if the signal pulse output by the first driving signal source 11 is at a continuous high level in the first data transmission period, the first level shift module 12 controls the second switch Q2 to turn off in the first data transmission period, and the output 143 of the first sending module 14 is at a weakly-driven high level state in the first data transmission period.

Optionally, the first control module 13 and the first level shift module 12 control the output end 144 of the first sending module 14 to be in a high-level state of strong driving in the first data transmission period, specifically:

when the duty ratio of the signal pulse output by the first driving signal source 11 is smaller than the first threshold, the first control module 13 controls the first switching tube Q1 to be turned on; if the signal pulse output by the first driving signal source 11 is at a continuous high level in the first data transmission period, the first level shift module 12 controls the second switch Q2 to be turned off, and the output terminal 143 of the first sending module 14 is in a high level state of strong driving in the first data transmission period.

Optionally, the first control module 13 and the first level shift module 12 control the output 143 of the first sending module 14 to be in a low-level state of strong driving in a low-level pulse period of the first data transmission cycle, specifically:

when the duty ratio of the signal pulse output by the first driving signal source 11 is smaller than the first threshold, the first control module 13 controls the first switching tube Q1 to be turned on; if the signal pulse output by the first driving signal source 11 has a low level pulse period in the first data transmission cycle, the first level shift module 12 controls the second switch tube Q2 to be turned on in the low level pulse period in the first data transmission cycle, and the output terminal 143 of the first sending module 14 is in a low level state of strong driving in the low level pulse period in the first data transmission cycle.

The first switch tube Q1 and the second switch tube Q2 may be triodes or Metal-Oxide-Semiconductor Field-Effect transistors (MOSFETs), which are abbreviated as MOS tubes. For convenience of illustration, the first switch Q1 of fig. 3 is exemplified by a PNP type triode, and the second switch Q2 is exemplified by an NPN type triode. Due to the level isolation capability of the triode, the surge protection capability of the wiegand interface circuit 100 can be improved.

The first diode D1 is a unidirectional device, which can avoid the risk that the wiegand interface circuit 100 is filled with high voltage due to wrong wiring.

In the embodiment of the present application, the first driving signal source 11 may output signal pulses. As shown in fig. 4, the signal pulse is composed of periodic high-level periods and low-level periods. The duty cycle of the signal pulses is defined as: the proportion of the high level period within one signal pulse period. Fig. 4 shows signal pulses of two different duty cycles: signal pulses with a duty cycle of 50% and signal pulses with a duty cycle of 90%.

High level refers to a high voltage as opposed to low level. In the logic level, when the level is higher than the high voltage Vih, the in level is considered as a high level. When the level is lower than the low voltage Vil, the level is considered as high.

The low voltage Vil is the maximum voltage allowed when the input or output of the logic gate is guaranteed to be low, and when the level is lower than Vil, the level is considered to be low.

The high voltage Vih ensures a minimum voltage allowed when the input or output of the logic gate is high, and when the level is higher than Vih, the level is considered high.

In a digital logic circuit, a low level indicates 0, and a high level indicates 1. Generally, the low level is 0-0.3V and the high level is 1.5-5V. In digital circuits, the high and low of a voltage are represented by logic levels. The logic level includes both a high level and a low level. The digital circuits formed by different components have different logic levels corresponding to voltages.

In Transistor-Transistor Logic (TTL) circuits, a voltage greater than 1.5 volts is specified as a Logic high level, represented by the numeral 1; a voltage of less than 0.3 volts is defined as a logic low level, represented by the number 0. The instant (time) at which the digital level changes from low (digital "0") to high (digital "1") is called the rising edge. The instant (time) at which the digital level changes from high (digital "1") to low (digital "0") is called a rising edge.

For example, the high level voltage may be 3.3V or 5V. The voltage of the low level may be 0V.

The voltage of the first voltage source V1 may be greater than the high level voltage of the first driving signal source 11, and the high voltage conforming to the wiegand interface circuit is realized by low voltage driving. For example, the high level voltage of the first driving signal source 11 is 1.8V, and the voltage of the first voltage source V1 is 5V. For another example, the high level voltage of the first driving signal source 11 is 3.3V, and the voltage of the first voltage source V1 is 5V.

The output of the wiegand interface circuit 100 is composed of a DATA line 1(DATA1) and a DATA line 2(DATA 2). Data line 1 is the output 143 of the first sending module 14, and data line 2 is the output 243 of the second sending module 24. When the wiegand interface circuit 100 outputs data "0", a low-level pulse (i.e., a negative pulse) appears on the data line 1. When the wiegand interface circuit 100 outputs data "1", a low-level pulse (i.e., a negative pulse) appears on the data line 2. When the wiegand interface circuit 100 is in an idle state, the data lines 1 and 2 are both at a high level.

In the case where the output 143 of the first sending module 14 transmits a continuous high level, and the output 243 of the second sending module 24 transmits a continuous high level, the wiegand interface circuit 100 is in an idle state. In the case that the output terminal 143 of the first sending module 14 transmits a low level pulse and the output terminal 243 of the second sending module 24 transmits a continuous high level, the wiegand interface circuit is in a data transmission state and transmits data "0". In the case that the output terminal 143 of the first sending module 14 transmits a continuous high level and the output terminal 243 of the second sending module 24 transmits a low level pulse, the wiegand interface circuit is in a data transmission state and transmits data "1".

It can be seen that whether the wiegand interface circuit 100 is in the idle state or the data transmission state depends on the level output from the output 143 of the first transmitting module 14 of the first interface circuit 10 and the level output from the output 243 of the first transmitting module 24 of the second interface circuit 20.

For convenience of explanation, only the level change of the output terminal 143 of the first transmitting module 14 of the first interface circuit 10 when the wiegand interface circuit 100 is in different states will be discussed below. Similarly, the level output by the output terminal 243 of the first sending module 24 of the second interface circuit 20 is not described in detail in this embodiment of the application.

In order to realize that the wiegand interface circuit is in the idle state, the output 143 of the first transmitting module 14 needs to transmit a continuous high level. The duty ratio of the signal pulse output by the first drive signal source 11 needs to be larger than the first threshold. Specifically, for example, when the output terminal 143 of the first transmitting module 14 transmits a continuous high level, the duty ratio of the signal pulse output by the first driving signal source 11 may be 100%. In order to realize that the Wiegand interface circuit transmits data '0' in a data transmission state. The output 143 of the first transmit module 14 needs to transmit a low level pulse. The duty ratio of the signal pulse output by the first drive signal source 11 needs to be smaller than the first threshold. Specifically, for example, when the output terminal 143 of the first transmitting module 14 transmits a low-level pulse, the duty ratio of the signal pulse output by the first driving signal source 11 may be 50%.

The magnitude of the first threshold may be related to parameter settings of the first control module 13, see below. For example, the first threshold is 95%.

The first control module 13 has a function of controlling the first switching tube Q1 to be turned off when the duty ratio of the signal pulse output by the first driving signal source 11 is greater than the first threshold value. The first level shift module 12 has a function of controlling the second switch Q2 to be turned off when the signal pulse output by the driving signal source 11 is at a high level.

In order to better understand the operation principle of the first interface circuit 10 of the wiegand interface circuit 100 of the present application, the following description will take as an example that the duty cycle of the signal pulse output by the first driving signal source 11 is 100%, the voltage of the first voltage source V1 is 5V, the first resistance is 1 kilo ohm (10K Ω), the second resistance is 240 ohm (Ω), and the third resistance is 10 Ω.

When the wiegand interface circuit 100 is in an idle state, the duty ratio of the signal pulse output by the first driving signal source 11 is 100%, the first control module 13 controls the first switching tube Q1 to be turned off, and the first level conversion module 12 controls the second switching tube Q2 to be turned off. Since the first switch Q1 and the second switch Q2 are both turned off, the second resistor R2 and the third resistor R3 do not participate in the output loop of the first transmitting module 14. The output loop of the first transmitting module 14 includes: the circuit comprises a first voltage source V1, a first diode D1 and a first resistor R1. At this time, the output terminal 143 of the first transmitting module 14 is pulled up to the positive voltage of the first voltage source V1 through the first resistor R1 and the first diode D1, the voltage of the output terminal 143 of the first transmitting module 14 is 5V, and the output is at a high level. Since the resistance of the first resistor R1 is 10K Ω, when the wiegand interface circuit 100 is connected to other wiegand interfaces, the first voltage source V1 is grounded through the first diode D1 and the first resistor R1, and at this time, considering that the first diode D1 has a threshold of on-voltage, the driving current of the first interface circuit 10 is less than 0.5mA (5V/10K Ω). Therefore, when the wiegand interface circuit is in an idle state, the wiegand interface circuit has leakage of 0.5mA grade, namely, the leakage current is less than 0.5mA, and the wiegand interface circuit is in a weak driving state. At this time, the output terminal of the first transmitting module 14 is in a high state of weak driving. If the wiegand interface circuit 100 of the embodiment of the present application is not used, the output end of the first sending module 14 is in a high-level state of strong driving when the wiegand interface circuit 100 is in an idle state, when the wiegand interface circuits between devices are connected with each other, a bus leakage problem exists, the strong leakage of the wiegand interface circuit 100 may cause a problem that the power consumption of the leakage end is large and the device is in failure due to stress loss, and a problem that the power receiving end is in a system power timing sequence and a power signal are abnormal due to power receiving, and the system is in a halt state, so that the system cannot be turned on or turned off due to power receiving may also be caused. By implementing the wiegand interface circuit 100 according to the embodiment of the present application, the above-mentioned problems can be avoided.

When the wiegand interface circuit 100 transmits data "1" in the first data transmission period, the output terminal 143 of the first sending module 14 needs to transmit a continuous high level in the first data transmission period. The duty ratio of the signal pulse output by the first driving signal source 11 is smaller than the first threshold, the first control module 13 controls the first switch Q1 to be turned on, and if the signal pulse is in the high level duration in the first data transmission cycle, the first level shift module 12 controls the second switch Q2 to be turned off. Since the first switch Q1 is turned on and the second switch Q2 is turned off, the second resistor R2 and the third resistor R3 participate in the output loop of the transmitting module 14. The output loop of the first sending module 14 includes: the circuit comprises a first voltage source V1, a first diode D1, a first resistor R1, a second resistor R2 and a third resistor R3. At this time, the output terminal 143 of the first transmitting module 14 is pulled up to the positive voltage of the first voltage source V1 through the first resistor R1 and the first diode D1, the voltage of the output terminal 143 of the first transmitting module 14 is 5V, and the output is at a high level. Since the resistance of the first resistor R1 is 10K Ω, when the wiegand interface circuit 100 is connected to other wiegand interfaces, the first voltage source V1 is grounded via the first diode D1 and the parallel resistor (the second resistor R2 and the third resistor R3 are connected in series and then connected to the first resistor R1), and at this time, the driving current of the first interface circuit 10 is about 20mA (5V/250 Ω), which is in a strong driving state. The driving current of the wiegand interface circuit 10 can reach 20mA, and the requirement of transmitting data "1" is met, and at this time, the output end of the first sending module 14 is in a high-level state of strong driving.

When the wiegand interface circuit transmits data "0" in the first data transmission cycle, the duty ratio of the signal pulse output by the first driving signal source 11 is smaller than the first threshold, the first control module 13 controls the first switching tube Q1 to be turned on, and if the signal pulse has a low level pulse period in the first data transmission cycle and is in the low level period, the first level conversion module 12 controls the second switching tube Q2 to be turned on. Since the first switch Q1 and the second switch Q2 are both turned on, the second resistor R2 and the third resistor R3 participate in the output loop of the first transmitting module 14. The output loop of the first sending module 14 includes: the circuit comprises a first voltage source V1, a first diode D1, a first resistor R1, a second resistor R2, a third resistor R3 and ground. At this time, the output terminal 143 of the first transmitting module 14 is pulled down to the ground through the third resistor R3, the voltage of the output terminal 143 of the first transmitting module 14 is 0V, and the output is at a low level. The first voltage source V1 is connected to the ground through the first diode D1 and the parallel resistor (the second resistor R2 and the third resistor R3 are connected in series and then connected to the first resistor R1), and at this time, the driving current of the first interface circuit 10 is about 20mA (5V/250 Ω), which is in a strong driving state. The driving current of the wiegand interface circuit 10 can reach 20mA, and the requirement of transmitting data 0 is met. At this time, the output terminal of the first transmitting module 14 is in a low state of strong driving.

In the wiegand interface circuit in the embodiment of the application, two switching tubes are adopted in the first sending module to control the output of the sending module, and as the resistance value of the second resistor is smaller than that of the first resistor, the wiegand interface circuit is driven to be in an idle state under the condition that the duty ratio of signal pulses output by the first driving signal source is larger than a first threshold value, so that the output end of the first sending module is in a weakly-driven high-level state, the situation that the wiegand interface circuit is in the weakly-driven high-level state in the idle state is ensured, the driving current is small, and when wiegand interfaces between devices are connected with each other, the problem of bus electric leakage of the wiegand interface circuit can be avoided.

Referring to fig. 5, fig. 5 is a schematic structural diagram of another first interface circuit according to an embodiment of the present disclosure. As shown in fig. 5, the first interface circuit 10 may include a first driving signal source 11, a first level shift module 12, a first control module 13, and a first transmitting module 14; the first transmitting module 14 comprises a first voltage source V1, a first diode D1, a first switch tube Q1, a second switch tube Q2, a first resistor R1, a second resistor R2 and a third resistor R3; the first level shift module 12 comprises a second voltage source V2, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and a third switching tube Q3; the first control module 13 includes a second diode D2, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a first capacitor C1, a fourth switch tube Q4, and a fifth switch tube Q5.

The positive electrode of the first driving signal source 11 is connected to the input end 121 of the first level shift module 12 and the input end 131 of the first control module 13, the output end 122 of the first level shift module 12 is connected to the control end of the first second switch tube Q2, the output end 132 of the first control module 13 is connected to the control end of the first switch tube Q1, the positive electrode of the first voltage source V1 is connected to the positive electrode of the first diode D1, the negative electrode of the first diode D1 is connected to the first end of the first switch tube Q1 and the first end of the first resistor R1, the second end of the first switch tube Q1 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the first end of the third resistor R3 and the first end of the second switch tube Q2, the second end of the second switch tube Q2 is grounded, and the first end of the third resistor R3 and the first end of the first resistor R1 are connected to the first end of the sending module 14 Output 143 of the first transistor; the resistance value of the second resistor R2 is smaller than that of the first resistor R1;

a positive electrode of the second voltage source V2 is connected to a first end of the fourth resistor R4, a second end of the fourth resistor R4 is connected to a positive electrode of the first driving signal source 11 and a first end of the fifth resistor R5, a second end of the fifth resistor R5 is connected to a control end of the third switching tube Q3, a first end of the third switching tube Q3 is connected to a first end of the sixth resistor R6 and a first end of the seventh resistor R7, a second end of the sixth resistor R6 is connected to a negative electrode (a connection line is not shown in fig. 5) of the first diode D1, a second end of the third switching tube Q3 is grounded, and a second end of the seventh resistor R7 is connected to a control end of the second switching tube Q2;

a positive electrode of the second diode D2 is connected to a positive electrode of the driving signal source 11 and a first terminal of the eighth resistor R8, a negative electrode of the second diode D2 is connected to a second terminal of the eighth resistor R8, a first terminal of the first capacitor C1 and a first terminal of the ninth resistor R9, a second terminal of the first capacitor C1 is grounded, a second terminal of the ninth resistor R9 is connected to a first terminal of the tenth resistor R10 and a control terminal of the fourth switch Q4, a second terminal of the tenth resistor R10 and a second terminal of the fourth switch Q4 are grounded, a first terminal of the fourth switch Q4 is connected to a first terminal of the eleventh resistor R11 and a control terminal of the fifth switch Q5, a second terminal of the eleventh resistor R11 is connected to a first terminal of the twelfth resistor R12 and a negative electrode of the first diode R1 (a connection line is not shown in fig. 5), a second end of the twelfth resistor R12 is connected to a first end of the thirteenth resistor R13 and a first end of the fifth switching tube Q5, a second end of the fifth switching tube Q5 is connected to a first end of the third switching tube Q3, and a second end of the thirteenth resistor R13 is connected to a control end of the first switching tube Q1;

when the duty ratio of the signal pulse output by the first driving signal source 11 is greater than the first threshold, the first control module 13 controls the first switch Q1 to turn off, if the signal pulse is in a high level period, the first level shift module 12 controls the second switch Q2 to turn off, and the output 143 of the first transmitting module 14 is in a weakly driven high level state.

In the embodiment of the present application, the voltage of the second voltage source V2 is less than the voltage of the first voltage source V1, and the voltage of the second voltage source V2 may be equal to the high level voltage of the first driving signal source 11, so as to implement the high voltage conforming to the wiegand interface circuit by low voltage driving. For example, the high level voltage of the first driving signal source 11 is 1.8V, the voltage of the second voltage source V2 is 1.8V, and the voltage of the first voltage source V1 is 5V. For another example, the high level voltage of the first driving signal source 11 is 3.3V, the voltage of the second voltage source V2 is 3.3V, and the voltage of the first voltage source V1 is 5V.

The first level shift module 12 and the first control module 13 may be in communication. The second terminal of the fifth switch Q5 of the first control module 13 is connected to the first terminal of the third switch Q3 of the first level shifter module 12. The first level shifter module 12 may control the fifth switch Q5 to be turned on or off.

The magnitude of the first threshold may be related to parameters of the eighth resistor R8 and the first capacitor C1 in the control module 13. The first capacitor C1 is charged when the signal pulse output by the first driving signal source 11 is in the high level period, and the first capacitor C1 is discharged through the second diode D2 when the signal pulse output by the first driving signal source 11 is in the low level period. During the charging process of the first capacitor C1, the voltage at the first terminal of the first capacitor C1 continuously rises, and when the voltage at the first terminal of the first capacitor C1 rises to the lowest voltage required for driving the fourth switch Q4, the fourth switch Q4 is turned on. During the discharging process of the first capacitor C1, the voltage at the first terminal of the first capacitor C1 continuously drops, and when the voltage at the first terminal of the first capacitor C1 drops to the lowest voltage required for driving the fourth switching tube Q4, the fourth switching tube Q4 is turned off.

The first threshold is related to the product of R8 and C1, the duration of the low level period of the signal pulse output by the first driving signal source 11 in one cycle, and the turn-on voltage of the fourth switching tube Q4.

Specifically, during the discharging process of the first capacitor C1, if the product of R8 and C1 is larger, the duration of the signal pulse output by the first driving signal source 11 in the low level period in one cycle is smaller, and the on-voltage of the fourth switch tube Q4 is smaller, the slower the voltage attenuation of the first end of the first capacitor C1 is, and the smaller the corresponding first threshold value can be set; similarly, if the smaller the product of R8 and C1, the longer the duration of the low level period of the signal pulse output by the first driving signal source 11 in one cycle, and the larger the on-voltage of the fourth switching tube Q4, the faster the voltage at the first end of the first capacitor C1 decays, the larger the corresponding first threshold value can be set.

The first level shift module 12 may implement a level flipping function. Specifically, the first level shifter module 12 may control the second switch Q2 to be turned on or off to implement level inversion of the first end of the second switch Q2.

Optionally, as shown in fig. 5, when the output of the first driving signal source 11 is inverted from a low level to a high level, the voltage at the second end of the fourth resistor R4 drives the third switching tube Q3 to turn on through the fifth resistor R5, so as to realize the inversion of the voltage at the first end of the third switching tube Q3 from the high level to the low level, and the voltage at the first end of the third switching tube Q3 drives the second switching tube Q2 to turn off through the seventh resistor R7, so as to realize the inversion of the voltage at the first end of the second switching tube Q2 from the low level to the high level.

Optionally, as shown in fig. 5, when the output of the first driving signal source 11 is flipped from a high level to a low level, the voltage at the second end of the fourth resistor R4 drives the third switching tube Q3 to turn off through the fifth resistor R5, so as to flip the voltage at the first end of the third switching tube Q3 from the low level to the high level, and the voltage at the first end of the third switching tube Q3 drives the second switching tube Q2 to turn on through the seventh resistor R7, so as to flip the voltage at the first end of the second switching tube Q2 from the high level to the low level.

Optionally, as shown in fig. 5, during the power-up phase of the first driving signal source 11, the voltage at the second end of the fourth resistor R4 is pulled up to the positive electrode of the second voltage source V2 through the fourth resistor R4.

In the embodiment of the present application, in order to avoid voltage fluctuation of the first driving signal source 11 in the power-on stage, the second voltage source V2 ensures that the first driving signal source 11 is at a high level in the initial state, and prevents the wiegand interface circuit from generating an error data bit in the initial state.

The control module 13 may control the first switch Q1 to be turned on or off.

Optionally, as shown in fig. 5, when the duty ratio of the signal pulse output by the first driving signal source 11 is greater than a first threshold, the voltage of the first end of the first capacitor C1 controls the fourth switching tube Q4 to be turned on through the ninth resistor R9, so that the fifth switching tube Q5 is turned off, and the voltage of the first end of the fifth switching tube Q5 controls the first switching tube Q1 to be turned off through the thirteenth resistor R13.

Optionally, as shown in fig. 5, when the duty ratio of the signal pulse output by the first driving signal source 11 is smaller than the first threshold and the signal pulse is in the high level period, the voltage of the first end of the first capacitor C1 controls the fourth switching tube Q4 to turn off through the ninth resistor R9, so that the fifth switching tube Q5 is turned on, and the voltage of the first end of the fifth switching tube Q5 controls the first switching tube Q1 to turn on through the thirteenth resistor R13.

Optionally, as shown in fig. 5, when the duty ratio of the signal pulse output by the first driving signal source 11 is smaller than the first threshold and the signal pulse is in the low level period, the voltage of the first end of the first capacitor C1 controls the fourth switching tube Q4 to be turned off through the ninth resistor R9, so that the fifth switching tube Q5 is turned on, and the voltage of the first end of the fifth switching tube Q5 controls the first switching tube Q1 to be turned off through the thirteenth resistor R13.

Optionally, as shown in fig. 5, when the first driving signal source 11 outputs a low level, the voltage of the first end of the first capacitor C1 controls the fourth switching tube Q4 to be turned off through the ninth resistor R9, so that the fifth switching tube Q5 is turned on, and the voltage of the first end of the fifth switching tube Q5 controls the first switching tube Q1 to be turned off through the thirteenth resistor R13.

Optionally, the first switching tube Q1 includes a first transistor, the second switching tube Q2 includes a second transistor, the third switching tube Q3 includes a third transistor, the fourth switching tube Q4 includes a fourth transistor, and the fifth switching tube Q5 includes a first metal oxide semiconductor field effect transistor.

Specifically, as shown in fig. 5, the first switching tube Q1 (i.e., the first transistor) is a PNP transistor, the second switching tube Q2 (i.e., the second transistor) is an NPN transistor, the third switching tube Q3 (i.e., the third transistor) is an NPN transistor, the fourth switching tube Q4 (i.e., the fourth transistor) is an NPN transistor, and the fifth switching tube Q5 (i.e., the first mosfet) is an N-type MOS transistor.

The control end of the first switch tube Q1 is a base electrode of the first triode, the first end of the first switch tube Q1 is an emitter electrode of the first triode, and the second end of the first switch tube Q1 is a collector electrode of the first triode. The control end of the second switch tube Q2 is a base electrode of the second triode, the first end of the second switch tube Q2 is a collector electrode of the second triode, and the second end of the second switch tube Q2 is an emitter electrode of the second triode. The control end of the third switching tube Q3 is a base electrode of the third triode, the first end of the third switching tube Q3 is a collector electrode of the third triode, and the second end of the third switching tube Q3 is an emitter electrode of the third triode. The control end of the fourth switching tube Q4 is a base electrode of the fourth triode, the first end of the fourth switching tube Q4 is a collector electrode of the fourth triode, and the second end of the fourth switching tube Q2 is an emitter electrode of the fourth triode.

Optionally, a voltage corresponding to the high level of the first driving signal source is equal to a voltage of the second voltage source.

Optionally, the voltage of the first voltage source is greater than the voltage corresponding to the high level of the first driving signal source, and the voltage of the first voltage source is greater than the voltage of the second voltage source.

In the embodiment of the application, the high voltage (for example, 5V) conforming to the wiegand interface circuit can be realized by low-voltage (for example, 1.8V or 3.3V) driving. For example, the high level voltage of the first driving signal source 11 is 1.8V, the voltage of the second voltage source V2 is 1.8V, and the voltage of the first voltage source V1 is 5V. For another example, the high level voltage of the first driving signal source 11 is 3.3V, the voltage of the second voltage source V2 is 3.3V, and the voltage of the first voltage source V1 is 5V.

For example, referring to fig. 6a, fig. 6a is a schematic diagram of a specific device parameter including a first interface circuit provided on the basis of fig. 5. Where, R1 ═ 10K Ω, R2 ═ 240 Ω, R3 ═ 10 Ω, R4 ═ 10K Ω, R5 ═ 10K Ω, R6 ═ 10K Ω, R7 ═ 10K Ω, R8 ═ 100K Ω, R9 ═ 10K Ω, R10 ═ 20K Ω, R11 ═ 10K Ω, R12 ═ 10K Ω, and R13 ═ 10K Ω. C1 ═ 47 nF. The model of Q1 is 2N3906, the models of Q2, Q3 and Q4 are all 2N3904, and the model of Q5 is AO 6408. The voltage of the first voltage source V1 is 5V, and the voltage of the second voltage source V2 is 1.8V. The duty ratio of the signal pulse output by the first driving signal source 11 in the idle state is 100%, and the level is 1.8V. The high level of the signal pulse output by the first driving signal source 11 in the data transmission state is 1.8V, the low level is 0V, the pulse period is 1600 μ s, and the duration of the high level period is 1450 μ s and the duration of the low level period is 150 μ s in one pulse period. The signal pulses output by the first drive signal source 11 are shown in fig. 6 b.

The first interface circuit of fig. 6a can implement a 5V high voltage that conforms to the wiegand interface circuit by a 1.8V low voltage drive.

Fig. 6c is a simulation diagram of an output signal pulse of the first interface circuit shown in fig. 6a and a simulation diagram of a corresponding signal pulse output by the first driving signal source.

For example, referring to fig. 7a, fig. 7a is a schematic diagram of a specific device parameter including a first interface circuit provided on the basis of fig. 5. Where, R1 ═ 10K Ω, R2 ═ 240 Ω, R3 ═ 10 Ω, R4 ═ 10K Ω, R5 ═ 10K Ω, R6 ═ 10K Ω, R7 ═ 10K Ω, R8 ═ 100K Ω, R9 ═ 50K Ω, R10 ═ 20K Ω, R11 ═ 10K Ω, R12 ═ 10K Ω, and R13 ═ 10K Ω. C1 ═ 47 nF. The model of Q1 is 2N3906, the models of Q2, Q3 and Q4 are all 2N3904, and the model of Q5 is AO 6408. The voltage of the first voltage source V1 is 5V, and the voltage of the second voltage source V2 is 3.3V. The duty ratio of the signal pulse output by the first driving signal source 11 in the idle state is 100%, and the level is 3.3V. The high level of the signal pulse output by the first driving signal source 11 in the data transmission state is 3.3V, the low level is 0V, the pulse period is 1600 μ s, and the duration of the high level period is 1450 μ s and the duration of the low level period is 150 μ s in one pulse period. The signal pulses output by the first drive signal source 11 are shown in fig. 7 b.

The first interface circuit of fig. 7a can implement a 5V high voltage (e.g., 5V) conforming to the first interface circuit by a 3.3V low voltage drive.

It should be noted that fig. 6a and fig. 7a are schematic diagrams illustrating a possible first interface circuit including device parameters according to an embodiment of the present application, and parameters such as capacitance, resistance, and switching tube may be of other types.

It should be noted that the second interface circuit 20 in fig. 1 has a similar function to the first interface circuit 10, and both of them form a wiegand interface circuit 100. The first interface circuit 10 corresponds to the data line 1, the second interface circuit 20 corresponds to the data line 2, and the second interface circuit 20 has the same internal design as the first interface circuit 10. The structures of the modules in the second interface circuit 20 in fig. 1 may refer to the structures of the modules in the first interface circuit 10 in fig. 5, and the specific component parameters thereof may refer to the parameters of the components in fig. 7a, which are not described herein again.

Referring to fig. 8, fig. 8 is a schematic structural diagram of a communication device according to an embodiment of the present disclosure. As shown in fig. 8, the communication device 300 may include a wiegand interface circuit 100 and a driver chip 200, wherein the first driving signal source 11 and the second driving signal source 21 in the wiegand interface circuit 100 are provided by the driver chip 200.

The driving Chip 20 may be a Microprocessor (MCU) or a System On Chip (SOC).

The communication device 100 may be used in the field of security control, such as a building entrance guard, a human recognition terminal device, an Internet Protocol Camera (IPC), and the like.

In the communication device in the embodiment of the application, under the condition that the duty ratio of the signal pulse output by the first driving signal source is greater than the first threshold and the duty ratio of the signal pulse output by the second driving signal source is greater than the second threshold, the wiegand interface circuit is driven to be in the idle state, so that the output end of the first sending module and the output end of the second sending module are in the high-level state of weak driving, the situation that the wiegand interface circuit is in the high-level state of weak driving in the idle state is ensured, the driving current is low, and when the wiegand interfaces between the devices are connected with each other, the problem of bus leakage of the wiegand interface circuit can be avoided. In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented.

Claims

1. A wiegand interface circuit, comprising:

a first interface circuit and a second interface circuit;

the first interface circuit comprises a first driving signal source, a first level conversion module, a first control module and a first sending module;

the second interface circuit comprises a second driving signal source, a second level conversion module, a second control module and a second sending module;

2. The wiegand interface circuit according to claim 1, wherein said first transmitting module comprises a first voltage source, a first diode, a first switch tube, a second switch tube, a first resistor, a second resistor and a third resistor;

3. The circuit according to claim 2, wherein the first control module and the first level shift module control the output terminal of the first sending module to be in a high-level state of strong driving in the first data transmission period, specifically:

4. The circuit of claim 2 or 3, wherein the first level shift module comprises a second voltage source, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and a third switch tube; wherein:

5. The circuit of claim 4, wherein the first control module comprises a second diode, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a first capacitor, a fourth switch tube, and a fifth switch tube, wherein:

6. The circuit according to claim 5, wherein when the output of the first driving signal source is flipped from a low level to a high level, the voltage at the second end of the fourth resistor drives the third switching tube to turn on through the fifth resistor, so as to flip the voltage at the first end of the third switching tube from the high level to the low level, and the voltage at the first end of the third switching tube drives the second switching tube to turn off through the seventh resistor, so as to flip the voltage at the first end of the second switching tube from the low level to the high level;

7. The circuit of claim 5, wherein during a power-up phase of the first driving signal source, a voltage at the second end of the fourth resistor is pulled up to the positive pole of the second voltage source through the fourth resistor.

8. The circuit according to claim 5, wherein when the duty cycle of the signal pulse output by the first driving signal source is greater than a first threshold, the voltage of the first terminal of the first capacitor controls the fourth switching tube to be turned on through the ninth resistor, so that the fifth switching tube is turned off, and the voltage of the first terminal of the fifth switching tube controls the first switching tube to be turned off through the thirteenth resistor;

9. The circuit according to any one of claims 5 to 8, wherein a voltage corresponding to a high level of the first driving signal source is equal to a voltage of the second voltage source;

10. The circuit of claim 4, wherein the high level of the first driving signal source corresponds to a voltage equal to the voltage of the second voltage source;

11. A communication device comprising a driver chip and the wiegand interface circuit according to any one of claims 1-10, wherein the first driving signal source and the second driving signal source in the wiegand interface circuit are provided by the driver chip.