CN217935589U - IIC bus level conversion circuit and electronic equipment - Google Patents

Abstract

The application discloses a level conversion circuit of an IIC bus and electronic equipment. The level conversion circuit includes two conversion circuits connected to a serial clock line and a serial data line in the IIC bus, respectively. Because the two conversion circuits can convert the levels of different nodes on the IIC bus, normal communication of clock signals and data signals between devices connected with the IIC bus and having different working levels can be ensured.

Description

IIC bus level conversion circuit and electronic equipment

Technical Field

The present disclosure relates to electronic technologies, and in particular, to a level shifter circuit for an inter-integrated circuit (IIC) bus and an electronic device.

Background

The IIC bus is a bidirectional two-wire synchronous serial bus that includes a serial data line (SDA) and a Serial Clock Line (SCL). Different devices in the electronic equipment, such as a controller and a memory, can communicate data through the IIC bus.

If the operating levels of the two devices connected to the IIC bus are different, the two electronic devices cannot directly communicate data through the IIC bus.

SUMMERY OF THE UTILITY MODEL

The application provides a power protection circuit and electronic equipment, which can solve the problem that the function of the power protection circuit in the related art is single. The technical scheme is as follows:

in one aspect, there is provided a level conversion circuit of an IIC bus including a serial clock line and a serial data line, the level conversion circuit including: a first conversion circuit connected to the serial clock line and a second conversion circuit connected to the serial data line;

each of the first conversion circuit and the second conversion circuit includes: a first conversion sub-circuit and a second conversion sub-circuit;

the first converting sub-circuit is respectively connected to a first power end, a second power end, a first node and a second node, and is configured to pull down a level of the second node to a first level if the level of the first node is the first level, and pull up the level of the second node to a third level if the level of the first node is the second level;

the second converting sub-circuit is respectively connected to the first power source terminal, the second power source terminal, the first node, and the second converting sub-circuit is configured to, if the level of the second node is the first level, pull down the level of the first node to the first level, and if the level of the second node is the third level, pull up the level of the first node to the second level under the driving of the first power source terminal;

wherein the second level and the third level are both high levels relative to the first level, a first node and a second node in the first conversion circuit are both connected to the serial clock line, and a first node and a second node in the second conversion circuit are both connected to the serial data line.

Optionally, the first conversion sub-circuit comprises: a first transmission sub-circuit and a first pull-up sub-circuit;

the first transmission sub-circuit is respectively connected to the first power source terminal, the first node, and the second node, and the first transmission sub-circuit is configured to pull down a level of the second node to the first level if the level of the first node is the first level;

the first pull-up sub-circuit is connected to the second power source terminal and the second node, and the first pull-up sub-circuit is configured to pull up a level of the second node to the third level under the driving of the second power source terminal.

Optionally, the first transmission sub-circuit comprises: a first switching transistor and a first diode;

a gate of the first switching transistor is connected to the first power terminal, a first pole of the first switching transistor is connected to the first node, a second pole of the first switching transistor is connected to a cathode of the first diode, and an anode of the first diode is connected to the second node.

Optionally, the first pull-up sub-circuit comprises: a first resistor;

one end of the first resistor is connected to the second node, and the other end of the first resistor is connected to the second power supply terminal.

Optionally, the first conversion circuit further includes the second conversion sub-circuit.

Optionally, the second conversion sub-circuit comprises: a second transmission sub-circuit and a second pull-up sub-circuit;

the second transmission sub-circuit is respectively connected to the second power end, the first node, and the second transmission sub-circuit is configured to pull down the level of the first node to the first level if the level of the second node is the first level;

the second pull-up sub-circuit is respectively connected to the first power end and the first node, and the second pull-up sub-circuit is configured to pull up a level of the first node to the second level under the driving of the first power end.

Optionally, the second transmission sub-circuit comprises: a second diode and a second switching transistor;

an anode of the second diode is connected to the first node, a cathode of the second diode is connected to a first pole of the second switching transistor, a gate of the second switching transistor is connected to the second power source terminal, and a second pole of the second switching transistor is connected to the second node.

Optionally, the second switch transistor and the first switch transistor in the first transmission sub-circuit are both N-type (MOS) transistors.

Optionally, the second pull-up sub-circuit comprises: a second resistor; one end of the second resistor is connected to the first node, and the other end of the second resistor is connected to the first power supply terminal.

Optionally, the resistance of the second pull-up sub-circuit is equal to the resistance of the first pull-up sub-circuit in the first conversion sub-circuit.

In another aspect, an electronic device is provided, which includes: an IIC bus, the level shifter circuit, the first device, and the second device as described above;

the IIC bus comprises a serial clock line and a serial data line;

a first node and a second node in a first conversion circuit in the level conversion circuit are both connected with the serial clock line, and a first node and a second node in a second conversion circuit in the level conversion circuit are both connected with the serial data line;

the first device is respectively connected with a first node in the first conversion circuit and a first node in the second conversion circuit;

the second device is connected to a second node in the first conversion circuit and a second node in the second conversion circuit, respectively.

The beneficial effect that technical scheme that this application provided brought includes at least:

the application provides a level conversion circuit of an IIC bus and electronic equipment. The level conversion circuit includes two conversion circuits connected to a serial clock line and a serial data line in the IIC bus, respectively. Because the two conversion circuits can convert the levels of different nodes on the IIC bus, normal communication of clock signals and data signals between devices connected with the IIC bus and having different working levels can be ensured.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a level shift circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a first conversion circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a second conversion circuit according to an embodiment of the present disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, the following detailed description of the embodiments of the present application will be made with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application, and referring to fig. 1, the electronic device includes: IIC bus, level shifter circuit 10, first device 20, and second device 30. Wherein the IIC bus includes a serial clock line SCL and a serial data line SDA.

Referring to fig. 1, a first node P1_1 and a second node P1_2 of a first conversion circuit 11 in a level conversion circuit 10 are both connected to a serial clock line SCL and are used for converting a level on the serial clock line SCL. The first node P2_1 and the second node P2_2 of the second conversion circuit 12 in the level conversion circuit 10 are both connected to the serial data line SDA and are used for converting the level on the serial data line SDA.

The first device 20 is connected to the first node P1_1 of the first conversion circuit 11 and the first node P2_1 of the second conversion circuit 12, respectively. The second device 30 is connected to the second node P1_2 of the first conversion circuit 11 and the second node P2_2 of the second conversion circuit 12, respectively.

In the embodiment of the present application, the first device 20 and the second device 30 may be two devices that need to communicate in an electronic apparatus. Alternatively, the first device 20 may be a Central Processing Unit (CPU) or a micro-controller unit (MCU) in the electronic apparatus, and the second device 30 is any Integrated Circuit (IC) in the electronic apparatus, that is, a device having an IIC interface, and is in data communication with the CPU or the MCU through an IIC bus. For example, the second device 30 may be a memory or a Liquid Crystal Display (LCD) driver.

Optionally, the electronic device may be a device that performs data transmission through an IIC communication protocol, such as a television, a recorder, or a mobile phone, which is not limited herein in this embodiment of the application.

For example, assume that the electronic device is a television, and the first device 20 is a memory in the television. The second device 30 is a display in a television set. The operating level of the memory is typically 3.3 volts (V), and the operating level of the display is typically 5V. The level conversion circuit provided by the embodiment of the application can convert the levels on the serial clock line SCL and the serial data line SDA in the IIC bus, so that video signals can be interacted between a display and a memory.

Fig. 2 is a schematic structural diagram of a level shift circuit of an IIC bus according to an embodiment of the present disclosure, where the level shift circuit may be applied to the electronic device shown in fig. 1. The IIC bus includes a serial clock line SCL and a serial data line SDA. Referring to fig. 2, the level shift circuit 10 includes: a first conversion circuit 11 connected to the serial clock line SCL and a second conversion circuit 12 connected to the serial data line SDA.

The first node P1_1 and the second node P1_2 in the first conversion circuit 11 are both connected to the serial clock line SCL, and the first node P2_1 and the second node P2_2 in the second conversion circuit 12 are both connected to the serial data line SDA. The first conversion circuit 11 and the second conversion circuit 12 each include: a first conversion sub-circuit 110 and a second conversion sub-circuit 120.

As shown in fig. 2, the first converting sub-circuit 110 is connected to the first power supply terminal V1, the second power supply terminal V2, the first node and the second node, respectively. Wherein the voltage of the second power source terminal V2 is higher than the voltage of the first power source terminal V1. For example, the voltage of the first power source terminal V1 may be 3.3V, and the voltage of the second power source terminal V2 may be 5V.

The first converting sub-circuit 110 is configured to: if the level of the first node is the first level, the level of the second node is pulled down to the first level, and if the level of the first node is the second level, the level of the second node is pulled up to the third level under the driving of the second power terminal V2.

Wherein the second level and the third level are both high level with respect to the first level, and the third level is higher than the second level. For example, the first level may be a level having a magnitude of 0V (i.e., a low level), and the second level and the third level may be levels having a magnitude greater than 0V (i.e., a high level). It is to be understood that the magnitude of the second level is positively correlated with the voltage of the first power source terminal V1, and the magnitude of the third level is positively correlated with the voltage of the second power source terminal V2. For example, the second level may have a magnitude of a voltage of the first power source terminal V1 (e.g., 3.3V), and the third level may have a magnitude of a voltage of the second power source terminal V2 (e.g., 5V).

In the embodiment of the present application, the first converting sub-circuit 110 in the first converting circuit 11 connected to the serial clock line SCL is used for converting the level of the clock signal transmitted from the first node P1_1 to the second node P1_ 2. When the clock signal transmitted to the first node P1_1 is a low level signal (i.e., the level of the first node P1_1 is a first level), the first conversion sub-circuit 110 can pull down the level of the second node P1_2 to the same first level as the first node P1_ 1. Thus, the transmission of the clock signal of low level can be realized.

When the clock signal transmitted to the first node P1_1 is a high level signal (i.e., the level of the first node P1_1 is the second level), the first converter sub-circuit 110 can pull up the level of the second node P1_2 to a third level corresponding to the voltage of the second power source terminal V2 under the driving of the second power source terminal V2.

In the present embodiment, the magnitude of the third level may be equal to the voltage of second power supply terminal V2, and the voltage of second power supply terminal V2 may be adapted to the operating level of second device 30. Thus, when the level of the first node P1_1 is the second level, the first converting sub-circuit 110 may pull up the level of the second node P1_2 to a third level adapted to the operating level of the second device 30. Thereby, level conversion and transmission of the high level clock signal of the first node P1_1 to the second node P1_2 can be achieved, thereby achieving high level clock signal transmission of the first device 20 to the second device 30.

The first conversion sub-circuit 110 in the second conversion circuit 12 connected to the serial data line SDA is used to convert the level of the data signal transmitted from the first node P2_1 to the second node P2_ 2. The operation principle of the first converting sub-circuit 110 in the second converting circuit 12 is the same as that of the first converting sub-circuit 110 in the first converting circuit 11. That is, when the data signal transmitted to the first node P2_1 is a low level signal (i.e., the level of the first node P2_1 is the first level), the first converting sub-circuit 110 can pull down the level of the second node P2_2 to the same first level as the first node P2_ 1. Thus, transmission of a low-level data signal can be achieved. When the data signal of the first node P2_1 is a high level signal (i.e., the level of the first node P2_1 is the second level), the first converting sub-circuit 110 may pull up the voltage of the second node P2_2 to a third level adapted to the operating level of the second device 30. Thereby, level conversion and transmission of a high-level data signal can be achieved.

With continued reference to fig. 2, the second converter sub-circuit 120 in the first converter circuit 11 is connected to the first power supply terminal V1, the second power supply terminal V2, the first node P1_1 and the second node P1_2, respectively. The second converting sub-circuit 120 is configured to: if the level of the second node P1_2 is the first level, the level of the first node P1_1 is pulled down to the first level, and if the level of the second node P1_2 is the third level, the level of the first node P1_1 is pulled up to the second level under the driving of the first power terminal V1.

In the embodiment of the present application, the second conversion sub-circuit 120 in the second conversion circuit 11 connected to the serial clock line SCL is used for converting the level of the clock signal transmitted from the second node P1_2 to the first node P1_ 1. When the clock signal transmitted to the second node P1_2 is a low level signal (i.e., when the level of the second node P1_2 is the first level), the second conversion sub-circuit 120 can pull down the level of the first node P1_1 to the same first level as the second node P1_ 2. Thereby, the transmission of the clock signal of the low level of the second node P1_2 to the first node P1_1 can be realized.

When the level of the clock signal transmitted to the second node P1_2 is a high level signal (i.e., the level of the second node P1_2 is a third level), the second converting sub-circuit 120 can pull up the voltage at the first node P1_1 to a second level corresponding to the first power source terminal V1 under the driving of the first power source terminal V1.

In the embodiment of the present application, the magnitude of the second level may be equal to the voltage of the first power supply terminal V1, and the voltage of the first power supply terminal V1 may be adapted to the operating level of the first device 20. Thus, when the level of the second node P1_2 is the third level, the second converting sub-circuit 120 may pull up the level of the first node P1_1 to the second level adapted to the operating level of the first device 20. Thereby, level conversion and transmission of the clock signal of high level of the second node P1_2 to the first node P1_1 can be achieved, thereby achieving high level clock signal transmission of the second device 30 to the first device 20.

The second conversion sub-circuit 120 in the second conversion circuit 12 connected to the serial data line SDA is configured to convert the level of the data signal transmitted from the second node P2_2 to the first node P2_ 1. The operation principle of the second converting sub-circuit 120 in the second converting circuit 12 is the same as that of the second converting sub-circuit 120 in the first converting circuit 11. That is, when the data signal transmitted to the second node P2_2 is a low level signal (i.e., the level of the second node P2_2 is the first level), the second converting sub-circuit 120 can pull down the level of the first node P2_1 to the same first level as the second node P2_ 2. Thus, transmission of a low-level data signal can be achieved. When the data signal of the second node P2_2 is a high level signal (i.e., the level of the second node P2_2 is a third level), the second conversion sub-circuit 120 may pull up the level of the first node P2_1 to a second level adapted to the operating level of the first device 20. Thereby, level conversion and transmission of a data signal of a high level can be achieved.

In summary, the embodiments of the present application provide a level shifter circuit for an IIC bus. The level conversion circuit includes two conversion circuits connected to a serial clock line and a serial data line in the IIC bus, respectively. Because the two conversion circuits can convert the levels of different nodes on the IIC bus, normal communication of clock signals and data signals between devices connected with the IIC bus and having different working levels can be ensured.

Fig. 3 is a schematic structural diagram of a first conversion circuit provided in an embodiment of the present application, and referring to fig. 3, a first conversion sub-circuit 110 in the first conversion circuit includes: a first transmission sub-circuit 111 and a first pull-up sub-circuit 112.

The first transmission sub-circuit 111 is connected to the first power source terminal V1, the first node P1_1 and the second node P1_2, respectively. The first pull-up sub-circuit 112 is connected to the second power source terminal V2 and the second node P1_2, respectively.

The first transmission sub-circuit 111 is configured to: if the level of the first node P1_1 is the first level, the level of the second node P1_2 is pulled down to the first level. The first pull-up sub-circuit 112 is configured to pull up the level of the second node P1_2 to a third level under the driving of the second power source terminal V2 if the level of the first node P1_1 is the second level.

For example, the first transmission subcircuit 111 may be used to: if the level of the first node P1_1 is the first level, a first path between the first node P1_1 and the second node P1_2 is turned on, so that the level of the second node P1_2 is pulled down to the first level; and if the level of the first node P1_1 is the second level, the first path between the first node P1_1 and the second node P1_2 is closed. Accordingly, the first pull-up sub-circuit 112 can pull up the level of the second node P1_2 to the third level when the first path is turned off. The first path is a path between the first node P1_1 and the second node P1_2 through the first transmission sub-circuit 111.

Referring to fig. 3, the first transmission sub-circuit 111 may include: a first switching transistor Q1 and a first diode D1. The Gate (Gate, G) of the first switching transistor Q1 is connected to the first power source terminal V1, the first pole of the first switching transistor Q1 is connected to the first node P1_1, the second pole of the first switching transistor Q1 is connected to the cathode of the first diode D1, and the anode of the first diode D1 is connected to the second node P1_ 2.

The first switch transistor Q1 may be an N-type MOS transistor, the first pole of the first switch transistor Q1 may be a Source (Source, S), and the second pole of the first switch transistor Q1 may be a Drain (Drain, D).

The first pull-up sub-circuit 112 may include: a first resistor R1. One end of the first resistor R1 is connected to the second node P1_2, and the other end of the first resistor R1 is connected to the second power terminal V2. Alternatively, the voltage of the first power source terminal V1 may be 3.3V, and the voltage of the second power source terminal V2 may be 5V.

It is to be understood that when the clock signal transmitted to the first node P1_1 is a low level signal (i.e., the level of the first node P1_1 is a first level), the voltage of the source S of the first switching transistor Q1 is less than the voltage of the gate G. Accordingly, a voltage difference between the gate G and the source S of the first switching transistor Q1 is greater than a threshold voltage of the first switching transistor Q1, and the drain D and the source S of the first switching transistor Q1 are turned on, so that the cathode of the first diode D1 is at the first level. At this time, the level at the second node P1_2 connected to the anode of the first diode D1 is also pulled down to the same first level as the first node P1_ 1. Thereby, the transmission of the clock signal of the low level between the first node P1_1 and the second node P1_2 can be realized.

When the clock signal transmitted to the first node P1_1 is a high level signal (i.e., the level of the first node P1_1 is a second level), the voltage between the gate G and the source S of the first switching transistor Q1 is less than the threshold voltage of the first switching transistor Q1, and the first switching transistor Q1 is turned off. Thus, the first resistor R1 is capable of pulling up the level of the second node P1_2 to a third level corresponding to the second power source terminal V2, driven by the second power source terminal V2. Wherein the third level is adapted to the operating level of the second device 30. Thereby, level conversion and transmission of the clock signal of high level between the first node P1_1 and the second node P1_2 can be achieved.

Referring to fig. 4, the first conversion sub-circuit 110 in the second conversion circuit 12 connected to the serial data line SDA is used to convert the level of the data signal transmitted from the first node P2_1 to the second node P2_ 2. The structure and the operation principle of the first converting sub-circuit 110 in the second converting circuit 12 are the same as those of the first converting sub-circuit 110 in the first converting circuit 11, and are not repeated herein.

With continued reference to fig. 3, the second conversion sub-circuit 120 includes: a second transmission sub-circuit 121 and a second pull-up sub-circuit 122. The second transmitting sub-circuit 121 is connected to the second power source terminal V2, the first node P1_1 and the second node P1_2, respectively. The second pull-up sub-circuit 121 is connected to the first power terminal V1 and the first node P1_1, respectively.

The second transmitter 121 circuit is configured to: if the level of the second node P1_2 is the first level, the level of the first node P1_1 is pulled down to the first level. The second pull-up sub-circuit 121 is configured to: if the level of the second node P1_2 is the third level, the level of the first node P1_1 is pulled up to the second level under the driving of the first power source terminal V1. The second path is a path between the second node P1_2 and the first node P1_1 through the second transmission sub-circuit 121.

For example, the second transmission subcircuit 121 may be configured to: if the level of the second node P1_2 is the first level, turning on a second path between the second node P1_2 and the first node P1_1, thereby pulling down the level of the first node P1_1 to the first level; and if the level of the second node P1_2 is the third level, the second path between the second node P1_2 and the first node P1_1 is closed. Accordingly, the second pull-up sub-circuit 122 may pull up the level of the first node P1_1 to the second level when the second path is turned off.

With continued reference to fig. 3, the second transmit subcircuit 121 may include: a second diode D2 and a second switching transistor Q2. The anode of the second diode D2 is connected to the first node P1_1, the cathode of the second diode D2 is connected to the first electrode of the second switching transistor Q2, the gate G of the second switching transistor Q2 is connected to the second power source terminal V2, and the second electrode of the second switching transistor Q2 is connected to the second node P1_ 2.

The second switching transistor Q2 may be an N-type MOS transistor, the first pole of the second switching transistor Q2 may be the drain D, and the second pole of the second switching transistor Q2 may be the source S.

The second pull-up sub-circuit 122 may include: and a second resistor R2, one end of the second resistor R2 being connected to the first node P1_1, and the other end of the second resistor R2 being connected to the first power terminal V1.

It can be understood that when the clock signal transmitted to the second node P1_2 is a low level signal (i.e., the level of the second node P1_2 is a first level), the source S voltage of the second switching transistor Q2 is less than the voltage of the gate G. Accordingly, a voltage between the gate G and the source S of the second switching transistor Q2 is greater than a threshold voltage of the second switching transistor Q2, and the drain D and the source S of the second switching transistor Q2 are turned on, so that the cathode of the second diode D2 is at the first level. At this time, the level of the first node P1_1 connected to the anode of the second diode D2 is also pulled down to the same first level as the second node P1_ 2. Thereby, level conversion and transmission of the clock signal of a low level between the second node P1_2 and the first node P1_1 can be achieved.

When the clock signal transmitted to the second node P1_2 is a high level signal (i.e., the level of the second node P1_2 is a third level), the voltage between the gate G and the source S of the second switching transistor Q2 is less than the threshold voltage of the second switching transistor Q2, and the second switching transistor Q2 is in an off state. At this time, the second resistor R2 can pull up the level of the first node P1_1 to the second level corresponding to the first power source terminal V1 under the driving of the first power source terminal V1. Wherein the second level is adapted to the operating level of the first device 20. Thereby, level conversion and transmission of the clock signal of a high level between the second node P1_2 and the first node P1_1 can be achieved.

It can be understood that, in the first conversion circuit 11 connected to the serial clock line SCL, when the first node P1_1 transmits a clock signal to the second node P1_2, the first conversion sub-circuit 110 in the first conversion circuit 11 can perform corresponding conversion on the level at the second node P1_2 based on the level of the first node P1_ 1. When the second node P1_2 transmits the clock signal to the first node P1_1, the second conversion sub-circuit 120 in the first conversion circuit 11 can perform corresponding conversion on the level at the first node P1_1 based on the level at the second node P1_ 2. Therefore, through the two level conversion circuits, bidirectional level conversion between the first node P1_1 and the second node P1_2 on the serial clock line SCL can be realized, and the accuracy of clock signal transmission between the two nodes on the IIC bus is effectively ensured.

Optionally, in this embodiment of the application, the resistance value of the second resistor R2 in the second pull-up sub-circuit 121 may be equal to the resistance value of the first resistor R1 in the first pull-up sub-circuit 111. For example, the resistance value of the first resistor R1 and the resistance value of the second resistor R2 may be 1.5 kilo-ohms (k Ω), respectively. Alternatively, the resistance value of the first resistor R1 and the resistance value of the second resistor R2 may be both 4.7k Ω.

Referring to fig. 4, the second conversion sub-circuit 120 in the second conversion circuit 12 connected to the serial data line SDA is used to convert the level of the data signal transmitted from the second node P2_2 to the first node P2_ 1. The structure and operation principle of the second converting sub-circuit 120 in the second converting circuit 12 are the same as those of the second converting sub-circuit 120 in the first converting circuit 11, and are not repeated herein. By providing the first conversion sub-circuit 110 and the second conversion sub-circuit 120 in the second conversion circuit 12, bidirectional level conversion of the data signal line SDA in the IIC bus can be realized.

In summary, the present application provides a level shifter circuit for an IIC bus. The level conversion circuit includes two conversion circuits connected to a serial clock line and a serial data line in the IIC bus, respectively. Because the two conversion circuits can convert the levels of different nodes on the IIC bus, normal communication of clock signals and data signals between devices connected with the IIC bus and having different working levels can be ensured.

The terms "first," "second," and the like in this application are used for distinguishing between similar items and items that have substantially the same function or similar functionality, and it should be understood that "first," "second," and "nth" do not have any logical or temporal dependency or limitation on the number or order of execution.

The above description is only exemplary of the present application and should not be taken as limiting the present application, and any modifications, equivalents, improvements and the like that are made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (10)

1. A level shift circuit (10) for an inter integrated circuit, IIC, bus, the IIC bus comprising a Serial Clock Line (SCL) and a serial data line (SDA), the level shift circuit (10) comprising: a first conversion circuit (11) connected to the Serial Clock Line (SCL), and a second conversion circuit (12) connected to the serial data line (SDA);

each of the first conversion circuit (11) and the second conversion circuit (12) comprises: a first conversion sub-circuit (110) and a second conversion sub-circuit (120);

the first converting sub-circuit (110) is respectively connected to a first power supply terminal (V1), a second power supply terminal (V2), a first node and a second node, and the first converting sub-circuit (110) is configured to pull down a level of the second node to the first level if the level of the first node is the first level, and pull up the level of the second node to a third level under the driving of the second power supply terminal (V2) if the level of the first node is the second level;

the second converting sub-circuit (120) is respectively connected to the first power source terminal (V1), the second power source terminal (V2), the first node and the second node, and the second converting sub-circuit (120) is configured to pull down the level of the first node to the first level if the level of the second node is the first level, and pull up the level of the first node to the second level under the driving of the first power source terminal (V1) if the level of the second node is the third level;

wherein the second level and the third level are both high levels relative to the first level, a first node and a second node in the first conversion circuit (11) are both connected with the Serial Clock Line (SCL), and a first node and a second node in the second conversion circuit (12) are both connected with the serial data line (SDA).

2. The level shift circuit (10) of claim 1, wherein the first shift sub-circuit (110) comprises: a first transmission sub-circuit (111) and a first pull-up sub-circuit (112);

the first transmission sub-circuit (111) is respectively connected to the first power source terminal (V1), the first node, and the second node, and the first transmission sub-circuit (111) is configured to pull down a level of the second node to the first level if the level of the first node is the first level;

the first pull-up sub-circuit (112) is respectively connected to the second power supply terminal (V2) and the second node, and the first pull-up sub-circuit (112) is configured to pull up the level of the second node to the third level under the driving of the second power supply terminal (V2).

3. The level shift circuit (10) of claim 2, wherein the first transmission subcircuit (111) comprises: a first switching transistor (Q1) and a first diode (D1);

the gate of the first switching transistor (Q1) is connected to the first supply terminal (V1), the first pole of the first switching transistor (Q1) is connected to the first node, the second pole of the first switching transistor (Q1) is connected to the cathode of the first diode (D1), and the anode of the first diode (D1) is connected to the second node.

4. The level shift circuit (10) of claim 2, wherein the first pull-up sub-circuit (112) comprises: a first resistor (R1);

one end of the first resistor (R1) is connected to the second node, and the other end of the first resistor (R1) is connected to the second power supply terminal (V2).

5. The level shift circuit (10) of any of claims 1 to 4, wherein the second shift sub-circuit (120) comprises: a second transmission sub-circuit (121) and a second pull-up sub-circuit (122);

the second transmission sub-circuit (121) is respectively connected to the second power source terminal (V2), the first node, and the second transmission sub-circuit (121) is configured to pull down a level of the first node to the first level if the level of the second node is the first level;

the second pull-up sub-circuit (122) is respectively connected to the first power supply terminal (V1) and the first node, and the second pull-up sub-circuit (122) is configured to pull up a level of the first node to the second level under the driving of the first power supply terminal (V1).

6. The level shift circuit (10) of claim 5, wherein the second transmission subcircuit (121) comprises: a second diode (D2) and a second switching transistor (Q2);

an anode of the second diode (D2) is connected to the first node, a cathode of the second diode (D2) is connected to a first pole of the second switching transistor (Q2), a gate of the second switching transistor (Q2) is connected to the second power supply terminal (V2), and a second pole of the second switching transistor (Q2) is connected to the second node.

7. The level shift circuit (10) of claim 6, wherein the second switch transistor (Q2) and the first switch transistor (Q1) in the first transmission sub-circuit (111) are both NMOS transistors.

8. The level shift circuit (10) of claim 5, wherein the second pull-up sub-circuit (122) comprises: a second resistor (R2); one end of the second resistor (R2) is connected to the first node, and the other end of the second resistor (R2) is connected to the first power supply terminal (V1).

9. The level shifting circuit (10) of claim 5, wherein the resistance of the second pull-up sub-circuit (122) is equal to the resistance of the first pull-up sub-circuit (112) in the first switching sub-circuit (110).

10. An electronic device, characterized in that the electronic device comprises: an IIC bus, a level shifter circuit (10) as claimed in any one of claims 1 to 9, a first device (20) and a second device (30);

wherein the IIC bus comprises a Serial Clock Line (SCL) and a serial data line (SDA);

a first node (P1 _ 1) and a second node (P1 _ 2) in a first conversion circuit (11) in the level conversion circuit (10) are both connected with the Serial Clock Line (SCL), and a first node (P2 _ 1) and a second node (P2 _ 2) in a second conversion circuit (12) in the level conversion circuit (10) are both connected with the serial data line (SDA);

the first device (20) is connected to a first node (P1 _ 2) in the first switching circuit (11) and a first node (P2 _ 1) in the second switching circuit (12), respectively;

the second device (30) is connected to a second node (P1 _ 2) in the first switching circuit (11) and a second node (P2 _ 2) in the second switching circuit (12), respectively.

Images