CN212033770U - Peak voltage suppression circuit - Google Patents
Peak voltage suppression circuit Download PDFInfo
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- CN212033770U CN212033770U CN202020759739.1U CN202020759739U CN212033770U CN 212033770 U CN212033770 U CN 212033770U CN 202020759739 U CN202020759739 U CN 202020759739U CN 212033770 U CN212033770 U CN 212033770U
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Abstract
The utility model discloses a peak voltage suppression circuit, which comprises an input voltage detection circuit, a field effect transistor on-off control circuit and a peak voltage absorption circuit; the input voltage detection circuit comprises a voltage division circuit and a reference voltage regulator U1, and the field effect tube on-off control circuit comprises a voltage regulator tube D1, a triode Q1, a voltage regulator tube D2, a triode Q2, a voltage regulator tube D3 and a field effect tube Q3; the utility model discloses a to input voltage's detection and to the control of switch tube, restrain the input overvoltage, guarantee that the back level equipment normally works safely.
Description
Technical Field
The utility model relates to a circuit design technical field, especially a peak voltage suppression circuit.
Background
In application, the input voltage of the electronic device cannot exceed the maximum allowable input voltage, but the input voltage of the electronic device often causes a large voltage spike due to some reasons, such as untimely response of an input source loop, poor instantaneous contact of a switch during closing and the like, and the voltage spike is likely to cause the rear-stage electronic device to trigger input overvoltage protection, restart or stop working, and further cause the rear-stage electric device to fail to work normally.
SUMMERY OF THE UTILITY MODEL
For solving the problem that exists among the prior art, the utility model aims at providing a peak voltage suppression circuit, the utility model discloses can restrain the input overvoltage, guarantee that the back level equipment normally works safely.
In order to achieve the above object, the utility model adopts the following technical scheme: a peak voltage suppression circuit comprises an input voltage detection circuit, a field effect transistor on-off control circuit and a peak voltage absorption circuit; the input voltage detection circuit comprises a voltage dividing circuit and a reference voltage-stabilizing source U1, the field effect tube on-off control circuit comprises a voltage-stabilizing tube D1, a triode Q1, a voltage-stabilizing tube D2, a triode Q2, a voltage-stabilizing tube D3 and a field effect tube Q3, a reference pole of the reference voltage-stabilizing source U1 is connected with the voltage dividing circuit, a cathode of a reference voltage-stabilizing source U1 is connected with a positive pole of an input power supply through a resistor R3, an anode of the reference voltage-stabilizing source U1 is connected with a negative pole of the input power supply, a base of the triode Q1 is connected with a cathode of the reference voltage-stabilizing source U1 and a cathode of a voltage-stabilizing tube D1 through a resistor R4, a collector of the triode Q1 is connected with a positive pole of the input power supply through a resistor R5, an emitter of the triode Q1 and an anode of a voltage-stabilizing tube D1 are both connected with a negative pole of the input power supply, a base of the triode Q59, the collector of the triode Q2 is connected with the positive electrode of an input power supply through a resistor R7, the emitter of the triode Q2 and the anode of a voltage regulator tube D2 are both connected with the negative electrode of the input power supply, the grid of the field effect tube Q3 is connected with the collector of the triode Q2 and the cathode of the voltage regulator tube D3 through a resistor R9, the source and the drain of the field effect tube Q3 are connected in series with the negative electrode of the input power supply, the anode of the voltage regulator tube D3 is connected with the source of the field effect tube Q3, and the spike voltage absorption circuit is connected between the source and the drain of the field effect tube Q3 in parallel.
In a preferred embodiment, the voltage dividing circuit comprises a resistor R1 and a resistor R2 which are serially connected between the positive pole and the negative pole of the input power supply, and the connection end of the resistor R1 and the resistor R2 is connected with the reference pole of the reference voltage regulator U1.
In another preferred embodiment, the spike voltage absorbing circuit is a resistor R8.
In another preferred embodiment, the reference voltage regulator U1 is TL 431.
The utility model has the advantages that:
the utility model discloses can effectively restrain because of the voltage peak that input power caused, back level power supply unit overvoltage protection when avoiding the voltage peak guarantees back level electronic equipment's normal work.
Drawings
Fig. 1 is a schematic diagram of a circuit structure according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
Example (b):
as shown in fig. 1, a peak voltage suppression circuit includes an input voltage detection circuit, a field effect transistor on-off control circuit, and a peak voltage absorption circuit; the input voltage detection circuit comprises a voltage dividing circuit and a reference voltage-stabilizing source U1, the field effect tube on-off control circuit comprises a voltage-stabilizing tube D1, a triode Q1, a voltage-stabilizing tube D2, a triode Q2, a voltage-stabilizing tube D3 and a field effect tube Q3, a reference pole of the reference voltage-stabilizing source U1 is connected with the voltage dividing circuit, a cathode of a reference voltage-stabilizing source U1 is connected with a positive pole of an input power supply through a resistor R3, an anode of the reference voltage-stabilizing source U1 is connected with a negative pole of the input power supply, a base of the triode Q1 is connected with a cathode of the reference voltage-stabilizing source U1 and a cathode of a voltage-stabilizing tube D1 through a resistor R4, a collector of the triode Q1 is connected with a positive pole of the input power supply through a resistor R5, an emitter of the triode Q1 and an anode of a voltage-stabilizing tube D1 are both connected with a negative pole of the input power supply, a base of the triode Q59, the collector of the triode Q2 is connected with the positive electrode of an input power supply through a resistor R7, the emitter of the triode Q2 and the anode of a voltage regulator tube D2 are both connected with the negative electrode of the input power supply, the grid of the field effect tube Q3 is connected with the collector of the triode Q2 and the cathode of the voltage regulator tube D3 through a resistor R9, the source and the drain of the field effect tube Q3 are connected in series with the negative electrode of the input power supply, the anode of the voltage regulator tube D3 is connected with the source of the field effect tube Q3, and the spike voltage absorption circuit is connected between the source and the drain of the field effect tube Q3 in parallel.
In this embodiment, the voltage dividing circuit includes a resistor R1 and a resistor R2 connected in series between the positive electrode and the negative electrode of the input power supply, and the connection end of the resistor R1 and the resistor R2 is connected to the reference electrode of the reference regulator U1.
In this embodiment, the spike voltage absorbing circuit is a resistor R8.
In this embodiment, the reference voltage source U1 is TL 431.
The present embodiment is further illustrated below:
the peak voltage suppression circuit of the embodiment uses common components such as a resistor, a reference voltage regulator TL431, a triode, a field effect transistor and the like, suppresses input overvoltage through detection of input voltage and control of a switching tube, ensures that a subsequent device works safely and normally, and mainly comprises an input voltage detection circuit, a field effect transistor on-off control circuit and a peak voltage absorption resistor.
In normal operation, the fet Q3 is turned on, and the circuit supplies power to the subsequent stage device through the fet Q3, where Vout is approximately equal to Vin. When the peak voltage appears, the field effect transistor Q3 is turned off, the circuit supplies power to the rear-stage equipment through the resistor R8, and the resistor R8 absorbs the peak voltage.
The reference voltage regulator U1 is provided by dividing the voltage at the reference input terminal by a resistor R1 and a resistor R2:
Vref＝Vin×R2/(R2+R1)
the reference input of the reference regulator U1 sets the voltage value to Vref-set. When the input voltage is in a normal range, Vref is less than Vref-set, a reference voltage regulator U1 is in a turn-off state, at this time, a resistor R3 and a voltage regulator tube D1 form a passage, the base voltage of a triode Q1 is the clamping voltage of a voltage regulator tube D1, so that a triode Q1 is turned on, a resistor R5 and a triode Q1 form a passage, the base voltage of a triode Q2 is pulled down, the triode Q2 is turned off, a resistor R7 and the voltage regulator tube D3 form a passage, the grid-source voltage Vgs of a field effect tube Q3 is the clamping voltage of a voltage regulator tube D3, the clamping voltage Vgs (th) is larger than the turn-on voltage Vgs of a.
When the input voltage rises, the reference voltage regulator U1 simultaneously rises with reference to the input end voltage Vref, when Vref rises to Vref-set, the reference voltage regulator U1 is turned on, the cathode voltage is pulled down, namely the base voltage of a triode Q1 is pulled down, the triode Q1 is turned off, a resistor R5 and a voltage regulator D2 form a passage, the base voltage of a triode Q2 is the clamping voltage of the voltage regulator D2, the triode Q2 is turned on, a resistor R7 and the triode Q2 form a passage, the grid voltage of a field effect tube Q3 is pulled down, Vgs is smaller than the turn-on voltage, the field effect tube Q3 is turned off, current passes through the resistor R8, the resistor R8 absorbs overvoltage, the output current is Iout, the output voltage is Vout-Iout multiplied by R8, the value of the resistor R8 is set to ensure that the output voltage is within the normal working input voltage range of the post-stage equipment, so that when overvoltage occurs to the power supply, the input voltage of the post-stage equipment can, the equipment can work normally.
The above-mentioned embodiments only express the specific embodiments of the present invention, and the description thereof is specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention.
Claims (4)
1. A peak voltage suppression circuit is characterized by comprising an input voltage detection circuit, a field effect transistor on-off control circuit and a peak voltage absorption circuit; the input voltage detection circuit comprises a voltage dividing circuit and a reference voltage-stabilizing source U1, the field effect tube on-off control circuit comprises a voltage-stabilizing tube D1, a triode Q1, a voltage-stabilizing tube D2, a triode Q2, a voltage-stabilizing tube D3 and a field effect tube Q3, a reference pole of the reference voltage-stabilizing source U1 is connected with the voltage dividing circuit, a cathode of a reference voltage-stabilizing source U1 is connected with a positive pole of an input power supply through a resistor R3, an anode of the reference voltage-stabilizing source U1 is connected with a negative pole of the input power supply, a base of the triode Q1 is connected with a cathode of the reference voltage-stabilizing source U1 and a cathode of a voltage-stabilizing tube D1 through a resistor R4, a collector of the triode Q1 is connected with a positive pole of the input power supply through a resistor R5, an emitter of the triode Q1 and an anode of a voltage-stabilizing tube D1 are both connected with a negative pole of the input power supply, a base of the triode Q59, the collector of the triode Q2 is connected with the positive electrode of an input power supply through a resistor R7, the emitter of the triode Q2 and the anode of a voltage regulator tube D2 are both connected with the negative electrode of the input power supply, the grid of the field effect tube Q3 is connected with the collector of the triode Q2 and the cathode of the voltage regulator tube D3 through a resistor R9, the source and the drain of the field effect tube Q3 are connected in series with the negative electrode of the input power supply, the anode of the voltage regulator tube D3 is connected with the source of the field effect tube Q3, and the spike voltage absorption circuit is connected between the source and the drain of the field effect tube Q3 in parallel.
2. The spike voltage suppression circuit according to claim 1, wherein the voltage divider circuit comprises a resistor R1 and a resistor R2 connected in series between the positive and negative poles of the input power source, and the connection end of the resistor R1 and the resistor R2 is connected to the reference pole of the reference regulator U1.
3. The spike voltage suppression circuit of claim 1, wherein the spike voltage absorption circuit is a resistor R8.
4. The spike voltage suppression circuit of claim 1 wherein the reference regulator U1 is TL 431.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020759739.1U CN212033770U (en) | 2020-05-09 | 2020-05-09 | Peak voltage suppression circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020759739.1U CN212033770U (en) | 2020-05-09 | 2020-05-09 | Peak voltage suppression circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212033770U true CN212033770U (en) | 2020-11-27 |
Family
ID=73480638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020759739.1U Active CN212033770U (en) | 2020-05-09 | 2020-05-09 | Peak voltage suppression circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212033770U (en) |
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2020
- 2020-05-09 CN CN202020759739.1U patent/CN212033770U/en active Active
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