CN212032656U - Reliability testing device for non-volatile memory chip - Google Patents
Reliability testing device for non-volatile memory chip Download PDFInfo
- Publication number
- CN212032656U CN212032656U CN202020884584.4U CN202020884584U CN212032656U CN 212032656 U CN212032656 U CN 212032656U CN 202020884584 U CN202020884584 U CN 202020884584U CN 212032656 U CN212032656 U CN 212032656U
- Authority
- CN
- China
- Prior art keywords
- computer software
- upper computer
- module
- central control
- software system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The utility model relates to a reliability testing device of non-volatile memory chip, the device it includes: the system comprises a central control board system, a controllable power supply system, an upper computer software system, a display system and a temperature control system; wherein: the central control board system is respectively connected with the upper computer software system, the display system and the controllable power supply system; wherein: the temperature control system comprises a high-temperature box and a low-temperature box. The utility model discloses a design a well accuse board system, controllable electrical power generating system, host computer software system, display system and the mutual integrated device of temperature control system, the reliability test that reduces the NVM product need drop into a large amount of hardware costs and time cost.
Description
Technical Field
The utility model relates to a reliability testing arrangement of non-volatile memory chip.
Background
In recent years, embedded non-volatile memories (NVM) have gone beyond the range of embedded applications and microcontroller code storage into data applications ranging from high-capacity consumer electronics to high-reliability automotive and industrial products. As the range of embedded NVM applications expands, these new applications and requirements have driven the generation of new technologies and spawned new users in the embedded NVM market.
No matter the terminal application is a high-capacity consumer electronic product or a high-reliability automobile part, the embedded NVM must have high quality, high stability and high reliability, and not only needs to ensure high yield in production, but also needs to ensure reliable field performance in the whole product life cycle. Therefore, compared with a general integrated circuit chip, the reliability test items of the NVM products are more involved, and the reliability of the products in severe use environments such as high/low temperature needs to be simulated, and the NVM products are generally required to be repeatedly read and written at low temperature (-40 ℃), room temperature (25 ℃) and high temperature (125 ℃) for as many as 100 million times.
Therefore, reliability testing of embedded non-volatile memory products requires a significant investment in hardware and time costs.
SUMMERY OF THE UTILITY MODEL
To overcome the above-mentioned drawbacks and deficiencies of the prior art, the present invention provides a low-cost reliability testing device for non-volatile memory chips.
In order to solve the above technical problem, the utility model discloses have following constitution: a reliability testing device of a nonvolatile memory chip comprises: the system comprises a central control board system, a controllable power supply system, an upper computer software system, a display system and a temperature control system; wherein: the central control board system is respectively connected with the upper computer software system, the display system and the controllable power supply system; wherein: the temperature control system comprises a high-temperature box and a low-temperature box.
The technical effects of the embodiment are as follows: by designing a device in which a central control board system, a controllable power supply system, an upper computer software system, a display system and a temperature control system are integrated with each other, the reliability test of an NVM product can be reduced by investing a large amount of hardware cost and time cost.
Furthermore, the central control board system comprises a power supply module and a data reading, writing and erasing module.
The technical effects of the embodiment are as follows: the power supply module and the read-write data erasing module are arranged in the central control panel, so that the power supply function and the read-write data erasing function can be realized.
Furthermore, the upper computer software system comprises an NVM reading and writing module and a real-time Pass/Fail judging module.
The technical effects of the embodiment are as follows: the NVM reading and writing functions and the real-time Pass/Fail judging function of different specifications can be realized by arranging the NVM reading and writing module and the real-time Pass/Fail judging module in the upper computer software system.
Furthermore, the upper computer software system further comprises a chip data transmission module for transmitting and storing chip data.
The technical effects of the embodiment are as follows: the chip data transmission function can be realized by arranging the chip data transmission module in the upper computer software system.
Furthermore, the upper computer software system further comprises a central control board control module for controlling the central control board.
The technical effects of the embodiment are as follows: the function of controlling the central control board can be realized by arranging the central control board control module in the upper computer software system.
Furthermore, the upper computer software system further comprises a test data feedback module for feeding back the test data.
The technical effects of the embodiment are as follows: the function of feeding back the test data can be realized by arranging a test data feedback module in the upper computer software system.
Furthermore, the upper computer software system further comprises a data calculation module for judging whether the central control panel is in an abnormal state.
The technical effects of the embodiment are as follows: the function of judging whether the central control board is abnormal or not can be realized by arranging the data calculation module in the upper computer software system.
Furthermore, the upper computer software system further comprises a fault self-checking and repairing module, which is used for performing fault self-checking and repairing on the central control panel.
The technical effects of the embodiment are as follows: the function of self-checking and repairing the faults of the central control panel can be realized by arranging the fault self-checking and repairing module in the upper computer software system.
Furthermore, the reliability testing device of the non-volatile memory chip also comprises an embedded single chip microcomputer system, and the embedded single chip microcomputer system is connected with the upper computer software system.
The technical effects of the embodiment are as follows: the connection between the embedded single chip microcomputer system and the upper computer software system can be realized by arranging the embedded single chip microcomputer system in the reliability testing device of the non-volatile memory chip.
Compared with the prior art, the utility model has the advantages of: by designing a device in which a central control board system, a controllable power supply system, an upper computer software system, a display system and a temperature control system are integrated with each other, the reliability test of an NVM product can be reduced by investing a large amount of hardware cost and time cost.
Drawings
Fig. 1 is a schematic view of the overall structure of the present invention in one embodiment.
Detailed Description
The conception, the specific structure and the technical effects of the present invention will be further described with reference to the accompanying drawings, so as to fully understand the objects, the features and the effects of the present invention.
As shown in fig. 1, a reliability testing apparatus for a non-volatile memory chip includes: a central control board system 11, a controllable power supply system 12, an upper computer software system 13, a display system 14 and a temperature control system 15; wherein: the central control board system 11 is respectively connected with the upper computer software system 13, the display system 14 and the controllable power supply system 12; wherein: the temperature control system 15 includes a high temperature chamber and a low temperature chamber. The technical effects of the embodiment are as follows: by designing a device in which a central control board system 11, a controllable power supply system 12, an upper computer software system 13, a display system 14 and a temperature control system 15 are integrated with each other, the reliability test of the NVM product needs to invest a large amount of hardware cost and time cost.
The central control board system 11 comprises a power supply module and a read-write erasing data module. The technical effects of the embodiment are as follows: the power supply module and the read-write data erasing module are arranged in the central control panel, so that the power supply function and the read-write data erasing function can be realized.
The upper computer software system 13 comprises an NVM reading and writing module and a real-time Pass/Fail judging module. The technical effects of the embodiment are as follows: by arranging the NVM read-write module and the real-time Pass/Fail judgment module in the upper computer software system 13, NVM read-write functions and real-time Pass/Fail judgment functions of different specifications can be realized.
The upper computer software system 13 further includes a chip data transmission module, which is used for transmitting and storing chip data. The technical effects of the embodiment are as follows: the chip data transmission module is arranged in the upper computer software system 13, so that the function of transmitting chip data can be realized.
The upper computer software system 13 further includes a central control board control module for controlling the central control board. The technical effects of the embodiment are as follows: the function of controlling the central control panel can be realized by arranging the central control panel control module in the upper computer software system 13.
The upper computer software system 13 further includes a test data feedback module, configured to feed back the test data. The technical effects of the embodiment are as follows: the function of feeding back the test data can be realized by arranging a test data feedback module in the upper computer software system 13.
The upper computer software system 13 further includes a data calculation module for determining whether the central control panel is in an abnormal state. The technical effects of the embodiment are as follows: by arranging a data calculation module in the upper computer software system 13, the function of judging whether the central control panel is abnormal or not can be realized.
The upper computer software system 13 further includes a fault self-checking and repairing module, which is used for performing fault self-checking and repairing on the central control panel. The technical effects of the embodiment are as follows: the function of self-checking and repairing the faults of the central control panel can be realized by arranging a fault self-checking and repairing module in the upper computer software system 13.
The reliability testing device of the non-volatile memory chip further comprises an embedded single chip microcomputer system, and the embedded single chip microcomputer system is connected with the upper computer software system 13. The technical effects of the embodiment are as follows: the connection between the embedded single chip microcomputer system and the upper computer software system 13 can be realized by arranging the embedded single chip microcomputer system in the reliability testing device of the non-volatile memory chip.
Compared with the prior art, the utility model has the advantages of: by designing a device in which a central control board system 11, a controllable power supply system 12, an upper computer software system 13, a display system 14 and a temperature control system 15 are integrated with each other, the reliability test of the NVM product needs to invest a large amount of hardware cost and time cost.
The foregoing is merely exemplary and various modifications may be made by those skilled in the art without departing from the scope and spirit of the embodiments. The above embodiments may be implemented individually or in any combination.
Claims (9)
1. A reliability testing device for a nonvolatile memory chip is characterized by comprising: the system comprises a central control board system, a controllable power supply system, an upper computer software system, a display system and a temperature control system; wherein:
the central control board system is respectively connected with the upper computer software system, the display system and the controllable power supply system; wherein:
the temperature control system comprises a high-temperature box and a low-temperature box.
2. The apparatus of claim 1, wherein the central control board system comprises a power supply module and a data read/write/erase module.
3. The apparatus of claim 1, wherein the upper computer software system comprises an NVM read/write module and a real-time Pass/Fail determination module.
4. The device of claim 1, wherein the host computer software system further comprises a chip data transmission module for transmitting chip data.
5. The device of claim 1, wherein the upper computer software system further comprises a central control board control module for controlling the central control board.
6. The device for testing the reliability of a nonvolatile memory chip as in claim 1, wherein the upper computer software system further comprises a test data feedback module for feeding back the test data.
7. The device for testing the reliability of a nonvolatile memory chip as claimed in claim 1, wherein the upper computer software system further comprises a data calculation module for determining whether the central control panel is in an abnormal state.
8. The device for testing the reliability of the nonvolatile memory chip as in claim 1, wherein the upper computer software system further comprises a fault self-checking and repairing module for performing fault self-checking and repairing on the central control board.
9. The device of claim 1, further comprising an embedded single-chip microcomputer system, wherein the embedded single-chip microcomputer system is connected to the upper computer software system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020884584.4U CN212032656U (en) | 2020-05-22 | 2020-05-22 | Reliability testing device for non-volatile memory chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020884584.4U CN212032656U (en) | 2020-05-22 | 2020-05-22 | Reliability testing device for non-volatile memory chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212032656U true CN212032656U (en) | 2020-11-27 |
Family
ID=73481006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020884584.4U Active CN212032656U (en) | 2020-05-22 | 2020-05-22 | Reliability testing device for non-volatile memory chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212032656U (en) |
-
2020
- 2020-05-22 CN CN202020884584.4U patent/CN212032656U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7762818B2 (en) | Multi-function module | |
| CN101366182B (en) | A nand flash memory controller exporting a nand interface | |
| US6684356B2 (en) | Self-test ram using external synchronous clock | |
| KR100703969B1 (en) | Apparatus for testing memory module | |
| US11719748B2 (en) | Method of testing memory device employing limited number of test pins and memory device utilizing same | |
| CN102915209B (en) | Storage control chip, storage equipment and system data writing method | |
| CN109992525A (en) | Flash memory control | |
| CN112542199A (en) | Method, circuit, storage medium and terminal for detecting flash storage error | |
| CN212032656U (en) | Reliability testing device for non-volatile memory chip | |
| CN101354673B (en) | SPD chip error information simulation apparatus of memory | |
| CN112099856B (en) | Embedded system and starting method thereof | |
| CN102255208A (en) | Riser card | |
| CN102339648A (en) | Error-detection/error-correction verification module detection method and device | |
| CN111489786A (en) | Reliability testing device and method for non-volatile memory chip | |
| CN115904415A (en) | Burning device and burning method | |
| KR20100041514A (en) | Solid state drive apparatus reducing a test time and method for testing the same | |
| CN106611608B (en) | Memorizer control circuit unit, memorizer memory devices and data transmission method | |
| CN110209433B (en) | Method for identifying concentrators of different models | |
| CN104134464A (en) | System and method for testing address line | |
| CN113918081A (en) | Computer readable storage medium, method and device for configuring reliable command | |
| CN205428496U (en) | A test box for testing data storage ability of memory chip under high temperature environment | |
| TWI748550B (en) | Method and apparatus and computer program product for configuring reliable command | |
| US20110258492A1 (en) | Device for testing serial interface | |
| CN108664399A (en) | Processor chips emulator and power down test method | |
| CN215006613U (en) | Burning component and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |