CN211890399U

CN211890399U - High-hardness semiconductor wafer grinding and polishing pad

Info

Publication number: CN211890399U
Application number: CN202020459499.3U
Authority: CN
Inventors: 何超; 魏汝省; 李鹏; 景旭斌; 徐伟; 候凯亮
Original assignee: Shanxi Scintillation Crystal Co ltd
Current assignee: Shanxi Scintillation Crystal Co ltd
Priority date: 2020-04-01
Filing date: 2020-04-01
Publication date: 2020-11-10
Anticipated expiration: 2030-04-01

Abstract

The utility model discloses a high-hardness semiconductor wafer polishing pad; belongs to the technical field of semiconductor materials; the problems of local accumulation or local liquid shortage and uneven flow of the abrasive on a grinding and polishing pad are solved, and the method is used for grinding and polishing the high-hardness semiconductor wafer; the waterproof coating comprises a substrate, wherein the bottom of the substrate is provided with a back adhesive, and the bottom of the back adhesive is provided with a waterproof layer; the upper surface of the substrate is provided with a reticular grinding and polishing layer which protrudes out of the substrate, and the depth of the reticular grinding and polishing layer is 1-3 times of the width of the reticular edge; the utility model discloses the grinding is thrown and is filled up through the range and the injecing of physical space structure, has improved the concentration stability and the flow uniformity of abrasive material, and its clearance reaches more than 1 mu m/minute, shortens process time, obtains the wafer that the damage layer is stable, roughness TTV is less than 1 mu m.

Description

High-hardness semiconductor wafer grinding and polishing pad

Technical Field

The utility model belongs to power electronics industry, semiconductor material field relate to a high rigidity semiconductor wafer grinds throws and fills up.

Background

Semiconductor wafers can be classified into soft materials, hard and brittle materials, and the like according to their hardness, and there are various polishing processes for semiconductor wafers.

A grinding and polishing process for metal disk and free abrasive features that the free abrasive with different sizes and hardness is added to the grooved metal disks such as cast iron disk, copper disk and tin disk to grind and polish the wafer, resulting in low removal rate of wafer, deep damaged layer, poor flatness and high risk of edge cracking and splintering. Meanwhile, the surface of the grinding and polishing disc is single in grooving structure, the disc needs to be repaired and cleaned in time due to the influence of yield, the consumption time is long, the production efficiency is low, and the method is not suitable for large-batch continuous production.

The other is a grinding and polishing process of soft polishing cloth and free abrasive, the traditional soft polishing cloth is adopted, the free abrasive with different grain diameters and hardness is added to grind and polish the wafer, and the polishing cloth has low hardness and low removal rate, is only suitable for the polishing process with small removal amount and is not suitable for the grinding and polishing process with large removal amount.

The other method is a grinding and polishing process of fixed abrasive, which is to adhere abrasives with different grain diameters and hardness on the surface of a metal disc or polishing cloth and grind and polish a wafer by matching water or free abrasive.

The metal disc, the polishing cloth and the fixed abrasive disc basically adopt single grooving shapes and structures such as square grooves, spiral grooves and the like, and abrasive flows out through grooves in the side faces of the disc, so that the disc surface is uneven in abrasive distribution, poor in flowability and large in loss. The high requirements of high removal rate, stable damage layer and good flatness are difficult to achieve, and the high-hardness semiconductor wafer needs the uniform distribution of the grinding materials without local accumulation or local liquid shortage in the grinding and polishing process, so that the good fluidity is ensured.

SUMMERY OF THE UTILITY MODEL

The utility model overcomes the defects of the prior art and provides a high-hardness polishing pad for semiconductor wafers. Aiming at the grinding and polishing characteristics of the high-hardness semiconductor wafer, the grinding and polishing pad with a unique shape structure is adopted, the problems of local accumulation or local liquid shortage and uneven flow of the grinding materials on the grinding and polishing pad are solved, and the grinding and polishing pad is used for grinding and polishing the high-hardness semiconductor wafer.

The utility model discloses a realize through following technical scheme.

A high-hardness semiconductor wafer grinding and polishing pad comprises a substrate, wherein the bottom of the substrate is provided with a back adhesive, and the bottom of the back adhesive is provided with a waterproof layer; the upper surface of the substrate is provided with a reticular grinding and polishing layer protruding out of the substrate, and the depth of the reticular grinding and polishing layer is 1-3 times of the width of the reticular edge.

Further, the depth of the net-shaped grinding and polishing layer is 2 times of the width of the net-shaped edge.

Furthermore, the meshes of the reticular grinding and polishing layer are either triangular, rhombic or circular.

Further, the triangle is an equilateral triangle.

Furthermore, regular hexagonal meshes are arranged in triangular meshes of the net-shaped grinding and polishing layer, and the diagonal length of each regular hexagonal mesh is 1/2 of the side length of each triangle.

Further, the waterproof layer is waterproof paper.

The utility model discloses produced beneficial effect does for prior art.

The utility model discloses the pad is thrown in the mill has unique shape structure, advances the verification that relapses, and the netted mill that has a take the altitude and lattice structure is thrown the layer and is passed through the range and the injecing of physical space structure, has improved the concentration stability and the homogeneity that flows of abrasive material for the process is thrown in the mill of high rigidity semiconductor wafer, and its clearance reaches more than 1 mu m/minute, shortens process time, obtains the wafer that the damage layer is stable, roughness TTV is less than 1 mu m.

Drawings

Figure 1 is a longitudinal cross-sectional view of the polishing pad of the present invention.

Figure 2 is a top view of the mesh polishing layer of example 1.

Figure 3 is a top view of the mesh polishing layer described in example 2.

Fig. 4 is a top view of a diamond mesh net polishing layer.

Figure 5 is a top view of the mesh polishing layer of example 3.

In the figure, 1 is a substrate, 2 is a reticular grinding and polishing layer, 3 is a back adhesive, and 4 is waterproof paper.

Detailed Description

In order to make the technical problem, technical scheme and beneficial effect that the utility model will solve more clearly understand, combine embodiment and attached drawing, it is right to go on further detailed description the utility model discloses. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. The technical solution of the present invention is described in detail below with reference to the embodiments and the drawings, but the scope of protection is not limited thereto.

Example 1

4000g of polyethylene powder, 300g of polyvinyl alcohol adhesive and 300g of mixed solvent (containing ethyl acetate, toluene and butanone) are sequentially added into a slurry barrel, high-speed stirring and dispersion are carried out for 10 minutes, then 300g of polyisocyanate curing agent is added, uniform stirring is carried out to obtain slurry, the slurry is coated on the surface of a triangular mold, hot pressing and curing are carried out for 30 hours at 130 ℃ to obtain a substrate 1, a mesh grinding and polishing layer 2 with triangular convex meshes is formed on the upper surface of the substrate 1, the edge width of the mesh grinding and polishing layer 2 is 1.5mm, the depth of the mesh grinding and polishing layer 2 is 2mm, and back glue 3 and waterproof paper 4 are bonded on the back surface of the substrate 1. The polishing pad is matched with the oil-based abrasive materials of diamond and boron carbide with the grain size of 28um to polish the silicon carbide wafer.

Example 2

Adding 3000g of epoxy resin powder, 250g of polyester resin adhesive and 250g of mixed solvent (containing diethyl ether and ethyl acetate) into a slurry barrel in sequence, stirring and dispersing for 10 minutes at a high speed, then adding 250g of polyisocyanate curing agent, stirring uniformly to obtain slurry, coating the slurry on the surface of a hexagonal mold sleeved inside a triangle, hot-pressing and curing for 15 hours at 230 ℃ to obtain a substrate 1, sleeving a hexagonal reticular grinding and polishing layer 2 on the upper surface of the substrate 1 in a triangular mode to form convex meshes, wherein the edge width and the depth of the reticular grinding and polishing layer 2 are 0.5mm and 0.5mm, and the back surface of the substrate 1 is bonded with a back adhesive 3 and waterproof paper 4. And (3) grinding and polishing the sapphire wafer by matching the grinding and polishing pad with oily abrasive materials of silicon carbide and boron carbide with the particle size of 3 mu m.

Example 3

4500g of polyvinyl chloride powder, 350g of polyvinyl alcohol adhesive and 350g of mixed solvent (containing methanol and toluene) are sequentially added into a slurry barrel, high-speed stirring and dispersion are carried out for 10 minutes, then 350g of polyisocyanate curing agent is added, uniform stirring is carried out to obtain slurry, the slurry is coated on the surface of a circular mold, hot pressing and curing are carried out for 20 hours at 200 ℃ to obtain a substrate 1, a mesh grinding and polishing layer 2 with circular convex meshes is formed on the upper surface of the substrate 1, the edge width of the mesh grinding and polishing layer 2 is 1mm, the depth of the mesh grinding and polishing layer 2 is 1.5mm, and back glue 2 and waterproof paper 3 are bonded on the back surface of the substrate 1. The grinding and polishing pad is matched with oily grinding materials of silicon carbide and boron carbide with the grain size of 15 mu m to grind and polish the sapphire wafer.

The following table shows the removal rates and TTV test data for the polishing pads described in examples 1-3 for different polished wafers.

The above description is for further details of the present invention with reference to specific preferred embodiments, and it should not be understood that the embodiments of the present invention are limited thereto, and it will be apparent to those skilled in the art that the present invention can be implemented in a plurality of simple deductions or substitutions without departing from the scope of the present invention, and all such alterations and substitutions should be considered as belonging to the present invention, which is defined by the appended claims.

Claims

1. A high-hardness semiconductor wafer grinding and polishing pad comprises a substrate and is characterized in that a back adhesive is arranged at the bottom of the substrate, and a waterproof layer is arranged at the bottom of the back adhesive; the upper surface of the substrate is provided with a reticular grinding and polishing layer protruding out of the substrate, and the depth of the reticular grinding and polishing layer is 1-3 times of the width of the reticular edge.

2. A high hardness semiconductor wafer polishing pad as claimed in claim 1, wherein said web-like polishing layer has a depth of 2 times the width of the web-like edge.

3. The high hardness semiconductor wafer polishing pad according to claim 1, wherein the mesh of said net-shaped polishing layer is either triangular, rhombic or circular.

4. A high hardness semiconductor wafer polishing pad according to claim 3, wherein said triangle is an equilateral triangle.

5. The high hardness semiconductor wafer polishing pad as claimed in claim 4, wherein regular hexagonal meshes are provided in triangular meshes of said net polishing layer, and the diagonal length of said regular hexagonal meshes is 1/2 of the side length of the triangle.

6. The high hardness semiconductor wafer polishing pad according to claim 1, wherein said water-proof layer is a water-proof paper.