CN211830748U - C-band high-performance frequency synthesis system - Google Patents
C-band high-performance frequency synthesis system Download PDFInfo
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- CN211830748U CN211830748U CN202020670430.5U CN202020670430U CN211830748U CN 211830748 U CN211830748 U CN 211830748U CN 202020670430 U CN202020670430 U CN 202020670430U CN 211830748 U CN211830748 U CN 211830748U
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Abstract
The utility model discloses a C-band high-performance frequency synthesis system, which comprises a main loop phase-locked circuit for processing a first reference signal, an auxiliary loop phase-locked circuit for processing a second reference signal and a mixing amplification circuit; the main loop phase-locked circuit comprises a first phase detector, a first loop filter, a first voltage-controlled oscillator and a first power divider which are sequentially connected; the auxiliary loop phase-locked circuit comprises a second phase discriminator, a second loop filter, a second voltage-controlled oscillator and a second power divider which are connected in sequence; the first power divider forms an output signal and a first feedback signal respectively, the second power divider forms a second feedback signal and a third feedback signal, the third feedback signal is fed back to the second phase discriminator, and the first feedback signal and the second feedback signal are fed back to the first phase discriminator through the mixing amplification circuit. The utility model discloses a C wave band high performance frequency synthesis system has the characteristics that the low power dissipation, phase place small in noise and spurious suppression are high.
Description
Technical Field
The utility model relates to a wireless communication technology field specifically indicates a C wave band high performance frequency synthesis system.
Background
With the development of wireless communication technology, in a wireless transceiving radio frequency system, higher and higher requirements are put forward on performance indexes of a local vibration source, and very low phase noise, small frequency switching time, extremely small frequency stepping and wide frequency band coverage are often required.
The implementation method of the C-band high-performance frequency synthesis system generally includes a phase-locked frequency synthesis mode and a direct frequency synthesis mode. Direct frequency synthesis is often suitable for electronic systems with larger size due to the need of a series of frequency mixing, frequency doubling and filtering amplification, and the direct frequency synthesis has the disadvantages of large size, complex circuit and high cost. The phase-locked frequency synthesis is widely applied because the circuit is simple to realize, small in size, low in power consumption, extremely low in stray and extremely high in cost performance. In the aspect of actual performance index realization, the phase noise, the frequency hopping time, the frequency stepping and the frequency broadband can not be considered at all sometimes, and must be chosen or rejected, so that the application range of the method is limited. The C-band high-performance frequency source system has obvious application short boards, and particularly has the requirements on very low phase noise, small frequency stepping, wide frequency band coverage, high frequency hopping speed and extremely small volume.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a C wave band high performance frequency synthesis system has characteristics that the low power dissipation, phase place small in noise and spurious suppression are high.
The utility model discloses can realize through following technical scheme:
the utility model discloses a C-band high-performance frequency synthesis system, which comprises a main loop phase-locked circuit for processing a first reference signal, an auxiliary loop phase-locked circuit for processing a second reference signal and a mixing amplification circuit; the main loop phase-locked circuit comprises a first phase detector, a first loop filter, a first voltage-controlled oscillator and a first power divider which are sequentially connected; the auxiliary loop phase-locked circuit comprises a second phase discriminator, a second loop filter, a second voltage-controlled oscillator and a second power divider which are connected in sequence; the first power divider forms an output signal and a first feedback signal respectively, the second power divider forms a second feedback signal and a third feedback signal, the third feedback signal is fed back to the second phase discriminator, and the first feedback signal and the second feedback signal are fed back to the first phase discriminator through the mixing amplification circuit.
Furthermore, the mixing amplifying circuit comprises a second amplifier, a mixer, a first amplifier and a band-pass filter which are connected in sequence, wherein the first power divider is connected with the input end of the second amplifier, and the second power divider is connected with the input end of the mixer.
Further, the frequency of the first reference signal is 50-56.25MHz, and the frequency of the second reference signal is 100 MHz.
Further, the signal frequency of the first power divider is 7.8-8.2GHz, and the signal frequency of the second power divider is 6.9-7.4 GHz.
Furthermore, the first phase discriminator and the second phase discriminator are in the HMC704LP4E type, the frequency dividing ratio N value of the first phase discriminator is 16, and the frequency dividing ratio N value of the second phase discriminator is 69-74.
Furthermore, the models of the first power divider and the second power divider are EP2C +.
Further, the first voltage controlled oscillator is of the model HMC506LP4E, and the second voltage controlled oscillator is of the model HMC505LP 4E.
Further, the mixer model is HMC558LC 3B.
Further, the first loop filter and the second loop filter are active loop filters.
Further, the second amplifier is a high isolation amplifier HMC564LC4 and the first amplifier is NBB-400.
The utility model relates to a C wave band high performance frequency synthesis system has following beneficial effect:
the power consumption is low, the system adopts the intra-loop double-loop mixing phase-locking synthesis, and the system has the excellent characteristics of a phase-locking circuit, small volume, light weight, low power consumption and high cost performance.
And secondly, the phase noise is low, and the system adopts intra-loop double-loop mixing phase-locked synthesis and comprises two phase-locked loops, a main loop and an auxiliary loop. The two phase-locked loops coordinate to work to complete frequency synthesis, and the large frequency division ratio of the single phase-locked loop is uniformly shared by the two phase-locked loops, so that the purpose of reducing phase noise is achieved, and the phase noise is excellent; moreover, the auxiliary loop works by adopting high phase discrimination frequency, and the C-band high-performance frequency synthesis system can realize higher frequency output and larger frequency bandwidth coverage and has extremely low phase noise.
And thirdly, stray suppression is high, after double-loop mixing, the radio frequency working frequency of the main loop phase discriminator is lower, the value of the frequency dividing ratio N is reduced, and stray deterioration is small. By utilizing the excellent characteristic, the DDS output of large stray can be adopted as the reference signal of a C-band high-performance frequency synthesis system, the minimum stepping output is realized, high stray inhibition is obtained, and the contradiction that the small stepping and low stray index can not be simultaneously realized is solved.
Fourth, the isolation is high, and the internal circuit has adopted the metal shielding case to keep apart, has prevented that the signal from crossing each other, prevents simultaneously that the signal from revealing to the outside, has improved the isolation greatly.
And fifthly, the device has the advantages of wide application range, simplicity, independence, convenience in use, small size, low power consumption and low cost, and can be used as a basic component of a complex frequency synthesis system.
Drawings
Fig. 1 is a schematic block diagram of a C-band high-performance frequency synthesis system according to the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the following provides a detailed description of the product of the present invention with reference to the embodiments and the accompanying drawings.
As shown in fig. 1, the utility model discloses a C-band high-performance frequency synthesis system, which comprises a main loop phase-locked circuit for processing a first reference signal, an auxiliary loop phase-locked circuit for processing a second reference signal and a mixing amplifier circuit; the main loop phase-locked circuit comprises a first phase detector, a first loop filter, a first voltage-controlled oscillator and a first power divider which are sequentially connected; the auxiliary loop phase-locked circuit comprises a second phase discriminator, a second loop filter, a second voltage-controlled oscillator and a second power divider which are connected in sequence; the first power divider forms an output signal and a first feedback signal respectively, the second power divider forms a second feedback signal and a third feedback signal, the third feedback signal is fed back to the second phase discriminator, and the first feedback signal and the second feedback signal are fed back to the first phase discriminator through the mixing amplification circuit.
In this embodiment, the mixing amplifying circuit includes a second amplifier, a mixer, a first amplifier, and a band-pass filter, which are connected in sequence, where the first power divider is connected to an input end of the second amplifier, and the second power divider is connected to an input end of the mixer.
In this embodiment, the frequency of the first reference signal is 50-56.25MHz and the frequency of the second reference signal is 100 MHz.
In this embodiment, the signal frequency of the first power divider is 7.8-8.2GHz, and the signal frequency of the second power divider is 6.9-7.4 GHz.
In this embodiment, the first phase detector and the second phase detector are of the HMC704LP4E type, the frequency division ratio N of the first phase detector is 16, and the frequency division ratio N of the second phase detector is 69-74.
In this embodiment, the models of the first power divider and the second power divider are EP2C +, and the specific parameters are as follows: 1.8-12.5 GHZ, ISO:16 dB.
In the embodiment, the first voltage-controlled oscillator is of a model HMC506LP4E, the output power of the first voltage-controlled oscillator is 14dBm, and the frequency range is 7.8-8.7 GHz; the second voltage-controlled oscillator is HMC505LP4E, the output power of the second voltage-controlled oscillator is 11dBm, and the frequency range is 6.8-7.4 GHz.
In this embodiment, the model of the mixer is HMC558LC3B, and the specific parameters are: IF is DC-6 GHz, RF is 5.5-14 GHz, insertion loss: 7 dB.
In this embodiment, the first loop filter and the second loop filter are active loop filters.
In this embodiment, the second amplifier is a high isolation amplifier HMC564LC4, and the specific parameters are: gain of 17dB, isolation of 40dB and 7-14 GHZ; the first amplifier is NBB-400, and the specific parameters are as follows: gain 15dB, DC-8 GHZ.
In the C-band high-performance frequency synthesis system, an intra-loop double-loop mixing phase-locking synthesis method is adopted, the frequency is synthesized through the coordination work of two phase-locked loops, the large frequency division ratio generated by the synthesis of a single phase-locked loop can be shared uniformly through the two phase-locked loops, and therefore the purpose of reducing the phase noise deterioration is achieved. The auxiliary loop phase-locked circuit synthesizes a section of higher frequency signal, and adopts high phase discrimination frequency to obtain broadband and large-step signal output, so that the phase noise deterioration is less because the phase discrimination frequency is high. And the lower narrow-band frequency generated by mixing the auxiliary loop and the main loop has low phase-locked frequency, so that the frequency dividing ratio N is not too large, and the phase noise deterioration is less. Therefore, the intra-loop double-loop mixing phase-locking synthesis method formed by the method not only realizes the output of high-frequency, wide-band and small-step signals, but also obtains better phase noise and higher spurious suppression.
Because the frequency of the main loop reference signal is variable, the step is extremely small, and therefore the C-band high-performance frequency synthesis system can obtain very fine steps. The main loop reference input can typically be implemented using the output signal of a DDS digital direct synthesizer.
The specific implementation method of the C-band high-performance frequency synthesis system of the present invention is as follows.
Firstly, a second reference signal of 100MHz is input, a signal of 6900 MHz-7400 MHz frequency is synthesized by an auxiliary loop phase-locked circuit, and the signal is used as the radio frequency input of the in-loop mixing. And the main loop phase-locked circuit generates a signal with the frequency of 7800 MHz-8200 MHz as a local oscillator input. And mixing the two signals to make difference, obtaining an intermediate frequency signal of 800-900 MHz, and then entering a main loop phase discriminator to carry out phase-locked synthesis.
The frequency of a first reference signal input into the main loop phase-locked circuit is designed to be 50 MHz-56.25 MHz, a frequency signal of 800-900 MHz is synthesized, and the frequency dividing ratio N value of the phase discriminator is 16.
After the auxiliary ring locking circuit is locked, the auxiliary ring locking circuit and the main ring locking circuit are mixed to generate a difference frequency signal of 800-900 MHz, frequency division is carried out by 16, then phase frequency discrimination and phase discrimination are carried out on the difference frequency signal and a first reference signal (50-56.25 MHz) to form an error signal, an error level is generated through loop filtering, an electric speed is regulated to the voltage-controlled oscillator, and the output frequency of the voltage-controlled oscillator is changed along with the voltage regulation of the electric speed. The voltage-controlled oscillator output signal of the main loop phase-locked circuit is mixed with the output signal of the auxiliary loop phase-locked circuit again, so that the difference frequency signal always falls in the frequency band range of 800-900 MHz. And in a cycle, closed loop locking is carried out so as to form a complete double-loop closed loop mixing phase locking source.
The synthetic frequency of the auxiliary loop phase-locked circuit is 6900 MHz-7400 MHz, the frequency step is determined by the frequency of the second phase discriminator, the phase discrimination is carried out according to the frequency of 100MHz, and the frequency step is 100 MHz. During frequency hopping, the main loop frequency can be linked with the auxiliary loop. When the synthesized signal of the phase-locked circuit changes in the frequency range of 6900 MHz-7400 MHz according to 100MHz step, the synthesized signal of the corresponding main loop phase-locked circuit will step in the frequency range of 7800 MHz-8200 MHz according to 100MHz and follow the frequency change of the auxiliary loop.
The radio frequency of the first phase detector of the main loop phase-locked circuit is obtained by mixing the output of the auxiliary loop and the output of the main loop, the difference frequency always falls in the range of 800-900 MHz, and the bandwidth is 100 MHz. The frequency of a first reference signal input by the main loop phase-locked circuit changes within the range of 50 MHz-56.25 MHz, and the frequency division N of the main loop is 16. The step of the main loop frequency is determined by the reference step, when the reference frequency is changed according to the step, the phase lock is 16 times frequency, and the main loop frequency step is changed according to the step of 16 times reference frequency. When frequency hopping is carried out, when the reference frequency is changed within the range of 50 MHz-56.25 MHz, the synthetic frequency range of the corresponding phase-locked circuit is changed by 100 MHz.
Therefore, through the linkage work of the main ring and the auxiliary ring, the change of the reference 1 frequency and the frequency of the phase-locked circuit is coordinately controlled, and the generation of the stepping signal with the frequency range of 7800 MHz-8200 MHz and the stepping of 1KHZ or even smaller can be realized.
The frequency mixing circuit obtains signals after the main loop and the auxiliary loop output frequency mixing, and the signals are filtered and amplified to filter out intermediate frequency higher harmonics and frequency mixing intermodulation signals. The circuit adopts high isolation mixer, and the local oscillator drive adopts high isolation amplifier, prevents like this that the mixer from revealing the signal anti-cluster and getting into the main road, forms stray signal.
The utility model discloses following beneficial effect has:
1. by adopting the intra-loop double-loop mixing phase-locking frequency synthesis mode, the method realizes lower phase noise, extremely small frequency stepping, wider frequency bandwidth coverage and higher frequency hopping speed.
2. In the auxiliary loop phase-locked circuit, the second phase discriminator has high working frequency, can synthesize higher frequency and wider frequency bandwidth on the premise of ensuring better phase noise, and simultaneously realizes higher frequency hopping speed.
3. In the main loop phase-locked circuit, the radio frequency input frequency of the first phase detector is low, and the frequency dividing ratio is small. Therefore, the reference signal input with the frequency step being extremely small and the frequency range being variable can be adopted for the reference, so that the extremely small frequency step is obtained, and simultaneously, the higher spurious suppression is obtained.
4. The C-band high-performance frequency synthesis system mixing circuit adopts a high-isolation mixer, and a local oscillator end drive adopts a high-isolation amplifier, so that the mixing signals can be prevented from entering a main path in an anti-series mode to form stray signals.
5. The internal circuit adopts the metal shielding case to keep apart, has prevented that the signal from crossing each other, prevents simultaneously that the signal from revealing the outside, has improved the isolation greatly.
6. The frequency synthesizer is simple, independent and convenient to use, small in size, low in power consumption and low in cost, and can be used as a basic component of a complex frequency synthesis system.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
The above embodiments are only specific embodiments of the present invention, and the description thereof is specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, many variations and modifications are possible without departing from the inventive concept, and such obvious alternatives fall within the scope of the invention.
Claims (10)
1. A C-band high-performance frequency synthesis system is characterized in that:
the device comprises a main loop phase-locked circuit for processing a first reference signal, an auxiliary loop phase-locked circuit for processing a second reference signal and a mixing amplification circuit;
the main loop phase-locked circuit comprises a first phase detector, a first loop filter, a first voltage-controlled oscillator and a first power divider which are sequentially connected;
the auxiliary loop phase-locked circuit comprises a second phase discriminator, a second loop filter, a second voltage-controlled oscillator and a second power divider which are connected in sequence;
the first power divider forms an output signal and a first feedback signal respectively, the second power divider forms a second feedback signal and a third feedback signal, the third feedback signal is fed back to the second phase discriminator, and the first feedback signal and the second feedback signal are fed back to the first phase discriminator through the mixing amplification circuit.
2. The C-band high performance frequency synthesis system of claim 1, wherein: the frequency mixing amplifying circuit comprises a second amplifier, a frequency mixer, a first amplifier and a band-pass filter which are sequentially connected, wherein the first power divider is connected with the input end of the second amplifier, and the second power divider is connected with the input end of the frequency mixer.
3. The C-band high performance frequency synthesis system of claim 2, wherein: the frequency of the first reference signal is 50-56.25MHz, and the frequency of the second reference signal is 100 MHz.
4. The C-band high performance frequency synthesis system of claim 3, wherein: the signal frequency of the first power divider is 7.8-8.2GHz, and the signal frequency of the second power divider is 6.9-7.4 GHz.
5. The C-band high performance frequency synthesis system of claim 4, wherein: the model of first phase detector, second phase detector is HMC704LP4E, the frequency division ratio N value of first phase detector is 16, the frequency division ratio N value of second phase detector is 69 ~ 74.
6. The C-band high performance frequency synthesis system of claim 5, wherein: the models of the first power divider and the second power divider are EP2C +.
7. The C-band high performance frequency synthesis system of claim 6, wherein: the first voltage-controlled oscillator is of the type HMC506LP4E, and the second voltage-controlled oscillator is of the type HMC505LP 4E.
8. The C-band high performance frequency synthesis system of claim 7, wherein: the mixer model is HMC558LC 3B.
9. The C-band high performance frequency synthesis system of claim 8, wherein: the first loop filter and the second loop filter are active loop filters.
10. The C-band high performance frequency synthesis system of claim 9, wherein: the second amplifier is a high isolation amplifier HMC564LC4 and the first amplifier is NBB-400.
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| CN114978156A (en) * | 2022-06-28 | 2022-08-30 | 成都西科微波通讯有限公司 | Method for realizing fine stepping frequency |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114978156A (en) * | 2022-06-28 | 2022-08-30 | 成都西科微波通讯有限公司 | Method for realizing fine stepping frequency |
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