CN211826214U - Peak current detection circuit without sampling resistor - Google Patents
Peak current detection circuit without sampling resistor Download PDFInfo
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- CN211826214U CN211826214U CN202020286547.3U CN202020286547U CN211826214U CN 211826214 U CN211826214 U CN 211826214U CN 202020286547 U CN202020286547 U CN 202020286547U CN 211826214 U CN211826214 U CN 211826214U
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Abstract
The utility model relates to a power management field discloses no sampling resistance's peak current detection circuit, including proportion current conversion circuit and voltage comparison circuit, proportion current conversion circuit inserts external current, is disposed and is converted external current into voltage output, and voltage comparison circuit is connected to proportion current conversion circuit's output electricity, and voltage comparison circuit still electricity connects reference voltage. The utility model discloses a convert external current into voltage and carry out the comparison with the reference voltage who sets up in advance, when being higher than reference voltage, the signal of telecommunication is sent to voltage comparison circuit output, realizes peak current detection, need not be in extra connection sampling resistance, simplifies peripheral application scheme, practices thrift the cost.
Description
Technical Field
The utility model relates to a power management field, concretely relates to peak current detection circuit who does not have sampling resistor.
Background
In a power circuit, in order to ensure normal operation of the power circuit, a power management chip is commonly used to perform voltage detection, current detection, peak current detection, and the like on the power circuit.
When the current detection or peak current detection is performed by the conventional power management chip, a sampling resistor needs to be connected to the periphery of the chip, and the current of the power circuit is obtained by sampling the voltage at two ends of the sampling resistor.
SUMMERY OF THE UTILITY MODEL
In view of the not enough of background art, the utility model provides a peak current detection circuit of no sampling resistor, the technical problem that solve is that current power management chip need connect sampling resistor at the periphery when peak current detects, and application scheme is complicated, and is with high costs moreover.
For solving the technical problem, the utility model provides a following technical scheme: the peak current detection circuit without the sampling resistor comprises a proportional current conversion circuit and a voltage comparison circuit, wherein the proportional current conversion circuit is connected with external current and is configured to convert the external current into voltage for output, the output end of the proportional current conversion circuit is electrically connected with the voltage comparison circuit, and the voltage comparison circuit is also electrically connected with reference voltage.
Further, the proportional current conversion circuit comprises a triode NPN1, a diode D1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first PMOS transistor MP1, a second PMOS transistor MP2, a first operational amplifier a1, and a resistor R1; a collector of the triode NPN1 is connected to an external current, an emitter of the triode NPN1 is respectively electrically connected to an anode of the diode D1, a drain of the first NMOS tube MN1 and a positive input end of the first operational amplifier a1, a gate of the first NMOS tube MN1 is electrically connected to a gate of the second NMOS tube MN2, and a source of the first NMOS tube MN1 and a source of the second NMOS tube MN2 are both grounded; the source electrode of the first PMOS transistor MP1 and the source electrode of the second PMOS transistor MP2 are both connected to a power supply V2, the gate electrode of the first PMOS transistor MP1 is electrically connected to the gate electrode of the second PMOS transistor MP2, the source electrode of the first PMOS transistor MP1 and the drain electrode of the third NMOS transistor MN3, the source electrode of the third NMOS transistor MN3 is electrically connected to the drain electrode of the second NMOS transistor MN2 and the negative input terminal of the first operational amplifier a1, the output terminal of the first operational amplifier a1 is electrically connected to the gate electrode of the third NMOS transistor MN3, and the drain electrode of the second PMOS transistor MP2 is grounded through a resistor R1.
The drain voltage of the first NMOS transistor MN1 and the drain voltage of the second NMOS transistor MN2 are made to be the same by the first operational amplifier a1, and when the gate voltage, the drain voltage and the source voltage of the first NMOS transistor MN1 and the second NMOS transistor MN2 are the same, the width-to-length ratio of the first NMOS transistor MN1 to the second NMOS transistor MN2 is the ratio of the currents flowing through the two NMOS transistors.
The first PMOS transistor MP1 and the second PMOS transistor MP2 are proportional current sources, and the width-to-length ratio is the current ratio of the two PMOS transistors.
The voltage comparison circuit comprises a first voltage comparator CMP1, wherein the positive input end of the first voltage comparator CMP1 is electrically connected with the drain electrode of the second PMOS transistor MP2, and the negative input end of the first voltage comparator CMP1 is electrically connected with a reference voltage.
Since the transistor NPN1 is connected in series with the first NMOS transistor MN1, the current inputted to the transistor from the outside is the on-state current I of the first NMOS transistor MN1MN1. Assuming that the width-to-length ratio of the first NMOS transistor MN1 to the second NMOS transistor MN2 is M and the width-to-length ratio of the first PMOS transistor MP1 to the second PMOS transistor MP2 is N, the voltage VR1 across the resistor R1 is IMN1R1/(M × N), when the VR1 is higher than the reference voltage connected to the negative input terminal of the first voltage comparator CMP1, the output signal of the first voltage comparator CMP1 changes, so that the peak current detection can be realized by setting the magnitude of the reference voltage.
The output end of the first voltage comparator CMP1 is electrically connected with a logic circuit, the logic circuit is electrically connected with a capacitor charging and discharging circuit, and the capacitor charging and discharging circuit is configured to control the on and off of the triode NPN1 and the first NMOS transistor MN 1.
The capacitor charging and discharging circuit comprises a capacitor C1, a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a second operational amplifier A2, a second voltage comparator CMP2, a third voltage comparator CMP3, a resistor R2 and a resistor R3; a power supply V2 charges a capacitor C1 through a first switch K1, the capacitor C1 discharges through a second switch K2, a positive input end of a second operational amplifier A2 is electrically connected with the power supply VM, output ends of a second operational amplifier A2 are respectively electrically connected with a negative input end of the second operational amplifier A2, a resistor R2 and one end of a third switch K3, the other end of the third switch K3 is respectively electrically connected with a capacitor C1, the positive input end of a second voltage comparator CMP2 and the positive input end of a third voltage comparator CMP3, a resistor R2 is electrically connected with one end of a resistor R3 through a fourth switch K4, the other end of the resistor R3 is electrically connected with the negative input end of a second voltage comparator CMP2, the output end of the second voltage comparator CMP2 is electrically connected with the grid electrode of a first NMOS tube MN1 through an NMOS tube driving circuit, the negative input end of a third voltage comparator CMP3 is electrically connected with a power supply VM, and the output end of the third voltage comparator CMP3 is electrically connected with the base electrode of an NPN triode 1 through a base electrode driving circuit.
Compared with the prior art, the utility model beneficial effect who has is: when the peak current detection circuit is used, a sampling resistor is not required to be connected to the periphery, external current is connected to a collector of the triode NPN1, the external current is converted into voltage through the proportional current conversion circuit and then is input to the first voltage comparator CMP1, therefore, current peak detection can be achieved by setting reference voltage connected with the negative input end of the first voltage comparator CMP1, the sampling resistor is not required to be additionally connected, a peripheral application scheme is simplified, and cost is saved.
Drawings
The utility model discloses there is following figure:
FIG. 1 is a schematic diagram of the present invention;
fig. 2 is a waveform diagram of the present invention in use.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic drawings and illustrate the basic structure of the present invention only in a schematic manner, and thus show only the components related to the present invention.
As shown in fig. 1, the peak current detection circuit without a sampling resistor includes a proportional current conversion circuit 4 and a voltage comparison circuit 5, the proportional current conversion circuit 4 is connected to an external current and configured to convert the external current into a voltage output, an output terminal of the proportional current conversion circuit 4 is electrically connected to the voltage comparison circuit 5, and the voltage comparison circuit 5 is further electrically connected to a reference voltage VREF.
The proportional current conversion circuit 4 comprises a triode NPN1, a diode D1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first PMOS transistor MP1, a second PMOS transistor MP2, a first operational amplifier a1 and a resistor R1; a collector of the triode NPN1 is connected to an external current, an emitter of the triode NPN1 is respectively electrically connected to an anode of the diode D1, a drain of the first NMOS tube MN1 and a positive input end of the first operational amplifier a1, a gate of the first NMOS tube MN1 is electrically connected to a gate of the second NMOS tube MN2, and a source of the first NMOS tube MN1 and a source of the second NMOS tube MN2 are both grounded; the source electrode of the first PMOS transistor MP1 and the source electrode of the second PMOS transistor MP2 are both connected to a power supply V2, the gate electrode of the first PMOS transistor MP1 is electrically connected to the gate electrode of the second PMOS transistor MP2, the source electrode of the first PMOS transistor MP1 and the drain electrode of the third NMOS transistor MN3, the source electrode of the third NMOS transistor MN3 is electrically connected to the drain electrode of the second NMOS transistor MN2 and the negative input terminal of the first operational amplifier a1, the output terminal of the first operational amplifier a1 is electrically connected to the gate electrode of the third NMOS transistor MN3, and the drain electrode of the second PMOS transistor MP2 is grounded through a resistor R1.
The voltage comparison circuit 5 includes a first voltage comparator CMP1, a positive input terminal of the first voltage comparator CMP1 is electrically connected to the drain of the second PMOS transistor MP2, and a negative input terminal of the first voltage comparator CMP1 is electrically connected to the reference voltage VREF.
The output end of the first voltage comparator CMP1 is electrically connected to the logic circuit 1, the logic circuit 1 is electrically connected to the capacitor charge-discharge circuit 6, and the capacitor charge-discharge circuit 6 is configured to control the on/off of the transistor NPN1 and the first NMOS transistor MN 1.
In order to ensure that the current is in a peak state when peak current detection is performed, the capacitor charging and discharging circuit 6 comprises a capacitor C1, a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a second operational amplifier a2, a second voltage comparator CMP2, a third voltage comparator CMP3, and resistors R2 and R3; a power supply V2 charges a capacitor C1 through a first switch K1, the capacitor C1 discharges through a second switch K2, a positive input end of a second operational amplifier A2 is electrically connected with the power supply VM, output ends of a second operational amplifier A2 are respectively electrically connected with a negative input end of the second operational amplifier A2, a resistor R2 and one end of a third switch K3, the other end of the third switch K3 is respectively electrically connected with a capacitor C1, the positive input end of a second voltage comparator CMP2 and the positive input end of a third voltage comparator CMP3, a resistor R2 is electrically connected with one end of a resistor R3 through a fourth switch K4, the other end of the resistor R3 is electrically connected with the negative input end of a second voltage comparator CMP2, the output end of the second voltage comparator CMP2 is electrically connected with the grid electrode of a first NMOS tube MN1 through an NMOS tube driving circuit, the negative input end of a third voltage comparator CMP3 is electrically connected with a power supply VM, and the output end of the third voltage comparator CMP3 is electrically connected with the base electrode of an NPN triode 1 through a base electrode driving circuit. The logic circuit 1 controls the on and off of the first switch K1, the second switch K2, the third switch K3 and the fourth switch K4.
The utility model discloses the theory of operation as follows: the width-to-length ratio of the first NMOS transistor MN1 to the second NMOS transistor MN2 is M, and since the gate voltage, the drain voltage and the source voltage of the first NMOS transistor MN1 and the second NMOS transistor MN2 are the same, the current I flowing through the first NMOS transistor MN1MN1And current I of second NMOS transistor MN2MN2The ratio is only: i isMN2＝IMN1/M, current IMN1Is the same as the external current that is coupled to transistor NPN 1. The first PMOS transistor MP1 and the second PMOS transistor MP2 are proportional current sources, have a width-to-length ratio N, and flow the current I of the first PMOS transistor MP1MP1And current I of second PMOS transistor MP2MP2The ratio of the components is as follows: i isMP2＝IMP1N, then the voltage VR1 across the resistor R1 is IMN1R1/(M × N). The peak current is detected by comparing the voltage VR1 and the reference voltage VREF through the first voltage comparator CMP 1.
The peak current detection circuit has two working states, namely a demagnetization state and a detection state. When the power supply VM is in a demagnetizing state, the triode NPN1 is turned off, the third switch K3 is turned on, the fourth switch K4 is turned on, and the power supply VM charges the capacitor C1 through the second operational amplifier a2 and charges the capacitor C2 through the fourth switch K4, so that the voltage on the capacitor C1 is VM and is maintained. When the circuit is in a detection state, the triode NPN1 is opened, the third switch K3 and the fourth switch K4 are both opened, the second switch K2 is closed, then the capacitor C1 starts discharging through the second switch K2 and with a current of the magnitude of I2, the comparators of the second voltage comparator CMP2 and the third voltage comparator CMP3 do not work during discharging, and the voltage at the two ends of the resistor R1 can follow the current I to enable the current I to flow through the comparatorMN1Increase and gradually riseWhen the voltage of the capacitor C1 is charged to the voltage of V1, the second voltage comparator CMP2 is turned over, SD _ N outputs a high potential, the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned off, the current of the NPN1 charges the VCC through the diode D1 connected to the emitter thereof until the voltage of the capacitor C1 is charged to VM, the third voltage comparator CMP3 is turned over, SD _ B outputs a high potential, the NPN1 is turned off, peak detection is finished, and the system enters a demagnetization mode.
V1 is the power supply VM obtained by the second operational amplifier a2 and the resistor R2, and its magnitude is V1 ═ VM-R2 ═ I3, and the power supply VM may be a 5V power supply or a 7V power supply.
After the transistor NPN1 is turned on, the voltage on the capacitor C1 starts to discharge from VM until the first voltage comparator CMP1 flips, at which time the discharge time is T2, and then the capacitor C1 starts to charge, and the charging time is T1.
As shown in fig. 2, by controlling the ratio of T1 and T2 and the magnitude of VREF, the peak current inp 1 of the transistor NPN1 can be calculated. Let I1: i2 ═ K: 1, T1: t2 ═ 1: k, the peak current IPK _ NPN1 of inp 1 (VREF × M × N (K +1))/(R1 × K).
In light of the above, the present invention is not limited to the above embodiments, and various changes and modifications can be made by the worker without departing from the scope of the present invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (5)
1. The peak current detection circuit without the sampling resistor is characterized in that: the voltage comparison circuit is electrically connected with the reference voltage.
2. The peak current detection circuit without a sampling resistor according to claim 1, characterized in that: the proportional current conversion circuit comprises a triode NPN1, a diode D1, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a first PMOS tube MP1, a second PMOS tube MP2, a first operational amplifier A1 and a resistor R1, wherein a collector of the triode NPN1 is connected with external current, an emitter of the triode NPN1 is respectively and electrically connected with the anode of the diode D1, the drain of the first NMOS tube MN1 and the positive input end of the first operational amplifier A1, the gate of the first NMOS tube MN1 is electrically connected with the gate of the second NMOS tube MN2, and the source of the first NMOS tube MN1 and the source of the second NMOS tube MN2 are both grounded; the source electrode of the first PMOS tube MP1 and the source electrode of the second PMOS tube MP2 are both connected to a power supply V2, the grid electrode of the first PMOS tube MP1 is respectively and electrically connected with the grid electrode of the second PMOS tube MP2, the source electrode of the first PMOS tube MP1 and the drain electrode of a third NMOS tube MN3, the source electrode of the third NMOS tube MN3 is respectively and electrically connected with the drain electrode of the second NMOS tube MN2 and the negative input end of a first operational amplifier A1, the output end of the first operational amplifier A1 is electrically connected with the grid electrode of the third NMOS tube MN3, and the drain electrode of the second PMOS tube MP2 is grounded through a resistor R1.
3. The peak current detection circuit without a sampling resistor according to claim 2, characterized in that: the voltage comparison circuit comprises a first voltage comparator CMP1, wherein the positive input end of the first voltage comparator CMP1 is electrically connected with the drain electrode of the second PMOS tube MP2, and the negative input end of the first voltage comparator CMP1 is electrically connected with a reference voltage.
4. The peak current detection circuit without a sampling resistor according to claim 3, wherein: the output end of the first voltage comparator CMP1 is electrically connected with a logic circuit, the logic circuit is electrically connected with a capacitor charging and discharging circuit, and the capacitor charging and discharging circuit is configured to control the on and off of the triode NPN1 and the first NMOS transistor MN 1.
5. The peak current detection circuit without a sampling resistor according to claim 4, wherein: the capacitor charging and discharging circuit comprises a capacitor C1, a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a second operational amplifier A2, a second voltage comparator CMP2, a third voltage comparator CMP3, a resistor R2 and a resistor R3; the power supply V2 charges a capacitor C1 through a first switch K1, the capacitor C1 discharges through a second switch K2, a positive input end of a second operational amplifier A2 is electrically connected with the power supply VM, output ends of a second operational amplifier A2 are respectively electrically connected with a negative input end of the second operational amplifier A2, a resistor R2 and one end of a third switch K3, the other end of the third switch K3 is respectively electrically connected with a capacitor C1, a positive input end of a second voltage comparator CMP2 and a positive input end of a third voltage comparator CMP3, the resistor R2 is electrically connected with one end of the resistor R3 through a fourth switch K4, the other end of the resistor R3 is electrically connected with a negative input end of a second voltage comparator CMP2, an output end of the second voltage comparator CMP2 is electrically connected with a grid electrode of a first NMOS tube MN1 through an NMOS tube driving circuit, a negative input end of a third voltage comparator CMP3 is electrically connected with a power supply VM, and an output end of the third voltage comparator CMP3 is electrically connected with a base electrode of a triode NPN1 through a base electrode driving circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020286547.3U CN211826214U (en) | 2020-03-10 | 2020-03-10 | Peak current detection circuit without sampling resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020286547.3U CN211826214U (en) | 2020-03-10 | 2020-03-10 | Peak current detection circuit without sampling resistor |
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| Publication Number | Publication Date |
|---|---|
| CN211826214U true CN211826214U (en) | 2020-10-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020286547.3U Active CN211826214U (en) | 2020-03-10 | 2020-03-10 | Peak current detection circuit without sampling resistor |
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|---|---|
| CN (1) | CN211826214U (en) |
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- 2020-03-10 CN CN202020286547.3U patent/CN211826214U/en active Active
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