CN211790729U - High-low voltage protection circuit - Google Patents
High-low voltage protection circuit Download PDFInfo
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- CN211790729U CN211790729U CN202020776670.3U CN202020776670U CN211790729U CN 211790729 U CN211790729 U CN 211790729U CN 202020776670 U CN202020776670 U CN 202020776670U CN 211790729 U CN211790729 U CN 211790729U
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Abstract
The utility model relates to a power management field discloses a high low-voltage protection circuit, including voltage conversion module, undervoltage locking module, reference voltage module, oscillator, time-recorder, voltage detection module, logic control module, drive circuit and MOS pipe, voltage conversion module converts busbar voltage into operating voltage, and undervoltage locking module is in output enable signal when operating voltage is higher than the start voltage of settlement, reference voltage module to voltage detection module input reference voltage, and voltage detection module detects busbar voltage, and logic control module leads to or closes through drive circuit control MOS pipe. The utility model relates to a novelty carries out voltage protection when busbar voltage is too high or low excessively, for opening circuit between messenger control circuit system and the generating line, and then prevents that circuit control system from damaging because of busbar voltage fluctuation is too big.
Description
Technical Field
The utility model relates to a power management field, concretely relates to high-low voltage protection circuit.
Background
As shown in fig. 1, the input AC voltage range of a common AC-DC power adapter or AC-DC control circuit system is 85V-300V, but the grid voltage of some countries or regions is unstable, and the amplitude thereof may exceed this range, and the withstand voltage of the input capacitor C1 on the AC-DC bus is generally 400V, as shown in fig. 1, when the input AC voltage exceeds 300V, the rectified DC voltage thereof is 424V, and exceeds the withstand voltage of the input capacitor C1, which may cause the input capacitor C1 to be damaged or explode. If the input capacitor C1 of a higher withstand voltage specification is used, the manufacturing cost of the system increases. In addition, if the bus bar input alternating voltage is too low, the control chip circuit is easily damaged due to too large stress.
SUMMERY OF THE UTILITY MODEL
In view of the not enough of background art, the utility model provides a high-low voltage protection circuit opens protect function when detecting input bus alternating voltage too high or too low, protection input electric capacity and control chip make it work in normal bus alternating voltage all the time.
For solving the technical problem, the utility model provides a following technical scheme: a high-low voltage protection circuit comprises a voltage conversion module, an under-voltage locking module, a reference voltage module, an oscillator, a timer, a voltage detection module, a logic control module, a driving circuit and an MOS (metal oxide semiconductor) tube;
the voltage conversion module converts the bus voltage into working voltage;
the under-voltage locking module outputs a starting signal when the working voltage is higher than a set starting voltage;
the reference voltage module inputs a reference voltage VUP, a reference voltage VDN and a reference voltage VST to the voltage detection module, the reference voltage VUP is used for judging whether the bus voltage is higher than a high-voltage threshold value, the reference voltage VDN is used for judging whether the bus voltage is lower than a low-voltage threshold value, and the reference voltage VST is used for detecting whether the bus voltage is smaller than the starting voltage of the MOS tube or not during initial power-on;
the voltage detection module comprises a sampling circuit, a first voltage comparator, a second voltage comparator and a third voltage comparator, wherein the sampling circuit samples the bus voltage and inputs the sampled voltage to a positive input end of the first voltage comparator, a negative input end of the second voltage comparator and a negative input end of the third voltage comparator, the negative input end of the first voltage comparator is connected with a reference voltage VUP, the positive input end of the second voltage comparator is connected with a reference voltage VDN, the positive input end of the third voltage comparator is connected with a reference voltage VST, and output ends of the first voltage comparator, the second voltage comparator and the third voltage comparator are electrically connected with the logic control module;
the logic control module respectively inputs a driving signal to the driving circuit and a control signal to the oscillator, the output end of the driving circuit is electrically connected with the grid electrode of the MOS tube, the source electrode of the MOS tube is electrically connected with a peripheral circuit, the drain electrode of the MOS tube is grounded, the timer times according to the output signal of the oscillator and inputs a timed signal to the logic control module after the timed time is up.
The overcurrent detection module is characterized by further comprising an overcurrent detection module, one input end of the overcurrent detection module is electrically connected with one end of the sampling resistor RCS and the drain electrode of the MOS tube respectively, the other input end of the overcurrent detection module is connected with an overcurrent reference voltage, the output end of the overcurrent detection module is electrically connected with the logic module, and the other end of the sampling resistor RCS is grounded.
Further, the sampling circuit includes a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4 and a resistor R1, a drain of the third NMOS tube is electrically connected to a gate of the third NMOS tube N3, a gate of the fourth NMOS tube N4 and one end of the sampling resistor RUP, a drain of the sampling resistor RUP is connected to the bus, a source of the third NMOS tube N3 is electrically connected to a drain of the first NMOS tube N1, a gate of the first NMOS tube N1 and a gate of the second NMOS tube N2, a source of the first NMOS tube N1 and a source of the second NMOS tube N9 are both grounded, a source of the first PMOS tube P1 and a source of the second PMOS tube P56 are both connected to a power supply, a gate of the first PMOS tube P1 is electrically connected to a drain of the second PMOS tube N27, a source of the first PMOS tube P2, a drain of the first PMOS tube P867 and a drain of the fourth PMOS tube P8658, the grid electrode of the third PMOS tube P3 is respectively and electrically connected with the grid electrode of the fourth PMOS tube P4, the drain electrode of the third PMOS tube P3 and the drain electrode of the fourth NMOS tube N4, the drain electrode of the fourth PMOS tube P4 is respectively and electrically connected with the positive input end of the first voltage comparator, the negative input end of the second voltage comparator, the negative input end of the third voltage comparator and one end of the resistor R1, and the other end of the resistor R1 is grounded.
Compared with the prior art, the utility model beneficial effect who has is: through this high-low voltage protection circuit, when power adapter or other control circuit system access buses, if bus voltage appears undulantly, this high-low voltage protection circuit can in time form between bus and power adapter and open circuit when power adapter's input voltage scope not, and then protection power adapter avoids bus voltage's impact and damages, prevent that input bus electric capacity from appearing damaging or explosion, can also prevent in addition when bus voltage is too low that power adapter's control chip circuit from damaging because of stress is too big.
Drawings
The utility model discloses there is following figure:
FIG. 1 is a block diagram of a typical AC-DC control system;
FIG. 2 is a system configuration diagram of the present invention;
fig. 3 is a circuit diagram of the voltage detection module of the present invention;
FIG. 4 is a circuit diagram of the present invention;
fig. 5 is a schematic diagram of bus voltage for starting the MOS transistor according to the present invention;
fig. 6 is a schematic diagram of bus voltage for overvoltage protection according to the present invention;
fig. 7 is a schematic diagram of the bus voltage for low voltage protection according to the present invention;
fig. 8 is a flowchart of the present invention.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic drawings and illustrate the basic structure of the present invention only in a schematic manner, and thus show only the components related to the present invention.
As shown in fig. 2-3, a high-low voltage protection circuit includes a voltage conversion module, an under-voltage locking module, a reference voltage module, an oscillator, a timer, a voltage detection module, a logic control module, a driving circuit, an over-current detection module, and an MOS transistor, where the MOS transistor is a high-voltage MOSFET;
the voltage conversion module converts the bus voltage into working voltage;
the undervoltage locking module, namely UVLO, outputs a starting signal when the working voltage is higher than the set starting voltage;
the reference voltage module inputs a reference voltage VUP, a reference voltage VDN and a reference voltage VST to the voltage detection module, the reference voltage VUP is used for judging whether the bus voltage is higher than a high-voltage threshold value, the reference voltage VDN is used for judging whether the bus voltage is lower than a low-voltage threshold value, and the reference voltage VST is used for detecting whether the bus voltage is smaller than the starting voltage of the MOS tube or not when the MOS tube is initially electrified, in the embodiment, the VUP is 1.05V, the VDN is 0.3V, and the VST is 0.1V;
the voltage detection module comprises a sampling circuit, a first voltage comparator, a second voltage comparator and a third voltage comparator, wherein the sampling circuit comprises a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4 and a resistor R1, the drain electrode of the third NMOS tube is respectively and electrically connected with the gate electrode of the third NMOS tube N3, the gate electrode of the fourth NMOS tube N4 and one end of a sampling resistor RUP, the other end of the sampling resistor RUP is connected to a bus, the source electrode of the third NMOS tube N3 is respectively and electrically connected with the drain electrode of the first NMOS tube N1, the gate electrode of the first NMOS tube N1 and the gate electrode of the second NMOS tube N2, the source electrode of the first NMOS tube N1 and the source electrode of the second NMOS tube N635 are both grounded, the source electrode of the first PMOS tube P1 and the source electrode of the second PMOS tube P2 are respectively and the drain electrode of the PMOS tube P599, the drain electrode of the second PMOS tube P2 is electrically connected with the source electrode of the fourth PMOS tube P4, the grid electrode of the third PMOS tube P3 is electrically connected with the grid electrode of the fourth PMOS tube P4, the drain electrode of the third PMOS tube P3 and the drain electrode of the fourth NMOS tube N4 respectively, the drain electrode of the fourth PMOS tube P4 is electrically connected with the positive input end of the first voltage comparator, the negative input end of the second voltage comparator, the negative input end of the third voltage comparator and one end of the resistor R1 respectively, and the other end of the resistor R1 is grounded.
The working principle of the voltage detection module is as follows: the first NMOS transistor N1 and the second NMOS transistor N2 are a pair of current proportional sources, the proportion of the current proportional sources is K1, the first PMOS transistor P1 and the second PMOS transistor P2 are also proportional current sources, the proportion of the current proportional sources is K2, the resistor R1 is also a sampling resistor, the bus voltage is converted into current through the sampling resistor RUP, and voltage is formed on the resistor R1, and the voltage is:
since VGS may be approximately equal to VT and VLN voltage is much larger than VGS voltage, the influence of the fluctuation of VGS voltage on the system can be ignored, so when VGS is set to 1V in this example, the voltage across resistor R1 is:
the voltage change of VR1 can represent the change of bus voltage, reference voltage VUP, reference voltage VDN and reference voltage VST are respectively the detection reference of bus upper voltage, the detection reference of bus lower voltage and the reference of starting voltage, and the voltage detection module compares VR1 with reference voltage VUP, reference voltage VDN and reference voltage VST respectively to judge whether the bus voltage is too high or too low, and whether the MOS tube is allowed to start.
The logic control module respectively inputs a driving signal to the driving circuit and a control signal to the oscillator, the output end of the driving circuit is electrically connected with the grid electrode of the MOS tube, the source electrode of the MOS tube is electrically connected with a peripheral circuit, the drain electrode of the MOS tube is grounded, the timer times according to the output signal of the oscillator and inputs a timed signal to the logic control module after the timed time is up.
One input end of the over-current detection module is electrically connected with one end of the sampling resistor RCS and the drain electrode of the MOS tube respectively, the other input end of the over-current detection module is connected with over-current reference voltage, the output end of the over-current detection module is electrically connected with the logic module, and the other end of the sampling resistor RCS is grounded.
At the moment that the system, i.e. the high-low voltage protection circuit, is powered on, the bus voltage may fall on any phase of the AC alternating current signal, at this time, if the logic control module turns on the high-voltage MOSFET, the voltage of the bus falling on the capacitor C1 may be a peak voltage, then the current charging the capacitor and the current flowing through the high-voltage MOSFET at this time may be very large, the transient power consumption of the high-voltage MOSFET may be very large, and even the high-voltage MOSFET may be damaged.
Therefore, at initial power-on, the high-voltage MOSFET is not turned on, that is, GND and DRN are disconnected, the bus supplies power to the voltage conversion module through LN, VCC voltage rises slowly, when VCC voltage is greater than start voltage of UVLO (this embodiment is set to 9.5V), UVLO is turned on, the system starts to detect DET pin current and enters a working state, but overvoltage and overcurrent protection detection is not performed until the DET pin current is detected to be equivalent to a voltage across an internal resistor R1 less than VST (currently set to 1/3 of VDN low-voltage detection), and the logic control module controls the high-voltage MOSFET to be turned on. After the high-voltage MOSFET is conducted, a path is formed between GND and DRN, the capacitor C1 is connected to a bus, charging from low voltage is started, charging current is small due to the fact that voltage on the capacitor C1 is low, transient power consumption of the high-voltage MOSFET is low, and the high-voltage MOSFET works in a safe area. The point a in fig. 5 is the position where the high voltage MOSFET is turned on.
When the high-voltage MOSFET is switched on, the bus voltage drops to the position A in fig. 5, the voltage detection module starts to perform low-voltage UVP detection, the oscillator starts to oscillate, the timer starts to time, within a half alternating current period (10ms), if VR1 is lower than VDN all the time, UVP protection is triggered, namely the logic control module closes the high-voltage MOSFET, timing is started simultaneously, after TDELAY is counted, the system triggers UVLO signals to start to detect again, and starts to time when the bus voltage reaches the position A again, and if VR1 is not lower than VDN within 10ms, the system starts to work normally.
As shown in fig. 7, in normal operation, if VR1 is smaller than VDN and TUVP continues, UVP protection is triggered, i.e. the logic control module controls the high voltage MOSFET to turn off and start timing, and after TDELAY is counted up, the system triggers UVLO signal to start re-detection.
As shown in fig. 6, when the bus detection voltage VR1 exceeds VUP, the system starts OVP detection and starts timing, and if VR1 is always higher than VUP within the time of Tovp, OVP protection is triggered, at this time, the system turns off the power high voltage MOSFET and starts timing, and after TDELAY is counted up, the system triggers UVLO signal to start re-detection.
The calculation formulas of the highest voltage and the lowest voltage of the bus allowed to be accessed in the current system are as follows:
if the top resistance of the DET pin is RUP, the detected top voltage is calculated as follows:
in this embodiment, if RUP is 5.1M, K1 is K2 is 30, and R1 is 42K, the protection range of AC input is 85V to 298V, the system operates normally in this interval, and the system triggers the protection function outside this interval. The range of the interval is fixed, but can be translated up and down. The range of this interval is adjusted by adjusting the RUP.
In light of the above, the present invention is not limited to the above embodiments, and various changes and modifications can be made by the worker without departing from the scope of the present invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (3)
1. A high-low voltage protection circuit, characterized in that: the device comprises a voltage conversion module, an under-voltage locking module, a reference voltage module, an oscillator, a timer, a voltage detection module, a logic control module, a driving circuit and an MOS (metal oxide semiconductor) tube;
the voltage conversion module converts the bus voltage into working voltage;
the undervoltage locking module outputs a starting signal when the working voltage is higher than a set starting voltage;
the reference voltage module inputs a reference voltage VUP, a reference voltage VDN and a reference voltage VST to the voltage detection module, the reference voltage VUP is used for judging whether the bus voltage is higher than a high-voltage threshold value, the reference voltage VDN is used for judging whether the bus voltage is lower than a low-voltage threshold value, and the reference voltage VST is used for detecting whether the bus voltage is smaller than the starting voltage of the MOS tube or not during initial power-on;
the voltage detection module comprises a sampling circuit, a first voltage comparator, a second voltage comparator and a third voltage comparator, wherein the sampling circuit samples the bus voltage and inputs the sampled voltage to a positive input end of the first voltage comparator, a negative input end of the second voltage comparator and a negative input end of the third voltage comparator, the negative input end of the first voltage comparator is connected with a reference voltage VUP, the positive input end of the second voltage comparator is connected with a reference voltage VDN, the positive input end of the third voltage comparator is connected with a reference voltage VST, and the output ends of the first voltage comparator, the second voltage comparator and the third voltage comparator are electrically connected with the logic control module;
the logic control module respectively inputs a driving signal to the driving circuit and a control signal to the oscillator, the output end of the driving circuit is electrically connected with the grid electrode of the MOS tube, the source electrode of the MOS tube is electrically connected with the peripheral circuit, the drain electrode of the MOS tube is grounded, the timer times according to the output signal of the oscillator and inputs a timed signal to the logic control module after the timed time is up.
2. The high-low voltage protection circuit of claim 1, wherein: still include and overflow the detection module, overflow the detection module's an input electricity respectively connect sampling resistor RCS one end with the drain electrode of MOS pipe, overflow another input of detection module and insert and overflow reference voltage, overflow the detection module's output electricity and connect logic module, sampling resistor RCS other end ground connection.
3. The high-low voltage protection circuit of claim 1, wherein: the sampling circuit comprises a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4 and a resistor R1, wherein the drain electrode of the third NMOS tube is respectively and electrically connected with the grid electrode of the third NMOS tube N3, the grid electrode of the fourth NMOS tube N4 and one end of a sampling resistor RUP, the other end of the sampling resistor RUP is connected to a bus, the source electrode of the third NMOS tube N3 is respectively and electrically connected with the drain electrode of the first NMOS tube N1, the grid electrode of the first NMOS tube N1 and the grid electrode of the second NMOS tube N2, the source electrode of the first NMOS tube N1 and the source electrode of the second NMOS tube N829 are both grounded, the source electrode of the first PMOS tube P695P 2 and the source electrode of the second PMOS tube P2 are both connected to a power supply, the drain electrode of the first PMOS tube P53 is respectively and the drain electrode of the PMOS tube P2 and the drain electrode of the PMOS tube P8658, the grid electrode of the third PMOS tube P3 is respectively and electrically connected with the grid electrode of the fourth PMOS tube P4, the drain electrode of the third PMOS tube P3 and the drain electrode of the fourth NMOS tube N4, the drain electrode of the fourth PMOS tube P4 is respectively and electrically connected with the positive input end of the first voltage comparator, the negative input end of the second voltage comparator, the negative input end of the third voltage comparator and one end of the resistor R1, and the other end of the resistor R1 is grounded.
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| CN202020776670.3U CN211790729U (en) | 2020-05-12 | 2020-05-12 | High-low voltage protection circuit |
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| CN202020776670.3U CN211790729U (en) | 2020-05-12 | 2020-05-12 | High-low voltage protection circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111404123A (en) * | 2020-05-12 | 2020-07-10 | 无锡恒芯微科技有限公司 | High-low voltage protection circuit |
| CN114884043A (en) * | 2022-05-25 | 2022-08-09 | 兰州万里航空机电有限责任公司 | A in same direction as year voltage control circuit that releases for machine carries linkage lift system |
-
2020
- 2020-05-12 CN CN202020776670.3U patent/CN211790729U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111404123A (en) * | 2020-05-12 | 2020-07-10 | 无锡恒芯微科技有限公司 | High-low voltage protection circuit |
| CN114884043A (en) * | 2022-05-25 | 2022-08-09 | 兰州万里航空机电有限责任公司 | A in same direction as year voltage control circuit that releases for machine carries linkage lift system |
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