CN211700264U - Low-thermal-resistance packaging structure of power semiconductor device - Google Patents
Low-thermal-resistance packaging structure of power semiconductor device Download PDFInfo
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- CN211700264U CN211700264U CN202020664167.9U CN202020664167U CN211700264U CN 211700264 U CN211700264 U CN 211700264U CN 202020664167 U CN202020664167 U CN 202020664167U CN 211700264 U CN211700264 U CN 211700264U
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Abstract
The utility model relates to a power semiconductor device low thermal resistance packaging structure, include electrode interconnection piece, power chip and the lead frame that sets gradually in the crimping plastic-sealed body, the electrode crimping area between electrode interconnection piece and the power chip is equipped with the crimping buffer layer, be connected through the pin welded layer between electrode interconnection piece and the lead frame, the chip solid crystal district periphery of lead frame is equipped with a plurality of plastic-sealed body anchor holes. Compared with the prior art, the utility model discloses realize reliable electric heat stress crimping between chip and electrode interconnection piece and lead frame, form temperature compensation type through rigid connection between crimping plastic-sealed body and lead frame, constitute the two-sided heat dissipation channel of chip, make the device obtain better electric heat characteristic and wide range safe operating region under extreme operating condition.
Description
Technical Field
The utility model relates to a semiconductor chip does not have lead wire crimping formula packaging technology, especially relates to a low thermal resistance packaging structure of power semiconductor device.
Background
The leadless press-fit type package of the semiconductor chip is a high-reliability package form of the semiconductor power chip, and is mainly applied to the package of high-power devices, such as: power ICs, MOSFETs and IGBT devices. Compared with welding packaging, the compression joint type packaging has the advantage of compact structure, can realize double-sided heat dissipation, completely eliminates failure modes related to a bonding wire and a welding layer in the traditional welding type IGBT technology, is mainly applied to packaging of a MOSFET (metal oxide semiconductor field effect transistor) and an IGBT (insulated gate bipolar transistor) high-power module (IPM), but is not reported in the aspect of semiconductor chip discrete devices.
There are currently two main forms of crimping technology:
1. a spring press-contact type represented by ABB corporation and patented;
2. the boss is press-fit, represented by TOSHIBA, WESTCODE, DYNEX and midvehicle electrical appliances.
The technical structure for realizing the crimping function in the two crimping technical forms is formed by adding a mechanical pressure element, and the defects are as follows:
A. external pressure and a spring are introduced, so that failure hidden dangers caused by uneven pressure or fatigue of the spring exist, and the improvement of the time-effect reliability of the device is restricted.
B. Due to the limitations of the additional mechanical pressure element mechanism, the crimping technology cannot be applied to power IC and discrete device packages that have severe requirements on the structural size.
C. The packaging of a high-power module (IPM) is non-airtight, and the contact between a chip and the external environment (water, gas and dust) is isolated by pouring insulating materials such as silicone gel or epoxy resin into the module, but the pouring materials usually isolate the heat transfer and the phenomenon of degradation of the isolation effect occurs in the long-term working process.
At present, because the semiconductor chip material is upgraded from the first generation to the third generation wide bandgap material, and the power density of the semiconductor power chip device is increased day by day and the requirement on the use environment is increased day by day, the existing device structure and the device manufactured by the thermosetting plastic packaging material and the injection molding (transfer molding) packaging process cannot play the excellent characteristic of the working junction temperature of the third generation wide bandgap material chip above 175 ℃ because of the limitation of the inherent characteristics of the material, the structure and the process, and cannot meet the reliability requirement of the high-power device, thereby limiting the expansion of the cost performance advantage of the third generation semiconductor device and the industrialization process of the high-order power device.
For these reasons, the development requirements of the modern semiconductor industry can be met only by making full innovations in the structure, material and process of the package.
SUMMERY OF THE UTILITY MODEL
The present invention is directed to a power semiconductor device with a low thermal resistance package structure for overcoming the above-mentioned drawbacks of the prior art.
The purpose of the utility model can be realized through the following technical scheme:
the utility model provides a power semiconductor device low heat resistance packaging structure, includes electrode interconnection piece, power chip and the lead frame that sets gradually in the crimping plastic-sealed body, the electrode crimping area between electrode interconnection piece and the power chip is equipped with the crimping buffer layer, connect through pin welded layer between electrode interconnection piece and the lead frame, the chip solid crystal district periphery of lead frame is equipped with a plurality of plastic-sealed body anchor holes.
Preferably, a chip die bonding area between the power chip and the lead frame is provided with a compression bonding die bonding layer.
Preferably, the electrode interconnection sheet is provided with a high-temperature-resistant electrically insulating coating on a side facing the lead frame between the electrode crimping regions.
Preferably, the electrode interconnection sheet is an electrode interconnection heat sink sheet having dual functions of electrical conduction and thermal diffusion.
Preferably, a temperature compensation type through rigid connection is formed between the compression molding body and the lead frame.
Preferably, the compression joint plastic package body is made of a thermoplastic high polymer material.
Preferably, the compression bonding buffer layer is specifically a compression bonding strain buffer alloy layer.
Preferably, the power chip is a back-plated metal power chip.
Preferably, the compression welding crystal layer is a vacuum compression welding alloy solder layer.
Preferably, the compression molded body is rigidly integrated with the device core component through the molded body anchoring hole.
Compared with the prior art, the utility model has the advantages of it is following:
1. the source of the crimping acting force for forming the pressure contact connection between the chip output and input electrodes and the interconnection system is changed into the strain force formed by the thermal strain difference of related structural materials in the device by an externally added mechanical pressure element, so that the reliable electrothermal stress crimping between the chip and the electrode interconnection sheet and the lead frame is realized, the temperature compensation type through rigid connection is formed between the crimping plastic package body and the lead frame, and a double-sided heat dissipation channel of the chip is formed, so that the device obtains more excellent electrothermal characteristics and a wide safe working area under extreme working conditions.
2. The compensation and recovery characteristics of the strain force formed by the thermal strain difference of the high-molecular multi-component material structure adopted by the compression-joint plastic package body are far superior to those of a unit mechanical elastic element, and the failure hidden danger of a device caused by uneven pressure or spring fatigue can be greatly reduced.
3. The invention adopts the leadless crimping surface, the crimping strain buffer alloy layer and the high-temperature-resistant electric insulation coating, thereby greatly reducing the packaging parasitic effect and improving the working reliability of the device.
4. The electrode interconnection sheet adopts an integrated structure of electrode interconnection and heat dissipation, and forms an efficient heat conduction channel with a high-strength, high-heat-conduction and high-insulation compression molding body.
5. The crimping buffer layer can compensate the temperature influence of the crimping pressure difference, Cu ions in the electrode crimping area of the isolation electrode interconnection sheet diffuse to the ohmic contact area of the chip electrode, and the possibility of low breakdown of the chip is reduced.
6. Because the packaging structure cancels additional mechanical elements, the conventional thermosetting high polymer material and injection molding (transfer molding) process are not adopted, the structural limitation is eliminated, and the compression joint type packaging technology can be applied to the packaging of power ICs and discrete devices with strict requirements on the structural size.
Drawings
Fig. 1 is a front view of the package structure of the present invention;
FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1;
fig. 3 is a sectional view taken in the direction B-B in fig. 1.
The figure is marked with: 1. the lead frame, 2, power chip, 3, electrode interconnection piece, 4, crimping plastic-sealed body, 5, high temperature resistant electrical insulation coating, 6, crimping buffer layer, 7, crimping welding solid crystal layer, 8, pin welding layer, 9, plastic-sealed body anchor hole.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The embodiment is implemented on the premise of the technical solution of the present invention, and a detailed implementation manner and a specific operation process are given, but the scope of the present invention is not limited to the following embodiments.
Examples
As shown in fig. 1, the present application provides a low thermal resistance package structure of a power semiconductor device, which includes an electrode interconnection piece 3, a power chip 2 and a lead frame 1 sequentially disposed in a compression molding body 4. The electrode crimping area between the electrode interconnection piece 3 and the power chip 2 is provided with a crimping buffer layer 6, specifically, a crimping strain buffer alloy layer in the embodiment can compensate the temperature influence of the crimping pressure difference, and the Cu ions in the electrode crimping area of the electrode interconnection piece 3 are prevented from diffusing to the ohmic contact area of the chip electrode, so that the possibility of low breakdown of the chip is reduced. A plurality of plastic package body anchoring holes 9 are formed in the periphery of a chip die bonding area of the lead frame 1, so that the compression joint plastic package body 4 and the inner core part of the device form a rigid whole through the plastic package body anchoring holes 9. The electrode interconnection sheet 3 is connected with the lead frame 1 through the pin welding layer 8, so that input and output of the power chip 2 are electrically connected.
The compression joint plastic package body 4 is made of thermoplastic polymer material. The stress difference formed by the difference between the Coefficient of Thermal Expansion (CTE) of the recrystallized material of the material for pressing the plastic package body 4 under the conditions of high temperature and high pressure and the CTE of the related heterogeneous embedded part material can generate a pressure larger than 10MPa, and the reliable pressing connection of the chip electrode and the chip interconnection piece is realized.
The electrode interconnection sheet 3 is an electrode interconnection heat sink with dual functions of electric conduction and thermal diffusion, and reduces the possibility of heat accumulation in the chip operation.
The side of the electrode interconnection sheet 3 facing the lead frame 1 between the electrode crimping areas is provided with a low-dielectric high-temperature-resistant electrically insulating coating 5, which aims to eliminate the possibility of inter-electrode short circuit caused by the deformation of the electrode interconnection sheet 3 in the high-pressure injection molding process and reduce the parasitic effect of packaging.
And a chip die bonding area between the power chip 2 and the lead frame 1 is provided with a compression welding die bonding layer 7, specifically a vacuum compression welding alloy solder layer, so that low-thermal resistance die bonding of the power chip 2 is realized.
Providing at least one power chip 2 with back-plated metal, wherein the manufacturing method for realizing the low-thermal-resistance packaging structure of the power semiconductor device comprises the following steps:
s1, respectively forming a pressure welding buffer layer 6 and a pressure welding crystal layer 7 in the electrode pressure welding area of the electrode interconnection sheet 3, and forming a high temperature resistant electric insulation coating 5 between the electrode pressure welding areas of the electrode interconnection sheet 3 and facing the lead frame 1; a compression welding crystal-fixing layer 7 is manufactured in a chip crystal-fixing area of the lead frame 1, and a plurality of plastic-sealed body anchoring holes 9 are processed on the periphery of the chip crystal-fixing area;
s2, placing the electrode interconnection sheet 3, the power chip 2 and the lead frame 1 into a positioning jig according to the requirement of a specified position, and placing the positioning jig into a vacuum compression welding machine to finish die bonding welding, electrode eutectic welding and compression buffer layer 6 coplanar joint to manufacture a device core part;
s3, the inner core part of the device is arranged in a non-remelting high-temperature high-pressure injection mould according to the requirement of a specified position, a thermoplastic high polymer material is injected in a high-temperature high-pressure mode, the compression joint plastic package body 4 and the inner core part of the device form a rigid whole through the plastic package body anchoring hole 9, the compression joint of the electrode interconnection sheet 3 and the chip electrode is realized through the internal stress difference after cooling, and the plastic package of the device is completed.
The power IC device and the high-power discrete device packaged by the technical scheme of the application are detected by a third-party national level component reliability detection mechanism, and all the purposes are achieved: AEC-Q100; AEC-Q101; class i (vehicle gauge class, military class) standard.
The scheme of the application is suitable for manufacturing the packaging structure of the discrete device for packaging a plurality of power semiconductor chips on the same carrier. The application scientifically applies the thermal strain difference parameters of related structural materials to construct a more compact structural system with engineering, greatly reduces the packaging thermal resistance of the power semiconductor device, enables the multiple power chips 2 to exert the efficiency to the maximum extent under the specified use technical conditions, enables the device to obtain more excellent electric heating characteristics and a wide safe working area (SOA) under the extreme working conditions, and obviously improves the reliability index of the device.
Claims (10)
1. The utility model provides a power semiconductor device low heat resistance packaging structure, its characterized in that includes electrode interconnection piece (3), power chip (2) and lead frame (1) that set gradually in crimping plastic-sealed body (4), the electrode crimping area between electrode interconnection piece (3) and power chip (2) is equipped with crimping buffer layer (6), be connected through pin welded layer (8) between electrode interconnection piece (3) and lead frame (1), the chip solid crystal district periphery of lead frame (1) is equipped with a plurality of plastic-sealed body anchor hole (9).
2. The power semiconductor device low thermal resistance packaging structure is characterized in that a die bonding area between the power die (2) and the lead frame (1) is provided with a pressure welding die bonding layer (7).
3. A power semiconductor device low thermal resistance packaging structure according to claim 1, characterized in that the side of the electrode interconnection sheet (3) facing the lead frame (1) between the electrode crimping areas is provided with a high temperature resistant electrically insulating coating (5).
4. The power semiconductor device low thermal resistance packaging structure is characterized in that the electrode interconnection piece (3) is an electrode interconnection cooling fin with double functions of electric conduction and thermal diffusion.
5. The power semiconductor device low thermal resistance packaging structure according to claim 1, wherein a temperature compensation through rigid connection is formed between the compression molding body (4) and the lead frame (1).
6. The power semiconductor device low thermal resistance packaging structure according to claim 1, wherein the compression molding body (4) is made of a thermoplastic polymer material.
7. The power semiconductor device low thermal resistance packaging structure according to claim 1, wherein the compression buffer layer (6) is a compression strain buffer alloy layer.
8. The power semiconductor device low thermal resistance packaging structure is characterized in that the power chip (2) is a back-plated metal power chip (2).
9. The power semiconductor device low thermal resistance packaging structure according to claim 2, wherein the press-bonding die layer (7) is a vacuum press-bonding alloy solder layer.
10. The power semiconductor device low thermal resistance packaging structure is characterized in that the compression molding body (4) is rigidly integrated with the device inner core component through the molding body anchoring hole (9).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020664167.9U CN211700264U (en) | 2020-04-27 | 2020-04-27 | Low-thermal-resistance packaging structure of power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020664167.9U CN211700264U (en) | 2020-04-27 | 2020-04-27 | Low-thermal-resistance packaging structure of power semiconductor device |
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| Publication Number | Publication Date |
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| CN211700264U true CN211700264U (en) | 2020-10-16 |
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| CN202020664167.9U Active CN211700264U (en) | 2020-04-27 | 2020-04-27 | Low-thermal-resistance packaging structure of power semiconductor device |
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- 2020-04-27 CN CN202020664167.9U patent/CN211700264U/en active Active
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