CN115995427A - Internal insulation TO packaging structure for gallium nitride field effect transistor - Google Patents
Internal insulation TO packaging structure for gallium nitride field effect transistor Download PDFInfo
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- CN115995427A CN115995427A CN202310203447.8A CN202310203447A CN115995427A CN 115995427 A CN115995427 A CN 115995427A CN 202310203447 A CN202310203447 A CN 202310203447A CN 115995427 A CN115995427 A CN 115995427A
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- gallium nitride
- ceramic substrate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The application discloses an internal insulation TO packaging structure for a gallium nitride field effect transistor, comprising: the semiconductor device comprises a heat dissipation base plate, a ceramic substrate, a gallium nitride transistor, a MOSFET, a grid electrode, a drain electrode, a source electrode and a plurality of pins; the heat dissipation bottom plate is electrically insulated from each pin; the ceramic substrate is arranged on the heat dissipation bottom plate; the gallium nitride transistor and the MOSFET are arranged on the ceramic substrate; the ceramic substrate and the gallium nitride transistor are electrically connected with the MOSFET; the grid electrode, the drain electrode and the source electrode are electrically connected with the pins and are respectively electrically connected with the ceramic substrate, the gallium nitride transistor and the MOSFET. The radiating bottom plate is electrically insulated from the ceramic substrate and the pins, so that any electrode in the radiating bottom plate and the packaging structure is electrically insulated, the structure can be enabled to have higher safety and radiating effect without additionally increasing thermal resistance, and the problems of high pressure-resistant safety risk and high thermal resistance existing in the external insulation mode of the conventional gallium nitride field effect transistor are solved.
Description
Technical Field
The application relates TO the technical field of semiconductor packaging, in particular TO an internal insulation TO packaging structure for a gallium nitride field effect transistor.
Background
TO (Transistor Outline) is a transistor package intended to enable leads to be molded and used for surface mounting and direct insertion mounting, and is widely used for power semiconductor devices; the 3-pin drain-added heat dissipation base plate (drain pins are connected with the heat dissipation base plate in the heat dissipation installation screw hole area) is widely applied. Some TO packages, such as TO-220 and TO247, can be used for GaN FET packages, typically in the form of a 3-pin plus source heat sink base (source pins are connected TO the heat sink base in the area of heat sink mounting screw holes).
The external heat spreader of the TO package is typically connected TO the ground plane of the system primary side; the source electrode heat dissipation bottom plate of the gallium nitride field effect transistor is usually a current sampling resistor connected to the middle point of a bridge arm of a bridge circuit or a flyback circuit, and the potential of the current sampling resistor is unequal to that of an external radiator. Therefore, the existing gallium nitride field effect transistor needs TO adopt an insulating sleeve or an insulating gasket plus insulating particles TO ensure the insulation between gallium nitride and a radiator, or adopts an encapsulation mode (TO-220F, TO-247F, etc.) of an all-plastic encapsulation shell.
The mode of adding insulating particles into the insulating gaskets needs manual installation by a worker, the possibility that insulating sheets are inclined to cause insulation protection not to be in place by manual operation, pressure-resistant safety risks are caused, and meanwhile, the insulating gaskets also increase extra thermal resistance of the system; the insulation sleeve and the full plastic package shell have the problem of low heat dissipation performance caused by larger heat resistance.
Disclosure of Invention
In view of this, the present application aims TO provide an internal insulation TO package structure for a gan fet, which is used TO solve the problems of high voltage-resistant safety risk and high thermal resistance of the external insulation mode of the existing gan fet.
TO achieve the above technical object, the present application provides an internal insulating TO package structure for a gallium nitride field effect transistor, including: the semiconductor device comprises a heat dissipation base plate, a ceramic substrate, a gallium nitride transistor, a MOSFET, a grid electrode, a drain electrode, a source electrode and a plurality of pins;
the heat dissipation bottom plate is electrically insulated from each pin;
the ceramic substrate is arranged on the heat dissipation base plate and is electrically insulated from the heat dissipation base plate;
the gallium nitride transistor and the MOSFET are arranged on the ceramic substrate;
the ceramic substrate, the gallium nitride transistor and the MOSFET are mutually and electrically connected;
the grid electrode, the drain electrode and the source electrode are respectively and electrically connected with the pins in a one-to-one correspondence manner;
the grid electrode is electrically connected with the MOSFET;
the drain electrode is electrically connected with the gallium nitride transistor;
the source electrode is electrically connected with the ceramic substrate.
Further, a copper plating area is arranged on the ceramic substrate;
the gallium nitride transistor and the MOSFET are arranged on the copper plating area of the ceramic substrate, and are electrically connected through a connecting piece.
Further, the gallium nitride transistor and the MOSFET are bonded to the copper-plated area of the ceramic substrate through silver paste or soft solder.
Further, the gate is electrically connected to the MOSFET through a connector;
the drain electrode is electrically connected with the gallium nitride transistor through a connecting piece;
the source electrode is electrically connected with the ceramic substrate through a connecting piece.
Further, the connecting piece is a metal wire.
Further, the gate, the drain and the source are all electrically connected with the leads by wire bonding.
Further, the MOSFET is a silicon-based MOSFET or a silicon carbide-based MOSFET.
From the above technical solution, the present application provides an internal insulation TO packaging structure for gallium nitride field effect transistor, including: the semiconductor device comprises a heat dissipation base plate, a ceramic substrate, a gallium nitride transistor, a MOSFET, a grid electrode, a drain electrode, a source electrode and a plurality of pins; the heat dissipation bottom plate is electrically insulated from each pin; the ceramic substrate is arranged on the heat dissipation bottom plate; the gallium nitride transistor and the MOSFET are arranged on the ceramic substrate; the ceramic substrate, the gallium nitride transistor and the MOSFET are mutually and electrically connected; the grid electrode, the drain electrode and the source electrode are respectively and electrically connected with the pins in a one-to-one correspondence manner; the grid electrode is electrically connected with the MOSFET; the drain electrode is electrically connected with the gallium nitride transistor; the source electrode is electrically connected with the ceramic substrate. Wherein, radiating bottom plate and ceramic substrate and pin all electric insulation can make radiating bottom plate and the arbitrary extremely electric insulation in the packaging structure, compares in current inside insulating mode, and this scheme can not additionally increase thermal resistance and possess higher security and increase radiating effect, effectively solves the inside insulating mode of current gallium nitride field effect transistor and exists withstand voltage security risk and the great problem of thermal resistance.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a schematic diagram of a connection scheme of bottom gate GaN and a vertical channel MOSFET;
FIG. 2 is a schematic diagram of a bottom gate GaN and LDMOS connection;
FIG. 3 is a schematic diagram of the connection of top gate GaN to a vertical channel MOSFET;
fig. 4 is a schematic diagram of a connection between the top gate GaN and the LDMOS.
In the figure: 10. a heat dissipation base plate; 11. a ceramic substrate; 12. a gallium nitride transistor; 13. a MOSFET; 21. a gate; 22. a drain electrode; 23. and a source electrode.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the embodiments of the present application, are within the scope of the claimed invention.
In the description of the embodiments of the present application, it should be noted that, directions or positional relationships indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., are based on directions or positional relationships shown in the drawings, are merely for convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific direction, be configured and operated in the specific direction, and thus should not be construed as limiting the embodiments of the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the embodiments of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, interchangeably connected, integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected through an intermediary, or in communication between two elements. The specific meaning of the terms in the embodiments of the present application will be understood by those of ordinary skill in the art in a specific context.
The embodiment of the application provides an internal insulation TO packaging structure for a gallium nitride field effect transistor. Referring to fig. 1 to 4, fig. 1 is a schematic diagram illustrating a connection mode of bottom gate GaN and a vertical channel MOSFET; FIG. 2 is a schematic diagram of a bottom gate GaN and LDMOS connection; FIG. 3 is a schematic diagram of the connection of top gate GaN to a vertical channel MOSFET; fig. 4 is a schematic diagram of a connection between the top gate GaN and the LDMOS.
The package structure comprises: the semiconductor device comprises a heat dissipation base plate 10, a ceramic substrate 11, a gallium nitride transistor 12, a MOSFET13, a gate 21, a drain 22, a source 23 and a plurality of pins.
The heat sink base 10 is electrically isolated from each pin. Wherein, the heat dissipation base plate 10 and the pins are part of a lead frame in the TO package structure.
The ceramic substrate 11 is disposed on the heat dissipation base plate 10 and is electrically insulated from the heat dissipation base plate 10. Gallium nitride transistor 12 and MOSFET13 are disposed on ceramic substrate 11. Wherein the ceramic substrate 11 is DPC substrate in fig. 1 to 4; the gallium nitride transistor 12 is a gallium nitride heterojunction field effect transistor, that is, a GaN HEMT chip. The MOSFET13 is a metal-oxide semiconductor field effect transistor; in application, the MOSFET13 may be a silicon-based MOSFET or a silicon carbide-based MOSFET, and in this embodiment, the MOSFET13 is a silicon-based MOSFET, i.e., a Si MOSFET chip in the figure.
In this embodiment, the GaN fet may be a tandem GaN fet, which is composed of a GaN HEMT and a MOSFET. The ceramic substrate 11, the gallium nitride transistor 12, and the MOSFET13 are electrically connected to each other.
The grid electrode 21, the drain electrode 22 and the source electrode 23 are respectively and electrically connected with the pins in a one-to-one correspondence manner; the gate 21 is electrically connected to the MOSFET13; drain 22 is electrically connected to gallium nitride transistor 12; the source electrode 23 is electrically connected to the ceramic substrate 11.
Specifically, in the conventional package structure of the gan field effect transistor, a source electrode is generally soldered to a bottom plate of a package lead frame by wire bonding, and is connected to an external circuit through an intermediate lead. The gate and the source are connected to corresponding lead locations on the leadframe by metal bonding.
In this embodiment, the heat dissipation base plate 10 is electrically insulated from the pins and the ceramic substrate 11, that is, the heat dissipation base plate 10 is not electrically connected with the inside of the package structure, so that no additional insulating parts such as insulating sheets or insulating particles are required to be arranged in the package structure, the material cost and labor cost of insulating gaskets and insulating particles can be saved, the problem that the withstand voltage test caused by the installation error of the insulating gaskets is not passed is avoided, and the safety of the power supply system is improved. Compared with the existing full-plastic package gallium nitride field effect transistor, the structure has lower thermal resistance and better heat dissipation performance, and simultaneously solves the problem that the pin function of the traditional full-plastic package gallium nitride field effect transistor is incompatible with a silicon-based or silicon carbide MOSFET.
It should be noted that the package structure of the present embodiment may be applied TO improve existing TO-220 and TO-247, and may also be applied TO all other TO with mounting holes for mounting a heat sink by screws. In addition, in the packaging structure provided by the scheme, pin pins can be arranged at will, and are compatible with the package of the existing 3-Pin TO-220 or TO-247 plug-in units of silicon-based or silicon carbide MOSFET (the functional positions of the pins are consistent except for the heat dissipation bottom plate).
In a more specific embodiment, the ceramic substrate 11 is provided with copper plated areas thereon; the gallium nitride transistor 12 and the MOSFET13 are disposed on the copper-plated region of the ceramic substrate 11, and the gallium nitride transistor 12 and the MOSFET13 are electrically connected through the connection member 30.
That is, in this embodiment, the ceramic substrate 11 is a copper-plated ceramic substrate, and the copper-plated region of the surface thereof is used for electrical connection with the gallium nitride transistor 12 and the MOSFET 13.
As a further improvement, in order to improve the electrical connection effect of both the gallium nitride transistor 12 and the MOSFET13 and the ceramic substrate 11, the gallium nitride transistor 12 and the MOSFET13 may be both soldered to the copper-plated region of the ceramic substrate 11 by silver paste or soft solder.
In another embodiment, gate 21 is electrically connected to MOSFET13 through connection 30; drain 22 is electrically connected to gallium nitride transistor 12 by connection 30; the source electrode 23 is electrically connected to the ceramic substrate 11 through the connection member 30.
The connecting piece 30 may be a metal wire, such as a copper wire, a silver wire or an alloy wire, or may be a copper clip.
Further, in the present embodiment, the gate 21, the drain 22 and the source 23 are all electrically connected to the leads by wire bonding.
Specifically, the gate electrode 21 and the drain electrode 22 may be connected to leads of the lead frame through a metal pad on top of the package structure and by wire bonding. The source electrode 23 may be wire-bonded to the lead through the ceramic substrate 11.
In practical application, the internal insulation TO packaging structure for the gallium nitride field effect transistor only needs TO be electrically insulated from the heat dissipation bottom plate 10 and is provided with the lead frame shown in fig. 2, and the ceramic substrate 11 is applied, so that the packaging process flow of the subsequent chip can be consistent with the traditional mode without adjusting the process flow, and the internal insulation TO packaging structure not only ensures the heat dissipation effect, but also has higher safety and good compatibility and also has good economic benefit.
While the present invention has been described in detail with reference to the examples, it will be apparent to those skilled in the art that the foregoing examples can be modified or equivalents substituted for some of the features thereof, and any modifications, equivalents, improvements and substitutions made therein are intended to be within the spirit and principles of the present invention.
Claims (7)
1. An internal insulating TO package structure for a gallium nitride field effect transistor, comprising: a heat dissipation base plate (10), a ceramic substrate (11), a gallium nitride transistor (12), a MOSFET (13), a grid electrode (21), a drain electrode (22), a source electrode (23) and a plurality of pins;
the heat dissipation base plate (10) is electrically insulated from each pin;
the ceramic substrate (11) is arranged on the heat dissipation base plate (10) and is electrically insulated from the heat dissipation base plate (10);
the gallium nitride transistor (12) and the MOSFET (13) are arranged on the ceramic substrate (11);
the ceramic substrate (11), the gallium nitride transistor (12) and the MOSFET (13) are mutually and electrically connected;
the grid electrode (21), the drain electrode (22) and the source electrode (23) are respectively and electrically connected with the pins in a one-to-one correspondence manner;
the grid electrode (21) is electrically connected with the MOSFET (13);
-said drain (22) is electrically connected to said gallium nitride transistor (12);
the source electrode (23) is electrically connected to the ceramic substrate (11).
2. The internal insulation TO package structure for gallium nitride field effect transistor according TO claim 1, wherein the ceramic substrate (11) is provided with copper plated areas;
the gallium nitride transistor (12) and the MOSFET (13) are arranged on the copper plating area of the ceramic substrate (11), and the gallium nitride transistor (12) and the MOSFET (13) are electrically connected through a connecting piece (30).
3. The internal insulating TO package structure for gan field effect transistors of claim 2, wherein said gan transistor (12) and MOSFET (13) are bonded TO said copper plated area of said ceramic substrate (11) by silver paste or soft solder.
4. The internal insulation TO package structure for gallium nitride field effect transistors according TO claim 1, wherein the gate (21) is electrically connected TO the MOSFET (13) by a connection (30);
the drain electrode (22) is electrically connected to the gallium nitride transistor (12) through a connection (30);
the source electrode (23) is electrically connected to the ceramic substrate (11) through a connector (30).
5. The internal insulation TO package structure for gallium nitride field effect transistors according TO any one of claims 2 TO 4, wherein the connection (30) is a metal wire.
6. The internal insulating TO package structure for gan field effect transistors of claim 1, wherein the gate (21), drain (22) and source (23) are all electrically connected TO the leads by wire bonding.
7. The internal insulation TO package structure for gallium nitride field effect transistors according TO claim 1, wherein the MOSFET (13) is a silicon-based MOSFET or a silicon carbide-based MOSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310203447.8A CN115995427A (en) | 2023-03-03 | 2023-03-03 | Internal insulation TO packaging structure for gallium nitride field effect transistor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310203447.8A CN115995427A (en) | 2023-03-03 | 2023-03-03 | Internal insulation TO packaging structure for gallium nitride field effect transistor |
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| CN115995427A true CN115995427A (en) | 2023-04-21 |
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| CN202310203447.8A Pending CN115995427A (en) | 2023-03-03 | 2023-03-03 | Internal insulation TO packaging structure for gallium nitride field effect transistor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116646256A (en) * | 2023-05-26 | 2023-08-25 | 苏州量芯微半导体有限公司 | Processing method before packaging gallium nitride power device and packaging structure |
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- 2023-03-03 CN CN202310203447.8A patent/CN115995427A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116646256A (en) * | 2023-05-26 | 2023-08-25 | 苏州量芯微半导体有限公司 | Processing method before packaging gallium nitride power device and packaging structure |
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