CN211696673U - Photodiode array assembly convenient to maintain - Google Patents
Photodiode array assembly convenient to maintain Download PDFInfo
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- CN211696673U CN211696673U CN202020412055.4U CN202020412055U CN211696673U CN 211696673 U CN211696673 U CN 211696673U CN 202020412055 U CN202020412055 U CN 202020412055U CN 211696673 U CN211696673 U CN 211696673U
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- photodiode
- operational amplifier
- resistor
- input end
- inverting input
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Abstract
The utility model relates to a photodiode technical field discloses a little and be convenient for photodiode array subassembly of maintenance of dark current error, possesses: at least one photodiode for detecting a signal intensity of the light; the non-inverting input end of the operational amplifier is coupled with the cathode of one photodiode, and the inverting input end of the operational amplifier is connected with the cathode of the other photodiode; the non-inverting input end of the differential amplifier is connected with the signal output end of the operational amplifier, and the inverting input end of the differential amplifier is connected with the common end; when the photodiode is conducted, the input offset voltage is processed by the operational amplifier and then output to the differential amplifier for gain; and when the photodiode is cut off, the photodiode connected with the non-inverting input end of the operational amplifier eliminates dark current errors.
Description
Technical Field
The utility model relates to a photodiode technical field, more specifically say, relate to a photodiode array subassembly convenient to maintenance.
Background
Photodiodes are relatively common devices in the field of electrical signals as optical signals. In the past, photodiodes have a small amount of current (referred to as dark current) under reverse bias conditions, and they flow even in the absence of illuminance, resulting in large dark current errors of the circuit.
Therefore, how to reduce the dark current error of the photodiode under the reverse bias state becomes a technical problem that needs to be solved by those skilled in the art.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model lies in, to the above-mentioned big defect of dark current error under the reverse bias state of prior art, provide a photodiode array subassembly that dark current error is little and be convenient for maintain.
The utility model provides a technical scheme that its technical problem adopted is: a photodiode array module which is easy to maintain is constructed, and the photodiode array module is provided with:
at least one photodiode for detecting a signal intensity of the light;
the non-inverting input end of the operational amplifier is coupled with the cathode of one photodiode, and the inverting input end of the operational amplifier is connected with the cathode of the other photodiode;
the non-inverting input end of the differential amplifier is connected with the signal output end of the operational amplifier, and the inverting input end of the differential amplifier is connected with the common end;
when the photodiode is conducted, the input offset voltage is processed by the operational amplifier and then output to the differential amplifier for gain;
and when the photodiode is cut off, the photodiode connected with the non-inverting input end of the operational amplifier eliminates dark current errors.
In some embodiments, the differential amplifier further comprises an analog-to-digital converter, a positive input of the analog-to-digital converter is coupled to the output of the differential amplifier,
the negative input end of the analog-to-digital converter is coupled to the negative output end of the differential amplifier.
In some embodiments, the device further comprises a first resistor and a first capacitor,
the first resistor and the first capacitor are connected in parallel,
one end of the first resistor and one end of the first capacitor are respectively connected with the non-inverting input end of the operational amplifier.
In some embodiments, the device further comprises a second resistor and a second capacitor, the second resistor and the second capacitor are connected in parallel,
one end of the second resistor and one end of the second capacitor are respectively connected with the inverting input end of the operational amplifier,
the other ends of the second resistor and the second capacitor are respectively connected with the output end of the operational amplifier.
In some embodiments, the circuit further comprises a third resistor and a fourth resistor, the third resistor is arranged between the output end of the operational amplifier and the non-inverting input end of the differential amplifier,
one end of the fourth resistor is coupled to the inverting input end of the differential amplifier.
In some embodiments, the digital signal processor further comprises a fourth capacitor, and the fourth capacitor is disposed between the positive input end and the negative input end of the analog-to-digital converter.
The photodiode array assembly convenient to maintain of the utility model comprises at least one photodiode, an operational amplifier and a differential amplifier, wherein the inverting input end of the differential amplifier is connected with a public end; when the photodiode is conducted, the input offset voltage is processed by the operational amplifier and then output to the differential amplifier for gain; when the photodiode is cut off, the photodiode connected with the non-inverting input end of the operational amplifier eliminates dark current errors. Compared with the prior art, the photodiode has a small amount of current under the reverse bias condition, even the photodiode can flow under the condition of no illuminance, and a second photodiode of the same type can be arranged at the non-inverting input end of the operational amplifier to eliminate dark current errors.
Drawings
The invention will be further explained with reference to the drawings and examples, wherein:
fig. 1 is a partial circuit diagram of an embodiment of a photodiode array assembly for easy maintenance.
Detailed Description
In order to clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a partial circuit diagram of an embodiment of a photodiode array assembly for easy maintenance. As shown in fig. 1, in the first embodiment of the photodiode array module for easy maintenance of the present invention, the photodiode array module for easy maintenance mainly includes at least one photodiode (SFH1, SFH2), an operational amplifier a1, a differential amplifier a2, and an analog-to-digital converter A3.
Specifically, the photodiode photodiodes (SFH1, SFH2) have a dark current compensation function. Among them, the photodiodes (SFH1, SFH2) convert the current from the peripheral circuit input and drive the input of the analog-to-digital converter A3. The circuit can provide spectral sensitivity of 300nm to 900nm and photocurrent sensitivity of 35nA, dynamic range of 90dB and bandwidth of 2-5 MHz. The photodiode array component adopts a +/-5V power supply to supply power, the power consumption is only 30mA, and the photodiode array component is suitable for being applied to portable and high-resolution light intensity occasions.
The photodiodes (SFH1, SFH2) are used to detect the signal intensity of light. Wherein, when the photodiode (SFH1, SFH2) works, a zero bias mode or a reverse bias mode is adopted. The most accurate linear operation can be obtained in the photovoltaic mode, and higher switching speeds can be realized by operating the photodiodes (SFH1, SFH2) in the photoconductive mode.
Specifically, the photodiodes are a first photodiode SFH1 and a second photodiode SFH2, wherein the anode of the first photodiode SFH1 is connected to the anode of the second photodiode SFH2, the cathode of the first photodiode SFH1 is connected to the inverting input terminal of the operational amplifier a1, and the cathode of the second photodiode SFH2 is connected to the non-inverting input terminal of the operational amplifier a 1.
When the photodiodes (SFH1, SFH2) are in the photovoltaic mode, the offset voltage (i.e., VBIAS) input by the peripheral circuit is output to the operational amplifier a1 through the photodiodes (SFH1, SFH 2).
The operational amplifier a1 includes an electronic integrated circuit having a multistage amplification circuit, the input stage of which is a differential amplification circuit, and has high input resistance and zero drift suppression capability.
Specifically, the non-inverting input terminal of the operational amplifier a1 is connected to the cathode of the second photodiode SFH2, and the inverting input terminal of the operational amplifier a1 is connected to the cathode of the first photodiode SFH 1.
The input offset Voltage (VBIAS) is separated by the photodiode (SFH1, SFH2) and then input into the non-inverting terminal and inverting terminal of the operational amplifier a1, and then output to the differential amplifier a2 after being processed by the operational amplifier a 1.
The differential amplifier a2 may amplify the difference between the voltages at the two inputs with a fixed gain.
Specifically, the non-inverting input terminal of the differential amplifier a2 is connected to the signal output terminal of the operational amplifier a1, and the inverting input terminal of the differential amplifier a2 is connected to the common terminal via the third capacitor C3.
The third capacitor C3 is used to reduce impedance and noise, so as to improve the operation stability of the differential amplifier a 2.
When the photodiodes (SFH1, SFH2) are in the on state, the offset voltage (i.e. V) inputted from the peripheral circuitBIAS) Processed by an operational amplifier A1, and then output to a differential amplifier A2 for offset voltage (i.e., V)BIAS) Gain is performed to improve the response speed of the circuit.
When the photodiodes (SFH1, SFH2) are in the off state, the dark current generated by the second photodiode SFH2 is eliminated by the first photodiode SFH1 disposed at the non-inverting input terminal of the operational amplifier a1, so as to reduce the current error and improve the accuracy of the signal processing by the circuit.
In some embodiments, to improve the performance of the circuit, an analog-to-digital converter A3 may be provided in the circuit, where the analog-to-digital converter A3 is used to convert the input analog signal into a digital signal.
The A/D converter A3 has a positive input terminal (VIN +), a negative input terminal (VIN +), and a power input terminal (AVDD).
Specifically, the positive input terminal (VIN +) of the A3 is coupled to the positive output terminal (+ OUT) of the a2, and the negative input terminal (VIN +) of the A3 is connected to the negative output terminal (-OUT) of the a 2.
That is, the input analog signal is processed by the differential amplifier a2, and then is output to the positive input terminal (VIN +) and the negative input terminal (VIN +) of the analog-to-digital converter A3, respectively, and the analog signal is converted into a digital signal, so that the circuit can meet the application that requires higher bandwidth and lower resolution.
In some embodiments, in order to improve the quality of the input signal, a first resistor R1 and a first capacitor C1 may be disposed in the circuit. The first resistor R1 and the first capacitor C1 are connected in parallel, and have the functions of attenuating high-frequency signals and filtering.
One end of the first resistor R1 and one end of the first capacitor C1 are connected to the non-inverting input terminal of the operational amplifier a1, and the other end of the first resistor R1 and the other end of the first capacitor C1 are connected to the common terminal. That is, after the input offset Voltage (VBIAS) is processed by the first resistor R1 and the first capacitor C1, impurities carried by the input offset Voltage (VBIAS) can be reduced, and thus the signal quality of the input operational amplifier a1 can be effectively improved.
In some embodiments, the circuit further includes a second resistor R2 and a second capacitor C2, wherein the second resistor R2 and the second capacitor C2 are feedback circuits.
Specifically, the second resistor R2 and the second capacitor C2 are connected in parallel to form a feedback circuit of the inverting input terminal of the operational amplifier a 1.
One end of the second resistor R2 and one end of the second capacitor C2 are connected to the inverting input terminal of the operational amplifier a1, and the other end of the second resistor R2 and the other end of the second capacitor C2 are connected to the output terminal of the operational amplifier a 1.
That is, part or all of the signal output by the operational amplifier a1 passes through the second resistor R2 and the second capacitor C2, and then is fed back to the inverting input terminal of the operational amplifier a1, so as to increase the intensity of the input signal.
In some embodiments, a third resistor R3 and a fourth resistor R4 are also included. Specifically, the third resistor R3 is disposed between the output terminal of the operational amplifier a1 and the non-inverting input terminal of the differential amplifier a 2. One end of the fourth resistor R4 is coupled to the inverting input terminal of the differential amplifier a 2.
Offset voltage (i.e., V) from the output of operational amplifier A1BIAS) After being attenuated by the third resistor R3, the signal is output to the non-inverting terminal of the differential amplifier A2.
In some embodiments, in order to improve the signal quality of the input adc a3, a seventh resistor R7, an eighth resistor R8 and a fourth capacitor C4 may be disposed in the circuit, wherein the fourth capacitor C4 has a filtering function.
Specifically, the positive input terminal (VIN +) of the analog-to-digital converter A3 is connected to the positive output terminal (+ OUT) of the differential amplifier a2 through the eighth resistor R8, and the negative input terminal (VIN-) of the analog-to-digital converter A3 is connected to the negative output terminal (-OUT) of the differential amplifier a2 through the seventh resistor R7.
The fourth capacitor C4 is disposed between the positive input terminal (VIN +) and the negative input terminal (VIN-) of the adc A3.
The input analog signals are attenuated by the seventh resistor R7 and the eighth resistor R8 and filtered by the fourth capacitor C4, and then are input to the analog-to-digital converter A3, respectively, and the analog-to-digital converter A3 converts the input analog signals.
In some embodiments, the circuit is further provided with a power converter a4, wherein a power input terminal of the power converter a4 is connected to +5V voltage, and is converted into +2.5V voltage output after being processed by the power converter a4, so as to meet the requirement of the circuit for voltages of various stages.
While the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many modifications may be made by one skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (6)
1. A photodiode array module convenient to maintain is characterized by comprising:
at least one photodiode for detecting a signal intensity of the light;
the non-inverting input end of the operational amplifier is coupled with the cathode of one photodiode, and the inverting input end of the operational amplifier is connected with the cathode of the other photodiode;
the non-inverting input end of the differential amplifier is connected with the signal output end of the operational amplifier, and the inverting input end of the differential amplifier is connected with the common end;
when the photodiode is conducted, the input offset voltage is processed by the operational amplifier and then output to the differential amplifier for gain;
and when the photodiode is cut off, the photodiode connected with the non-inverting input end of the operational amplifier eliminates dark current errors.
2. The photodiode array assembly of claim 1, wherein the photodiode array assembly further comprises a plurality of photodiodes,
the differential amplifier further comprises an analog-to-digital converter, a positive input end of the analog-to-digital converter is coupled to the output end of the differential amplifier,
the negative input end of the analog-to-digital converter is coupled to the negative output end of the differential amplifier.
3. The photodiode array assembly of claim 1, wherein the photodiode array assembly further comprises a plurality of photodiodes,
also includes a first resistor and a first capacitor,
the first resistor and the first capacitor are connected in parallel,
one end of the first resistor and one end of the first capacitor are respectively connected with the non-inverting input end of the operational amplifier.
4. The photodiode array assembly of claim 1, wherein the photodiode array assembly further comprises a plurality of photodiodes,
also comprises a second resistor and a second capacitor which are connected in parallel,
one end of the second resistor and one end of the second capacitor are respectively connected with the inverting input end of the operational amplifier,
the other ends of the second resistor and the second capacitor are respectively connected with the output end of the operational amplifier.
5. The photodiode array assembly of claim 1, wherein the photodiode array assembly further comprises a plurality of photodiodes,
the differential amplifier further comprises a third resistor and a fourth resistor, the third resistor is arranged between the output end of the operational amplifier and the non-inverting input end of the differential amplifier,
one end of the fourth resistor is coupled to the inverting input end of the differential amplifier.
6. The photodiode array assembly of claim 2, wherein the photodiode array assembly further comprises a plurality of photodiodes,
the analog-to-digital converter further comprises a fourth capacitor, and the fourth capacitor is arranged between the positive input end and the negative input end of the analog-to-digital converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020412055.4U CN211696673U (en) | 2020-03-27 | 2020-03-27 | Photodiode array assembly convenient to maintain |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020412055.4U CN211696673U (en) | 2020-03-27 | 2020-03-27 | Photodiode array assembly convenient to maintain |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211696673U true CN211696673U (en) | 2020-10-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020412055.4U Expired - Fee Related CN211696673U (en) | 2020-03-27 | 2020-03-27 | Photodiode array assembly convenient to maintain |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211696673U (en) |
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2020
- 2020-03-27 CN CN202020412055.4U patent/CN211696673U/en not_active Expired - Fee Related
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| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20201016 Termination date: 20210327 |
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| CF01 | Termination of patent right due to non-payment of annual fee |