CN211628040U

CN211628040U - Analog quantity output module with HART protocol conversion and DCS system

Info

Publication number: CN211628040U
Application number: CN201922400201.1U
Authority: CN
Inventors: 傅晨晔; 蒋杰; 王维建
Original assignee: SHANGHAI XINHUA CONTROL TECHNOLOGY (GROUP) CO LTD
Current assignee: SHANGHAI XINHUA CONTROL TECHNOLOGY (GROUP) CO LTD
Priority date: 2019-12-27
Filing date: 2019-12-27
Publication date: 2020-10-02
Anticipated expiration: 2029-12-27

Abstract

The utility model discloses an aspect discloses an analog output module with HART protocol conversion, which relates to the field of analog output, and comprises a power module, a control chip module, a signal isolation module, an indicator light module, a HART protocol module, a multi-way switch switching module and an output driving module, wherein the control chip module is respectively in communication connection with the output driving module, the multi-way switch switching module and the HART protocol module through the signal isolation module; the control chip module lights the indicator light module through serial-parallel signals; the power module supplies power to the output circuit. The analog quantity output module designed by the utility model realizes switching the HART protocol on the channel without disturbance; in a second aspect, the present invention also discloses a DCS system with an analog output module for HART protocol conversion.

Description

Analog quantity output module with HART protocol conversion and DCS system

Technical Field

The utility model relates to an analog output field especially relates to an analog output module with HART protocol conversion.

Background

At present, Distributed Control Systems (DCS) have been widely used in the field of automation Control of power, petroleum, chemical industry, steel, paper making, cement, desulfurization, dust removal, water treatment, etc., and the Distributed Control Systems are a multi-level Computer system composed of a process Control level and a process monitoring level and using a Communication network as a link, and integrate 4C technologies such as computers (computers), Communication (Communication), display (CRT) and Control (Control), and the basic idea is Distributed Control, centralized operation, hierarchical management, flexible configuration and convenient configuration. Xinhua DCS system NetPAC is a new generation of the new DCS system.

The HART (Highway Addressable Remote transmitter) protocol, an open communication protocol for Highway Addressable Remote sensors, was introduced in 1985 by rosemont corporation of america for communication between field intelligent instruments and control room equipment. The HART protocol has become the industry standard for global smart meters at present.

In the prior art, an analog quantity output module in the DCS system is only responsible for outputting 4-20mA analog quantity signals, and does not unpack the HART protocol, but uses a special independent HART module for HART information transmission.

Therefore, those skilled in the art have devoted themselves to develop an analog output module with HART protocol conversion, which can switch the HART protocol over the channel without disturbance.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned defects in the prior art, the technical problem to be solved in the present invention is how to switch the HART protocol on the channel without disturbance by the analog output module of the DCS system to meet the needs of the industrial field.

In order to achieve the above object, the present invention provides an analog output module with HART protocol conversion. The system comprises a power supply module, a control chip module, a signal isolation module, an indicator lamp module, a HART protocol module, a multi-way switch switching module and an output driving module, wherein the control chip module is respectively in communication connection with the output driving module, the multi-way switch switching module and the HART protocol module through the signal isolation module; the control chip module lights the indicator light module through serial-parallel signals; the power supply module supplies power to the output circuit; the control chip module is used for communication and signal processing of an upper computer; the signal isolation module isolates an output signal from the control chip module; the indicator light module is used for indicating signal output; the HART protocol module analyzes and converts a HART protocol; the multi-way switch switching module is used for back correction and digital-to-analog conversion of output signals.

Further, the output driving module outputs a current signal of 4-20 mA.

Optionally, the control chip module communicates with the HART protocol module through a serial bus via the signal isolation module.

Optionally, the control chip module transmits data to the output driving module through the SPI serial bus and through the signal isolation module.

Optionally, the control chip module controls the multi-channel switch module to switch different channels after passing through the signal isolation module through a parallel bus.

Optionally, the power module adopts a DC/DC power module

Further, the DC/DC power supply module converts the 24V power supply into +/-15V.

Optionally, the output driver module comprises a back calibration, a digital-to-analog converter (DAC) and a current output circuit.

Optionally, the digital-to-analog converter (DAC) is an 8-channel 12-bit conversion chip.

Optionally, the digital-to-analog converter (DAC) configures an internal reference, and outputs analog quantity signals of 8 channels at the same time.

Optionally, the control chip module includes a CPLD and a CPU, and the CPLD and the CPU are interconnected through a bus.

Furthermore, the CPU adopts a high-speed magnetic medium isolation chip, so that the interference of field equipment on the CPU can be isolated.

Optionally, the CPU employs a 32-bit ARM M0 chip.

Further, the CPLD communicates with an upper computer to obtain analog quantity data required to be output, and the analog quantity data is sent to a digital-to-analog converter (DAC) through an isolated SPI bus.

Furthermore, the CPLD controls the switching of the multi-way switch and exchanges data with the CPU.

Optionally, the CPLD is provided with two communication interfaces for data exchange with the upper computer, so as to implement redundancy in communication with the upper computer.

Furthermore, the control chip module further comprises a storage unit, a watchdog unit and a configuration port which are connected with the CPU through a bus.

Furthermore, the HART protocol module is configured with a HART protocol decoding chip, and superimposes a HART signal of 1.2kHz on the analog quantity signal of 4-20mA to complete the HART protocol communication.

Optionally, the decoding chip of the HART protocol employs a5191HRT type HART modem.

Optionally, the decoding chip of the HART protocol configures a serial port to communicate with the CPU.

Further, the multi-way switch switching module switches channels in a polling master-slave mode, and switches the signal polling of the HART protocol module to each channel.

Optionally, the multi-way switch switching module employs a multi-way switch of the MUX 508.

Further, the output driving module is provided with 16 channels which are respectively arranged on the two board cards, and each board card is provided with 8 channels.

The utility model discloses still including the DCS system that has used any one of above-mentioned embodiments.

The utility model discloses an analog output module switches through the multi-way switch, can switch the HART agreement on the passageway without disturbance, has satisfied industrial field's needs.

The conception, the specific structure and the technical effects of the present invention will be further described with reference to the accompanying drawings, so as to fully understand the objects, the features and the effects of the present invention.

Drawings

FIG. 1 is a schematic diagram of the components of a preferred embodiment of the present invention;

fig. 2 is a schematic diagram of the application of the present invention in DCS.

Detailed Description

The technical contents of the preferred embodiments of the present invention will be more clearly understood and appreciated by referring to the drawings attached to the specification. The present invention may be embodied in many different forms of embodiments, and the scope of the invention is not limited to the embodiments described herein.

In the drawings, structurally identical elements are represented by like reference numerals, and structurally or functionally similar elements are represented by like reference numerals throughout the several views. The size and thickness of each component shown in the drawings are arbitrarily illustrated, and the present invention is not limited to the size and thickness of each component. The thickness of the components may be exaggerated where appropriate in the figures to improve clarity.

The utility model discloses a preferred embodiment includes power module, control chip module, signal isolation module, pilot lamp module, HART protocol module, multi-way switch switching module and output drive module. The control chip module transmits data to the output driving module through the SPI serial bus and the signal isolation module, the output driving module comprises a digital-to-analog converter (DAC), required current signals are output to the external terminal module after data conversion, the current signals flow back to form a current loop after being supplied to field equipment through an external terminal, the flowing-back current signals enter the HART protocol module to carry out HART protocol conversion, and are input to the control chip module after signal isolation through the SPI serial port. Because signals of a plurality of channels need to be collected, the control chip also needs to control the multi-channel switch switching module to switch different channels after being isolated by the signal isolation module through the parallel bus. The indicator light module and the control chip module are lightened by serial-parallel signals.

The power supply module is designed to be of a DC/DC type, and converts a 24V power supply into +/-15V power to supply power to the output circuit.

The control chip module is used for upper computer communication and signal processing, and comprises a CPLD and a CPU which are interconnected through a bus and are communicated; in order to isolate electromagnetic interference of field devices, the inventor adopts a high-speed magnetic medium isolation chip, specifically uses a 32-bit ARM M0 chip, and can use C language for programming; the CPLD communicates with an upper computer to obtain analog quantity data needing to be output, the analog quantity data is sent to a digital-to-analog converter (DAC) through an isolated SPI bus, the inventor selects the type of the digital-to-analog converter (DAC), selects an 8-channel 12-bit conversion chip, has an internal reference and simultaneously outputs analog quantity signals of 8 channels, and two pieces of DACs 7568 are used in the embodiment; the CPLD controls switching of the multiplexer, and exchanges data with the CPU. For the sake of safety, the CPLD is provided with two communication interfaces for data exchange with the upper computer, so that the redundancy of communication with the upper computer is realized. The inventor selects a CPLD, and the LCMXXO 2-2000 chip in MachXO2 series of LATTICE company is adopted in the embodiment.

In consideration of functional integrity and data storage, the inventor also configures a storage unit, a watchdog unit and a configuration port in the control chip module, and the storage unit, the watchdog unit and the configuration port are connected with the CPU through a bus. In the present embodiment, the memory cell selects the EEPROM.

The inventor designs a HART protocol module and analyzes the HART protocol. Setting a HART protocol decoding chip, and superposing a 1.2kHz HART signal to a 4-20mA analog quantity signal to complete HART protocol communication; the decoding chip adopts an A5191HRT type HART modem, and is configured with a serial port to communicate with the CPU. And the HART protocol module communicates with the control chip module through a serial port bus.

The inventor uses a signal isolation module to isolate an output signal from the control chip module.

The inventor designs an indicator lamp module for indicating signal output, each output channel is provided with a unique corresponding indicator lamp for describing the broken line or the overrun state of the channel, and the indicator lamp is on to represent that the current channel is broken line or exceeds a rated voltage range.

The inventor designs a multi-way switch switching module for the back calibration of output signals and the switching of HART protocol. The multiple switch switching module switches channels in a polling master-slave manner, and switches the signal polling of the HART protocol module to each channel, in this embodiment, a multiple switch of the MUX508 is used.

The inventor designs an output driving module which outputs a current signal of 4-20 mA; the output driving module comprises 16 channels which are respectively arranged on the two board cards, and each board card is provided with 8 channels.

In another preferred embodiment of the present invention, a DCS system is designed, as shown in fig. 2, including the analog output module with HART protocol conversion. This embodiment is illustrated as modules a1, a2, An; modules B1, B2 … … Bn; the modules N1, N2 … … Nn, and the like are installed in the DCS system.

The foregoing has described in detail preferred embodiments of the present invention. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the teachings of this invention without undue experimentation. Therefore, the technical solutions that can be obtained by a person skilled in the art through logic analysis, reasoning or limited experiments based on the prior art according to the concepts of the present invention should be within the scope of protection defined by the claims.

Claims

1. An analog quantity output module with HART protocol conversion is characterized by comprising a power supply module, a control chip module, a signal isolation module, an indicator light module, a HART protocol module, a multi-way switch switching module and an output driving module, wherein the control chip module is respectively in communication connection with the output driving module, the multi-way switch switching module and the HART protocol module through the signal isolation module; the control chip module lights the indicator light module through serial-parallel signals; the power supply module supplies power to the output circuit; the control chip module is used for communication and signal processing of an upper computer; the signal isolation module isolates an output signal from the control chip module; the indicator light module is used for indicating signal output; the HART protocol module analyzes and converts a HART protocol; the multi-way switch switching module is used for back correction and digital-to-analog conversion of output signals.

2. The analog output module with HART protocol conversion of claim 1, wherein the power module uses a DC/DC power module to convert 24V power to ± 15V.

3. The analog output module with HART protocol conversion of claim 1, wherein the control chip module comprises CPLD and CPU, and the CPLD and the CPU are interconnected through bus.

4. The analog output module with HART protocol conversion of claim 3, wherein the CPU is implemented as a high speed magnetic isolation chip.

5. The analog output module with HART protocol conversion of claim 1, wherein the output driver module comprises a calibration loop, a digital-to-analog converter and a current output circuit.

6. The analog output module with HART protocol conversion of claim 3, wherein the CPLD communicates with the upper computer to obtain the analog data to be outputted, and sends the analog data to the digital-to-analog converter through the isolated SPI bus.

7. The analog output module with HART protocol conversion of claim 6, wherein the digital-to-analog converter is an 8-channel 12-bit conversion chip.

8. The analog output module with HART protocol conversion of claim 7, wherein the digital-to-analog converter configures the internal reference and outputs the analog signals of 8 channels simultaneously.

9. The analog output module with HART protocol conversion of claim 3, wherein the control chip module further comprises a memory unit, a watchdog unit and a configuration port connected with the CPU through a bus.

10. A DCS system comprising the analog output module with HART protocol conversion according to any of claims 1 to 9.