CN211628021U - Time-to-digital conversion integrated circuit - Google Patents
Time-to-digital conversion integrated circuit Download PDFInfo
- Publication number
- CN211628021U CN211628021U CN202020247460.5U CN202020247460U CN211628021U CN 211628021 U CN211628021 U CN 211628021U CN 202020247460 U CN202020247460 U CN 202020247460U CN 211628021 U CN211628021 U CN 211628021U
- Authority
- CN
- China
- Prior art keywords
- time
- data
- pulse
- channel
- stop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Measurement Of Unknown Time Intervals (AREA)
Abstract
The application discloses time digital conversion integrated circuit, this integrated circuit includes control register and clock unit, still includes: the time-to-digital converter is used for carrying out edge time detection on the received starting pulse, the first channel stopping pulse and the second channel stopping pulse; the raw data memory is connected with the time-to-digital converter and is used for storing the time data detected by the time-to-digital converter; the arithmetic logic unit is connected with the original data memory and is used for automatically calculating a first group of interval duration data of the first channel stop pulse and the start pulse and a second group of interval duration data of the second channel stop pulse and the start pulse according to the time data; the data output register is connected with the arithmetic logic unit and used for storing the calculation result of the arithmetic logic unit; and the SPI interface is connected with the data output register and is used for externally connecting the MCU to read and write data. The method and the device can realize high communication efficiency and processing speed, and greatly improve the working performance.
Description
Technical Field
The present disclosure relates to circuit design technologies, and in particular, to a time-to-digital conversion integrated circuit.
Background
Laser radars are increasingly applied to ranging and automatic obstacle avoidance in the fields of automobile unmanned driving, automatic logistics trolleys, unmanned aerial vehicle cruising and the like; at present, three methods, namely a phase method, a trigonometry method and a time difference method are adopted for realizing the laser radar, the phase method has the defects of short distance, long time, low speed and the like, the trigonometry method has the defects of poor precision, complex realization structure and the like, and the method for realizing pulse time-to-digital conversion (belonging to the time difference method) for the laser radar with high precision and high speed is the best choice.
Pulsed time-to-digital conversion has also begun to be applied to laser ranging, such as the in-telescope laser ranging function. However, the existing pulse time-to-digital conversion circuit has limited processing capability and low speed and precision, especially in the outdoor severe environment application of laser ranging. In view of the above, it is an important need for those skilled in the art to provide a solution to the above technical problems.
SUMMERY OF THE UTILITY MODEL
The purpose of the present application is to provide a time-to-digital conversion integrated circuit, so as to effectively improve the performance in terms of time measurement range and measurement efficiency.
In order to solve the above technical problem, the present application discloses a time-to-digital conversion integrated circuit, which includes a control register and a clock unit, and is characterized by further including:
the time-to-digital converter is used for carrying out edge time detection on the received starting pulse, the first channel stopping pulse and the second channel stopping pulse;
the raw data memory is connected with the time-to-digital converter and is used for storing the time data detected by the time-to-digital converter;
the arithmetic logic unit is connected with the original data memory and is used for automatically calculating a first group of interval duration data of the first channel stop pulse and the starting pulse and a second group of interval duration data of the second channel stop pulse and the starting pulse according to the time data;
the data output register is connected with the arithmetic logic unit and is used for storing the calculation result of the arithmetic logic unit;
and the SPI interface is connected with the data output register and is used for externally connecting an MCU (microprogrammed control unit) to read and write data.
Optionally, the START pulse is a pulse received by the START terminal of the time-to-digital converter when the laser emitting circuit emits laser light;
the time-to-digital converter has two independent STOP channels for edge time detection; the first channel STOP pulse is a pulse received by the first STOP channel after the laser light is reflected and received, and the second channel STOP pulse is a pulse received by the second STOP channel after the laser light is reflected and received.
Optionally, the two STOP channels are specifically configured to capture the same set of pulses so as to operate in a single-channel double-precision mode;
alternatively, the two STOP channels are specifically configured to capture different sets of pulses, respectively, for operation in a dual channel single precision mode.
Optionally, the maximum number of pulses captured by each STOP channel of the time-to-digital converter in a single time duration is 10; the data output register has 22 groups of data storage capacity; so that the external MCU excludes data corresponding to the interference pulse from the multi-group data.
Optionally, the time-to-digital converter is further configured to detect a system clock period;
the arithmetic logic unit is further configured to calculate a calibration factor according to the system clock period detected by the time-to-digital converter, and perform calibration processing on the first set of interval duration data and the second set of interval duration data based on the calibration factor.
Optionally, the time-to-digital converter is specifically configured to detect time points corresponding to 0.5 system clock cycles and 1.5 system clock cycles, respectively;
the arithmetic logic unit is specifically configured to use the duration data of 1 system clock cycle obtained based on the difference calculation as the calibration factor, and use a ratio of the first group of interval duration data to the calibration factor and a ratio of the second group of interval duration data to the calibration factor as calibrated data.
Optionally, the arithmetic logic unit is further configured to:
and after the first group of interval duration data and the second group of interval duration data generated by calculation are output to the data output register, generating an interrupt signal and sending the interrupt signal to the external MCU so that the external MCU can read and write data conveniently.
The time-to-digital conversion integrated circuit provided by the application comprises a control register and a clock unit, and further comprises: the time-to-digital converter is used for carrying out edge time detection on the received starting pulse, the first channel stopping pulse and the second channel stopping pulse; the raw data memory is connected with the time-to-digital converter and is used for storing the time data detected by the time-to-digital converter; the arithmetic logic unit is connected with the original data memory and is used for automatically calculating a first group of interval duration data of the first channel stop pulse and the starting pulse and a second group of interval duration data of the second channel stop pulse and the starting pulse according to the time data; the data output register is connected with the arithmetic logic unit and is used for storing the calculation result of the arithmetic logic unit; and the SPI interface is connected with the data output register and is used for externally connecting an MCU (microprogrammed control Unit) to read data.
Therefore, the time-to-digital conversion integrated circuit provided by the application utilizes the integrated circuit with clear and efficient matching procedures of all parts, not only can realize a larger time detection range, but also can realize higher communication efficiency and processing speed, and greatly improves the working performance of the time-to-digital conversion integrated circuit. The time-to-digital conversion method provided by the application also has the beneficial effects.
Drawings
In order to more clearly illustrate the technical solutions in the prior art and the embodiments of the present application, the drawings that are needed to be used in the description of the prior art and the embodiments of the present application will be briefly described below. Of course, the following description of the drawings related to the embodiments of the present application is only a part of the embodiments of the present application, and it will be obvious to those skilled in the art that other drawings can be obtained from the provided drawings without any creative effort, and the obtained other drawings also belong to the protection scope of the present application.
Fig. 1 is a circuit structure diagram of a time-to-digital conversion integrated circuit according to an embodiment of the present disclosure.
Detailed Description
The core of the application is to provide a time-to-digital conversion integrated circuit so as to effectively improve the performance in the aspects of time measurement range, measurement efficiency and the like.
In order to more clearly and completely describe the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, an embodiment of the present application discloses a time-to-digital conversion integrated circuit, which includes a control register 101 and a clock unit 102; further comprising:
a time-to-digital converter 103 for performing edge time detection on the received start pulse, first channel stop pulse, and second channel stop pulse;
a raw data memory 104 connected to the time-to-digital converter 103 for storing the time data detected by the time-to-digital converter 103;
an arithmetic logic unit 105 connected to the raw data memory 104 for automatically calculating a first set of interval duration data of the first channel stop pulse and the start pulse and a second set of interval duration data of the second channel stop pulse and the start pulse based on the time data;
a data output register 106 connected to the arithmetic logic unit 105, for storing a calculation result of the arithmetic logic unit 105;
and the SPI interface 107 is connected with the data output register 106 and is used for externally connecting the MCU to read data.
The control register 101 is used for decoding and executing an operation command sent by the external MCU through the SPI 107, and the operation naming may include resetting, initializing, configuring a chip, measuring, reading measurement data, reading a circuit state value, and the like. The configuration chip commands can set other modules as required, including the number of pulses, edge selection for START and STOP, overflow time setting, interrupt selection, internal system clock division factor, whether to calibrate the measurement, etc.
The clock unit 102 is connected to the control register 101 for providing a base clock. This part generates a clock by an external crystal oscillator, and is switched and frequency-divided by the control register 101.
Specifically, the time-to-digital conversion integrated circuit provided in the embodiment of the present application specifically measures and calculates a first interval duration between a start pulse and a first channel stop pulse, and a second interval duration between the start pulse and a second channel stop pulse, so as to realize conversion from a time signal to a digital signal.
As a specific application, the time-to-digital conversion integrated circuit provided in the embodiment of the present application may be applied to pulse laser ranging, that is, a start pulse is used as a time mark for laser emission, a stop pulse is used as a time mark for laser reception, and an optical path may be calculated by combining an optical speed, so as to implement pulse laser ranging.
Thus, as a specific embodiment, the START terminal of the time-to-digital converter 103 is used to receive the pulse emitted by the marking laser, i.e., the START pulse, when the laser emitting circuit emits laser light. Also, the time-to-digital converter 103 has two independent STOP channels for edge time detection, the first channel STOP pulse being a pulse received by the first STOP channel (i.e., the STOP1 side) after the laser light is reflected and received, and the second channel STOP pulse being a pulse received by the second STOP channel (i.e., the STOP2 side) after the laser light is reflected and received.
Specifically, the laser emitting circuit emits laser to the target to be measured, the laser signal reflected from the target to be measured is detected and received by the laser receiving circuit, and then the signal is converted and amplified to generate a pulse, which is sent to the STOP channel of the time-to-digital converter 103 for detection.
It should be noted that each STOP channel of the time-to-digital converter 103 in this application has multiple pulse capture capability, so the first channel STOP pulse in this application can be a set of pulses, and the duration of the interval obtained thereby is a set of data. For example, if the first channel stop pulse is 10 pulses, 10 pieces of first interval duration data are correspondingly obtained to form a first group of interval duration data. The second channel stop pulse is similar and will not be described further herein.
In summary, in the present application, the time-to-digital converter 103 uses the STOP channel to perform edge time detection on the pulse; the raw data memory 104 is used for storing raw time data detected by the time-to-digital converter 103; the arithmetic logic unit 105 is configured to automatically calculate two sets of time duration data according to the three sets of time data: a first set of interval duration data of the start pulse and the first channel stop pulse, and a second set of interval duration data of the start pulse and the second channel stop pulse; the data output register 106 is used for storing calculation result data of the arithmetic logic unit 105; the SPI interface 107 is used for communicating with an external MCU, so that the external MCU can quickly acquire calculation result data for service calculation, for example, performing pulse laser ranging calculation.
In the circuit structure of the time-to-digital conversion integrated circuit provided by the application, each part of processes are clear, and the integrated circuit with high efficiency cooperation is formed. The time-to-digital converter 103 and other related devices have strong processing performance and storage performance, and the detectable interval duration is long, so that a large time detection range of 3.5ns-20us can be realized (the maximum distance corresponding to laser ranging is 3000 meters).
It should be further noted that the time-to-digital conversion integrated circuit provided by the present application is provided with the high-speed SPI interface 107, so that a communication frequency as high as 40mhz can be realized, and the communication efficiency and speed of the time-to-digital conversion integrated circuit are greatly improved. In addition, the arithmetic logic unit 105 in the present application can automatically calculate the time length after detecting that the original time data is written in the original data storage 104, without waiting for the instructions of other components such as an external MCU, thereby further effectively improving the working efficiency of the time-to-digital conversion integrated circuit.
Therefore, the time-to-digital conversion integrated circuit provided by the application utilizes the integrated circuit with clear and efficient matching procedures of all parts, not only can realize a larger time detection range, but also can realize higher communication efficiency and processing speed, and greatly improves the working performance of the time-to-digital conversion integrated circuit.
As a specific embodiment, the time-to-digital converter integrated circuit provided in the embodiment of the present application is based on the above, and the time-to-digital converter 103 can selectively operate in a single-channel double-precision mode or a double-channel single-precision mode based on two independent STOP channels.
In particular, two STOP channels may be used in particular to capture the same set of pulses in order to operate in a single-channel double-precision mode; in the mode, the two STOP channels are used for carrying out common-mode noise suppression averaging and other processing on the detection result of the same group of pulses, and the precision can be effectively improved. Alternatively, the two STOP channels may be specifically configured to capture different sets of pulses, respectively, for operation in a dual channel single precision mode.
Under a dual-channel single-precision mode, the precision of time-to-digital conversion can reach 46ps (corresponding to the laser ranging precision of 0.70 cm); and under the single-channel double-precision mode, the measurement precision of the method can reach 23ps (the corresponding laser ranging precision is 0.35 cm).
And, further, each STOP channel can selectively capture pulses in a "rising or falling edge" manner, or in a "rising and falling edge" manner.
As a specific embodiment, the time-to-digital conversion integrated circuit provided in the embodiment of the present application is based on the above, and the maximum number of pulses captured by each STOP channel of the time-to-digital converter 103 in a single time duration is 10; the data output register 106 has a storage capacity of 22 sets of data; so that the external MCU can eliminate the data corresponding to the interference pulse from the multi-group data.
In the single-channel double-precision mode, the application can receive 10 stop pulses at most. Specifically, the time-to-digital converter 103 may be specifically configured to capture time data of 10 pulses when performing edge time detection on the first channel stop pulse, so that the external MCU excludes data of interference pulses from the data, and obtains real time data of the first channel stop pulse.
In the dual-channel single-precision mode, the application can receive 20 STOP pulses at most.
Therefore, in the present embodiment, the number of pulses that can be captured by the time-to-digital converter 103 is large, and at most, 20 pulses can be measured, so that in the application of pulse laser ranging, it can be effectively avoided that the actual real target pulse is missed due to too many false reflection interference signals caused by a severe environment. Thus, the present embodiment can greatly improve the measurement accuracy of the time-to-digital converter 103 and the applicability in a severe environment.
As a specific embodiment, on the basis of the foregoing, the time-to-digital converter 103 is further configured to detect a system clock period;
the arithmetic logic unit 105 is further configured to calculate a calibration factor according to the system clock period detected by the time-to-digital converter 103, and perform calibration processing on the first set of interval duration data and the second set of interval duration data based on the calibration factor.
As a specific embodiment, on the basis of the above content, the time-to-digital converter 103 is specifically configured to detect time points corresponding to 0.5 system clock cycles and 1.5 system clock cycles respectively;
the arithmetic logic unit 105 is specifically configured to use the duration data of 1 system clock cycle obtained based on the difference calculation as the calibration factor, and use the ratio of the first group of interval duration data to the calibration factor and the ratio of the second group of interval duration data to the calibration factor as the calibrated data.
Specifically, in this embodiment, after the time data (START) of the START pulse is measured at the START end and the time data (STOP) of the STOP pulse is measured at the STOP end, the time digitizer 103 can perform high-precision measurement on 0.5 and 1.5 system clock cycles respectively to obtain the time data (CAL1) of 0.5 system clock and the time data (CAL2) of 1.5 system clock, and store the time data and the time data in the original data memory 104.
The arithmetic logic unit 105 performs a difference calculation based on CAL1 and CAL2 to generate calibration factors (CAL2 to CAL1), and further calculates (STOP-START)/(CAL2 to CAL1) as calibration data, and outputs the calibration data to the data output register 106.
The data output register 106 has a storage capacity of 22 groups of data for storing the related data corresponding to 20 STOP pulses, including STOP-START or (STOP-START)/(CAL2-CAL1) corresponding to each STOP pulse, i.e. the interval duration data before or after calibration; in addition to the 20 sets of data, calibration factors CAL2-CAL1 may be stored; in addition, status data may also be stored as a status register.
It should be noted that the time-to-digital conversion integrated circuit provided by the present application has a calibration function, and thus can selectively perform a calibration output and a non-calibration output. When output in non-calibrated form, arithmetic logic unit 105 can be used to calculate only the pre-calibration data, STOP-START, and store it into data output register 106.
When outputting in calibration form, the arithmetic logic unit 105 may obtain the calibration factors CAL2-CAL1, calculate the calibrated data (STOP-START)/(CAL2-CAL1), and store it in the data output register 106; alternatively, more preferably, the calibration factors CAL2-CAL1 do not have to be acquired frequently in view of the stability of the external clock, and therefore, the arithmetic logic unit 105 may store only the pre-calibration data, STOP-START, into the data output register 106, and the external MCU calculates (STOP-START)/(CAL2-CAL1) from the calibration factors CAL2-CAL1 previously read from the data output register 106.
As an embodiment, in the time-to-digital conversion integrated circuit provided in the embodiment of the present application, on the basis of the foregoing, the arithmetic logic unit 105 is further configured to:
after the first group of interval duration data and the second group of interval duration data generated by calculation are output to the data output register 106, an interrupt signal is generated and sent to the external MCU, so that the external MCU can read and write data.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the equipment disclosed by the embodiment, the description is relatively simple because the equipment corresponds to the method disclosed by the embodiment, and the relevant parts can be referred to the method part for description.
It is further noted that, throughout this document, relational terms such as "first" and "second" are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The technical solutions provided by the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall into the protection scope of the present application.
Claims (5)
1. A time-to-digital conversion integrated circuit comprising a control register and a clock unit, characterized by further comprising:
the time-to-digital converter is used for carrying out edge time detection on the received starting pulse, the first channel stopping pulse and the second channel stopping pulse;
the raw data memory is connected with the time-to-digital converter and is used for storing the time data detected by the time-to-digital converter;
the arithmetic logic unit is connected with the original data memory and is used for automatically calculating a first group of interval duration data of the first channel stop pulse and the starting pulse and a second group of interval duration data of the second channel stop pulse and the starting pulse according to the time data;
the data output register is connected with the arithmetic logic unit and is used for storing the calculation result of the arithmetic logic unit;
and the SPI interface is connected with the data output register and is used for externally connecting an MCU (microprogrammed control unit) to read and write data.
2. The time-to-digital conversion integrated circuit of claim 1, wherein the START pulse is a pulse received by a START terminal of the time-to-digital converter when a laser emitting circuit emits laser light;
the time-to-digital converter has two independent STOP channels for edge time detection; the first channel STOP pulse is a pulse received by the first STOP channel after the laser light is reflected and received, and the second channel STOP pulse is a pulse received by the second STOP channel after the laser light is reflected and received.
3. The time-to-digital conversion integrated circuit of claim 2, wherein said two STOP channels are specifically configured to capture the same set of pulses for operating in single-channel double-precision mode;
alternatively, the two STOP channels are specifically configured to capture different sets of pulses, respectively, for operation in a dual channel single precision mode.
4. The time-to-digital conversion integrated circuit of claim 1, wherein each STOP channel of the time-to-digital converter has a maximum number of 10 pulses captured in a single duration; the data output register has 22 groups of data storage capacity; so that the external MCU excludes data corresponding to the interference pulse from the multi-group data.
5. The time-to-digital conversion integrated circuit of any of claims 1-4, wherein the arithmetic logic unit is further configured to:
and after the first group of interval duration data and the second group of interval duration data generated by calculation are output to the data output register, generating an interrupt signal and sending the interrupt signal to the external MCU so that the external MCU can read and write data conveniently.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020247460.5U CN211628021U (en) | 2020-03-03 | 2020-03-03 | Time-to-digital conversion integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020247460.5U CN211628021U (en) | 2020-03-03 | 2020-03-03 | Time-to-digital conversion integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211628021U true CN211628021U (en) | 2020-10-02 |
Family
ID=72620900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020247460.5U Active CN211628021U (en) | 2020-03-03 | 2020-03-03 | Time-to-digital conversion integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211628021U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111190341A (en) * | 2020-03-03 | 2020-05-22 | 杭州瑞盟科技有限公司 | Time-to-digital conversion integrated circuit and method |
-
2020
- 2020-03-03 CN CN202020247460.5U patent/CN211628021U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111190341A (en) * | 2020-03-03 | 2020-05-22 | 杭州瑞盟科技有限公司 | Time-to-digital conversion integrated circuit and method |
| CN111190341B (en) * | 2020-03-03 | 2024-05-03 | 杭州瑞盟科技股份有限公司 | Time-to-digital conversion integrated circuit and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108732553B (en) | Laser radar waveform time identification method and online ranging system | |
| EP3647884B1 (en) | Circuit, method and related chip for time measurement, system, and device | |
| US10353062B2 (en) | Methods and apparatus for narrowband ranging systems using reference signal interpolation | |
| CN106019300A (en) | Laser ranging device and laser ranging method thereof | |
| CN107843903B (en) | Multi-threshold TDC high-precision laser pulse distance measuring method | |
| CN204989471U (en) | Multiple target pulsed laser distancer | |
| CN102901970A (en) | Single-modulation continuous wave laser ranging device and method | |
| CN207601308U (en) | A kind of laser ranging system | |
| CN116300377B (en) | Time-to-digital converter and laser radar | |
| CN209117877U (en) | A kind of multi-channel high-accuracy laser time of flight measuring system | |
| CN112147626A (en) | Electronic device, control method of electronic device, and computer-readable storage medium | |
| CN211628021U (en) | Time-to-digital conversion integrated circuit | |
| CN110471075A (en) | Radar range finding method, apparatus and terminal device | |
| CN110988901A (en) | TDC (time-to-digital converter) combined phase laser ranging method and system | |
| CN108919234B (en) | Processing circuit for transmitting sampling signal and pulse type laser radar | |
| CN109444856B (en) | Integer period measuring circuit applied to high-resolution time-to-digital converter | |
| CN111190341A (en) | Time-to-digital conversion integrated circuit and method | |
| CN212779189U (en) | Laser rangefinder telescope based on MS1003 and range finding circuit thereof | |
| CN107272011B (en) | Time point identification method, time point identification circuit system and laser ranging system | |
| CN114509722A (en) | Angle measuring method, system and related device | |
| CN112462379A (en) | Distance measuring method, device, system and storage medium | |
| CN112711010A (en) | Laser ranging signal processing device, laser ranging equipment and corresponding method thereof | |
| CN113296104A (en) | Efficient measurement method of SPAD type laser radar | |
| CN112558097A (en) | Electronic device, control method of electronic device, and computer-readable storage medium | |
| CN213338033U (en) | Laser radar signal processing circuit and laser radar |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 310000 room 701, building 9, No. 1, Weiye Road, Puyan street, Binjiang District, Hangzhou City, Zhejiang Province Patentee after: Hangzhou ruimeng Technology Co.,Ltd. Address before: 310051 room 701, building 9, No.1 Weiye Road, Puyan street, Binjiang District, Hangzhou City, Zhejiang Province Patentee before: HANGZHOU RUIMENG TECHNOLOGY Co.,Ltd. |