CN211606542U

CN211606542U - Optical message merging and distributing device with accurate time control

Info

Publication number: CN211606542U
Application number: CN202020601221.5U
Authority: CN
Inventors: 苏毅波; 杨晓珑; 李未科
Original assignee: Guangdong Onlly Electrical & Automation Co ltd
Current assignee: Guangdong Onlly Electrical & Automation Co ltd
Priority date: 2020-04-21
Filing date: 2020-04-21
Publication date: 2020-09-29
Anticipated expiration: 2030-04-21

Abstract

The utility model discloses an accurate time control's light message merges distributing device, including FPGA processing chip, the synchronizing signal interface that is used for receiving the clock source signal, be used for with host computer communication and dispose the RS232 interface of distribution parameter, a plurality of self-adaptation optical network input interfaces that are used for receiving the optical network message that the external equipment produced, and a plurality of self-adaptation optical network output interfaces that are used for merging or distributing the optical network message; the synchronous signal interface and the RS232 interface are connected with an FPGA processing chip, the plurality of self-adaptive optical network input interfaces are connected with the input end of the FPGA processing chip, and the plurality of self-adaptive optical network output interfaces are connected with the output end of the FPGA processing chip; the utility model discloses a receive the synchronization pulse signal, can be unanimous with the equipment time reference of outside production light message, timing accuracy is high, can export the optical network message that has the requirement to time interval and light message quantity and form.

Description

Optical message merging and distributing device with accurate time control

Technical Field

The utility model belongs to the technical field of message processing, concretely relates to accurate time control's light message merges distributing device.

Background

In the field of power grids, a transformer substation develops from a traditional network to an intelligent transformer substation, equipment intellectualization and networking are required, and network messages need to conform to the IEC61850 standard, so that information digitization, information transmission networking and communication model standardization in the intelligent transformer substation are required, and therefore a large amount of network message data of the intelligent transformer substation needs to be monitored and transmitted. According to investigation and statistics of optical message forwarding devices sold by various manufacturers in the market, the device only has a single networking forwarding function at present and can basically meet some conventional communication requirements, but aiming at some special communication, for example, a plurality of optical messages are converted into 1 optical message, and a certain time interval is set for timed output and other functions, no optical message communication device at home and abroad can provide optical message merging and distribution with accurate time control at present.

SUMMERY OF THE UTILITY MODEL

The main object of the present invention is to overcome the disadvantages and deficiencies of the prior art, and to provide an optical packet merging and distributing device with precise time control, which can automatically identify whether the network port is a gigabit optical network or a gigabit optical network, and output optical network packets with requirements on time interval, optical packet quantity and format.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

an optical message merging and distributing device with accurate time control comprises an FPGA processing chip, a synchronous signal interface for receiving a clock source signal, an RS232 interface for communicating with an upper computer and configuring distribution parameters, a plurality of adaptive optical network input interfaces for receiving optical network messages generated by external equipment, and a plurality of adaptive optical network output interfaces for merging or distributing the optical network messages; the synchronous signal interface and the RS232 interface are connected with an FPGA processing chip, the plurality of self-adaptive optical network input interfaces are connected with the input end of the FPGA processing chip, and the plurality of self-adaptive optical network output interfaces are connected with the output end of the FPGA processing chip;

the FPGA processing chip adjusts local clock reference according to the received synchronous pulse signal of the synchronous signal interface, sends the parameters of the upper computer to the FPGA processing chip through the RS232 interface, enables the FPGA processing chip to operate according to a set mode, sets one or more self-adaptive optical network input interfaces as input, and outputs the received external optical messages to one or more self-adaptive optical network output interfaces according to a set time interval and a combination and distribution mode.

As a preferred technical solution, the FPGA processing chip includes a data processing conversion module, a clock synchronization module, a parameter configuration module, a data cache module, and an optical network interface rate self-adaptive module, and the clock synchronization module, the parameter configuration module, the data cache module, and the optical network interface rate self-adaptive module are all connected to the data processing conversion module.

As a preferred technical solution, the data cache module includes a first-level FIFO and a second-level FIFO, the first-level FIFO is used to store original data, and the second-level FIFO adds a reception time stamp, a channel identifier, and length information on the basis of the original data.

As a preferred technical solution, the optical network port rate self-adaptive module is used to switch the network port used for access to the hundreds of megabits SFP module or the gigas SFP module, and then automatically switch the interface connecting the FPGA and the PHY to the MII mode or the RGMII mode according to the current module reconfiguration parameters.

As a preferred technical solution, the adaptive optical network interface employs a gigabit ethernet transceiver 88E 1512.

Preferably, the synchronization signal interface is HFBR 2416.

As a preferred technical scheme, the RS232 interface adopts a USB-to-RS 232 chip to be connected to the FPGA processing chip.

Compared with the prior art, the utility model, following advantage and beneficial effect have:

(1) the utility model discloses utilize self-adaptation optical network input interface to come automatic identification this net gape to be hundred mega optical network or giga optical network, reduce the quantity of hardware cost and different speed optical network gaps.

(2) The utility model discloses a synchronous signal interface receives the pulse per second or IRIG-B sign indicating number is as the clock source, guarantees to export the optical network message with contrast time under the synchronous condition of external clock source, can be unanimous with the equipment time reference of outside production light message, and timing accuracy is high, can export the optical network message that has the requirement to time interval and light message quantity and form.

Drawings

Fig. 1 is a schematic circuit structure diagram of an optical packet merging and dispatching device with precise time control in an embodiment;

fig. 2 is a schematic circuit diagram of another FPFA chip.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The utility model discloses "connect" in each embodiment can indicate wired connection also can indicate wireless connection.

The embodiment of the utility model provides a pair of accurate time control's light message merges dispensing device, as shown in figure 1, include: the FPGA-based optical network system comprises an FPGA processing chip, a synchronous signal interface, an RS232 interface, a plurality of self-adaptive optical network input interfaces and a plurality of self-adaptive optical network output interfaces, wherein the synchronous signal interface and the RS232 interface are connected with the FPGA processing chip, the self-adaptive optical network input interfaces are connected with the input end of the FPGA processing chip, and the self-adaptive optical network output interfaces are connected with the output end of the FPGA processing chip.

The plurality of self-adaptive optical network input interfaces are used for receiving optical network messages generated by external equipment after automatically identifying the speed of the optical fiber network; the plurality of self-adaptive optical network output interfaces are used for regularly combining or distributing optical network messages according to the setting of the upper computer on the information subjected to internal cache processing; the synchronous signal interface receives the pulse per second or an IRIG-B code as a clock source, and outputs an optical network message by comparing time under the condition of synchronizing with an external clock source; the RS232 interface is configured as an interface for communicating with an upper computer for configuring the distribution parameters.

In one embodiment, the adaptive optical network input interface and the adaptive optical network output interface use a gigabit ethernet transceiver 88E1512 from MARVELL, which is a physical layer device containing a single gigabit ethernet transceiver that performs equalization, echo and crosstalk cancellation, data recovery, and error correction at gigabit per second data rates using advanced mixed signal processing. The utilization 88E1512 can switch whether the working network is in a hundred mega optical network or a gigabit optical network according to the setting of the CPU or the FPGA.

Furthermore, the number of the adaptive optical network input interfaces and the number of the adaptive optical network output interfaces are 8, and 8 88E1512 chips are connected to the FPGA processing chip; of course, the number of the adaptive optical network interfaces in this embodiment may also be 10, 12, and the like, and the number may be expanded and configured according to the actual requirement.

In one embodiment, the synchronization signal interface uses an HFBR2416 of the ahigao company for synchronization of the receiving optical module, and a bandwidth of up to 155Mb provides low jitter and stability of the synchronization pulses.

Furthermore, the interface of the synchronization signal is that the HFBR2416 is directly connected to the FPGA processing chip after passing through a high-speed comparator, and the HFBR2416 is an optical connector device integrating the PIN photo-detector and the preamplifier, so that a larger voltage signal can be directly output. In addition, the HFBR2416 can convert the optical signal transmitted in the optical fiber into an analog voltage signal, and since the signal amplitude of the receiver is much larger than the output signal of the PIN photodetector, the anti-electromagnetic interference capability is significantly improved compared with the PIN photodetector.

In one embodiment, the RS232 interface uses a baud rate of 115200bps, and both reading and setting parameters can be quickly responded. Furthermore, the RS232 interface is connected to the FPGA processor by using a USB-to-RS 232 chip, so that a miniUSB line can be used for connecting the optical message merging and distributing device instead of a special 9-pin RS232 line, and the size of the optical message merging and distributing device with accurate time control can be designed to be smaller.

In one embodiment, as shown in fig. 2, the FPGA processing chip of the precise time-controlled optical packet merging and distributing apparatus includes a data processing conversion module, a clock synchronization module, a parameter configuration module, a data cache module, and an optical network interface rate self-adaptive module, where the clock synchronization module, the parameter configuration module, the data cache module, and the optical network interface rate self-adaptive module are all connected to the data processing conversion module.

Furthermore, the function realized by the optical network interface adaptive module is that when the optical network interface uses optical modules with different speeds, the module is automatically identified to be a hundred-megabyte optical module or a giga-gigabit optical module, and then optical messages are received and sent according to the current optical module speed and then stored in the data cache module.

Furthermore, the data buffer module is composed of two levels of FIFOs, wherein the first level of FIFO is used for temporarily storing the data received by each optical network interface, then adding the identification corresponding to the serial number of the optical network interface, buffering the data of a plurality of first level of FIFOs to the second level of FIFO through a bus arbitrator, and then transmitting the data of the second level of FIFO to the data processing and converting module;

furthermore, the clock synchronization module mainly has the functions of simply filtering the received pulses, then performing an average calculation, removing time jitter, and then outputting the time jitter to the data processing conversion module.

Furthermore, the parameter configuration module has the main function of receiving the configuration parameters of the upper computer and converting the configuration parameters into a specified format to the data processing conversion module.

Furthermore, the data processing conversion module realizes the function of reacquiring the pulse signal output by the clock synchronization module and then adjusting the local clock reference according to a certain mode, wherein the clock reference can be used for high-precision timing and comparing time output messages to the optical network port, and the data processing conversion module combines the data from the data cache module into one packet of data or multiple packets of data according to set parameters and distributes the data to the set optical network port.

In one of which is implementedIn the example, the FPGA processing chip uses Zynq-7020 of Zynq series of extensible processing platform of xilinx company for integration

The software programmability of the processor and the hardware programmability of the FPGA not only can realize important analysis and hardware acceleration, but also highly integrates the functions of a CPU, a DSP, an ASSP and a mixed signal on a single device.

The technical scheme of the utility model in, FPGA handle the chip according to receiving the synchronizing pulse signal of synchronizing signal interface, adjust local clock benchmark, FPGA handles the chip is issued to the parameter of host computer to the rethread RS232 interface, lets FPGA handle the chip and moves according to the mode of setting for, then sets for a mouth or a plurality of light net mouths as the input, after receiving outside light message, exports a light net mouth or a plurality of light net mouths according to the time interval of setting for and merge distribution mode.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, however, as long as there is no contradiction between the combinations of the technical features, the scope of the present invention should be considered as the scope of the present invention.

The above-described embodiments merely represent some embodiments of the present invention, and are not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several changes and modifications can be made, and any changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention should be construed as equivalent substitutions and all fall within the protection scope of the present invention.

Claims

1. An optical message merging and distributing device with precise time control is characterized by comprising an FPGA processing chip, a synchronous signal interface for receiving a clock source signal, an RS232 interface for communicating with an upper computer and configuring distribution parameters, a plurality of adaptive optical network input interfaces for receiving optical network messages generated by external equipment, and a plurality of adaptive optical network output interfaces for merging or distributing the optical network messages; the synchronous signal interface and the RS232 interface are connected with an FPGA processing chip, the plurality of self-adaptive optical network input interfaces are connected with the input end of the FPGA processing chip, and the plurality of self-adaptive optical network output interfaces are connected with the output end of the FPGA processing chip;

2. The device for merging and distributing optical packets with precise time control according to claim 1, wherein the FPGA processing chip comprises a data processing and converting module, a clock synchronization module, a parameter configuration module, a data cache module, and an optical network interface rate self-adaptive module, and the clock synchronization module, the parameter configuration module, the data cache module, and the optical network interface rate self-adaptive module are all connected to the data processing and converting module.

3. The apparatus according to claim 2, wherein the data buffering module comprises a first stage FIFO and a second stage FIFO, the first stage FIFO is used for storing original data, and the second stage FIFO adds a receiving time stamp, a channel identifier and length information on the basis of the original data.

4. The apparatus according to claim 2, wherein the optical packet merging/distributing apparatus is characterized in that the optical network port rate self-adaptive module is used to access a hundreds of megabits SFP module or a gigas SFP module, and then the interface connecting the FPGA and the PHY is automatically switched to an MII mode or an RGMII mode according to the current module reconfiguration parameter.

5. The apparatus according to claim 1, wherein the adaptive optical network interface employs a gigabit ethernet transceiver 88E 1512.

6. The apparatus according to claim 1, wherein the synchronization signal interface employs HFBR 2416.

7. The device for merging and distributing the optical messages with accurate time control according to claim 1, wherein the RS232 interface is connected to the FPGA processing chip by using a USB to RS232 chip.