CN106021172B - A kind of method and device of data communication - Google Patents
A kind of method and device of data communication Download PDFInfo
- Publication number
- CN106021172B CN106021172B CN201610377147.1A CN201610377147A CN106021172B CN 106021172 B CN106021172 B CN 106021172B CN 201610377147 A CN201610377147 A CN 201610377147A CN 106021172 B CN106021172 B CN 106021172B
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- signal
- data packet
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- ethernet
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7817—Specially adapted for signal processing, e.g. Harvard architectures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
Abstract
The invention discloses a kind of method and devices of data communication, this method comprises: fpga chip receives the parallel signal that physical chip is sent, the parallel signal is ethernet signal after photoelectric conversion becomes electric signal, to preset the signal after the format transmission of serial signal carries out serioparallel exchange to the physical chip；The fpga chip extracts the data packet in the parallel signal, and after the data packet is handled according to preset format, is sent to CPU.This method is while realizing multichannel Ethernet and single cpu two-way communication, it can be improved bandwidth availability ratio, steadily by multichannel 100 m ethernet signal acquisition, and a large amount of interruption will not be generated when uploading data, to reduce the occupancy to cpu resource, system performance is improved on the whole.
Description
Technical field
The present embodiments relate to the technical field of communication more particularly to a kind of method and devices of data communication.
Background technique
As the universal and associated device cost of Ethernet reduces, ethernet communication have become in order to grown away from
Preferred implementation method from stabilized communication, so all there are at least one Ethernet interfaces for most of terminal devices, to complete
Data reporting and issuing.Currently, existing in the market much based on the data collecting card of Ethernet.Most of its design architecture is
Using exchange chip as data processing core, data collection terminal is the multiple physical layer (Physical being articulated on exchange chip
Layer, PHY) chip.
It is a PHY chip being articulated on exchange chip that data, which upload end,.When reporting Ethernet data, multichannel data
Enter exchange chip by the plug-in multiple PHY chips of exchange chip, storage forwarding is then carried out by exchange chip, finally by
PHY chip uploads to central processing unit (Central Processing Unit, CPU).When issuing data, the CPU will be counted
Exchange chip is transferred to by PHY according to packet, exchange chip is by deblocking data packet, then determines which for needing to be forwarded to collection terminal
A PHY.The two-way communication between multichannel Ethernet interface and single cpu can be completed in this way.
Since capture card is when reported data is to CPU, CPU can be notified by interrupt mode.When data needs frequently report
When, CPU needs to expend a large amount of resource and time to respond and interrupt, to reduce system performance.In addition, due to the hair of ether packet
Sending the frame gap and the length that are at least 96bits there are length is the guidance code of 8Bytes.When the ether packet length reported is shorter
When, this will cause in reported data, and there are a large amount of invalid datas, to reduce the utilization rate of bandwidth.
Summary of the invention
The purpose of the embodiment of the present invention is to propose a kind of method and device of data communication, it is intended to solve how to reduce to account for
With the resource of CPU preciousness, improve the problem of bandwidth availability ratio.
For this purpose, the embodiment of the present invention uses following technical scheme:
In a first aspect, a kind of method of data communication, which comprises
Fpga chip receives the parallel signal that physical chip is sent, and the parallel signal is that ethernet signal passes through photoelectricity
After conversion becomes electric signal, to preset the letter after the format transmission of serial signal carries out serioparallel exchange to the physical chip
Number；
The fpga chip extracts the data packet in the parallel signal, and the data packet is carried out according to preset format
After processing, it is sent to CPU.
Preferably, the fpga chip receives the parallel signal that physical chip is sent, and the parallel signal is Ethernet
Signal is gone here and there simultaneously with presetting the format transmission of serial signal to the physical chip after photoelectric conversion becomes electric signal
Signal after conversion, comprising:
The ethernet signal enters electrooptical device SFP1, becomes electric signal after photoelectric conversion, with SerDes
Serial signal format transmission to the physical chip, the physical chip to the electric signal of SerDes serial signal format into
Row unstrings, and the electric signal after unstringing is become parallel signal, and pass through MII bus transfer to the fpga chip.
Preferably, the fpga chip extracts the data packet in the parallel signal, and by the data packet according to default
After format is handled, it is sent to CPU, comprising:
The fpga chip in turn caches the data packet of the parallel signal of at least one data feedback channel, and record pair
The timestamp and channel number answered, package to all data packets according to preset format；
After group packet, ether encapsulating is carried out by MAC core and is wrapped, it is described by GMII bus transfer to SGMII core after package
Data packet after package is transferred to SerDes core again by SGMII core, and the SerDes core is reported to institute after serializing data packet
State CPU.
Preferably, the method also includes:
The CPU with preset format package, serialization, goes here and there the data packet for needing to be handed down to each channel by SerDes
Row of channels is transferred to the fpga chip；
The fpga chip unpacks the data packet issued, and lookup is issued to the corresponding data packet in each channel, then
Through MII bus transfer into corresponding physical chip, the light is transferred to after the physical chip is serialized
Power conversion device SFP1 is sent to Ethernet after row photoelectric conversion.
Preferably, the fpga chip is Lattice ECP3-17 fpga chip.
Second aspect, a kind of device of data communication, described device include:
First receiving module, for the parallel signal that physical chip is sent, the parallel signal is ethernet signal warp
After crossing photoelectric conversion and becoming electric signal, after the format transmission to physical chip progress serioparallel exchange to preset serial signal
Signal；
First processing module, for extracting the data packet in the parallel signal, and by the data packet according to default lattice
After formula is handled, it is sent to CPU.
Preferably, first receiving module, is used for:
The ethernet signal enters electrooptical device SFP1, becomes electric signal after photoelectric conversion, with SerDes
Serial signal format transmission to the physical chip, the physical chip to the electric signal of SerDes serial signal format into
Row unstrings, and the electric signal after unstringing is become parallel signal, and pass through MII bus transfer to the fpga chip.
Preferably, the first processing module, is used for:
The data packet of the parallel signal of at least one data feedback channel is cached in turn, and record corresponding timestamp and
Channel number packages to all data packets according to preset format；
After group packet, ether encapsulating is carried out by MAC core and is wrapped, it is described by GMII bus transfer to SGMII core after package
Data packet after package is transferred to SerDes core again by SGMII core, and the SerDes core is reported to institute after serializing data packet
State CPU.
Preferably, described device further include:
Second receiving module, for receive the CPU by SerDes serial-port be sent to each channel to preset
Format package, serialization data packet；
Second processing module, for unpacking to the data packet issued, lookup is issued to the corresponding data in each channel
Packet, then institute is transferred to after the physical chip is serialized into corresponding physical chip by MII bus transfer
Electrooptical device SFP1 is stated, is sent to Ethernet after row photoelectric conversion.
Preferably, the fpga chip is Lattice ECP3-17 fpga chip.
The embodiment of the present invention provides a kind of method and device of data communication, and fpga chip receives what physical chip was sent
Parallel signal, the parallel signal is ethernet signal after photoelectric conversion becomes electric signal, to preset the lattice of serial signal
Formula is transferred to the physical chip and carries out the signal after serioparallel exchange；The fpga chip extracts the number in the parallel signal
According to packet, and after the data packet is handled according to preset format, it is sent to CPU, is realizing multichannel Ethernet and single cpu
While two-way communication, the resource of CPU preciousness can be occupied less, bandwidth availability ratio is improved, steadily by multichannel 100 m ethernet
It is that will not generate a large amount of interruption uploading data, so that the occupancy to cpu resource is reduced, whole while signal acquisition
System performance is improved on body.
Detailed description of the invention
Fig. 1 is a kind of flow diagram of the method for data communication provided in an embodiment of the present invention；
Fig. 2 is the flow diagram of the method for another data communication provided in an embodiment of the present invention；
Fig. 3 is the flow diagram of the method for another data communication provided in an embodiment of the present invention；
Fig. 4 is a kind of the functional block diagram of the device of data communication provided in an embodiment of the present invention.
Specific embodiment
The embodiment of the present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this
Locate described specific embodiment and is used only for explaining the embodiment of the present invention, rather than the restriction to the embodiment of the present invention.In addition also
It should be noted that only parts related to embodiments of the present invention are shown rather than entire infrastructure for ease of description, in attached drawing.
It is a kind of flow diagram of the method for data communication provided in an embodiment of the present invention with reference to Fig. 1, Fig. 1.
In Fig. 1, the method for the data communication includes:
Step 101, fpga chip receives the parallel signal that physical chip is sent, and the parallel signal is ethernet signal
After photoelectric conversion becomes electric signal, serioparallel exchange is carried out to the physical chip to preset the format transmission of serial signal
Signal afterwards；
Specifically, as shown in Fig. 2, the efficient communication of 8 road 100 m ethernet interfaces and single cpu may be implemented in Fig. 2.
Preferably, the fpga chip receives the parallel signal that physical chip is sent, and the parallel signal is Ethernet
Signal is gone here and there simultaneously with presetting the format transmission of serial signal to the physical chip after photoelectric conversion becomes electric signal
Signal after conversion, comprising:
The ethernet signal enters electrooptical device SFP1, becomes electric signal after photoelectric conversion, with SerDes
Serial signal format transmission to the physical chip, the physical chip to the electric signal of SerDes serial signal format into
Row unstrings, and the electric signal after unstringing is become parallel signal, and pass through MII bus transfer to the fpga chip.
Step 102, the fpga chip extracts the data packet in the parallel signal, and by the data packet according to default
After format is handled, it is sent to CPU.
Preferably, the fpga chip extracts the data packet in the parallel signal, and by the data packet according to default
After format is handled, it is sent to CPU, comprising:
The fpga chip in turn caches the data packet of the parallel signal of at least one data feedback channel, and record pair
The timestamp and channel number answered, package to all data packets according to preset format；
After group packet, ether encapsulating is carried out by MAC core and is wrapped, it is described by GMII bus transfer to SGMII core after package
Data packet after package is transferred to SerDes core again by SGMII core, and the SerDes core is reported to institute after serializing data packet
State CPU.
Specifically, in data feedback channel, by wherein all the way for, other closed-circuit working principles are the same.Ethernet signal from
R1 enters optical electrical switching device SFP1 becomes electric signal by sr1 with SerDes serial signal format biography after optical electrical is converted
Defeated to arrive PHY1, physical chip PHY1, which unstring to SerDes signal, is changed into parallel signal, and passes through MII bus transfer
To fpga chip, fpga chip unpacks data packet in a few road row of channels, extract useful information, mark timestamp and
Then these packets are reorganized according to user-defined format, and are serialized by the corresponding source port of corresponding data packet, finally
CPU, which is uploaded to, by SerDes serial-port sr9 deals with analysis.
Wherein, t1, t2, t3, t4, t5, t6, t7, t8: the Ethernet output of system, downlink signal；
R1, r2, r3, r4, r5, r6, r7, r8: the Ethernet input of system, uplink signal；
SFP1, SFP2, SFP3, SFP4, SFP5, SFP6, SFP7, SFP8:SFP (Small Form-factor
Pluggable transceiver, small package pluggable transceiver) photoelectric conversion module；
Sr1-sr8: the serdes signal input of photoelectric yield module belongs to uplink signal；
St1-st8: the serdes signal output of photoelectric yield module, downlink signal；
PHY1-PHY8: physical chip completes the mutual conversion of SerDer signal and MII bus signals；
M1-m8:MII bus, two-way signaling, fpga chip are communicated by MII interface with PHY chip；
FPGA:FPGA (Field-Programmable Gate Array, i.e. field programmable gate array) chip, herein
Solution/package of Ethernet packet, the timestamp label of Ethernet packet, by customized packet format solution/package, data packet are completed in system
Report/issue the functions such as control；
CPU: as the administrative unit of system, to reported data carry out processing analysis and toward each collection terminal issue response and
Control command；
Clk: clock module provides clock for whole system work.
Preferably, the method also includes:
The CPU with preset format package, serialization, goes here and there the data packet for needing to be handed down to each channel by SerDes
Row of channels is transferred to the fpga chip；
The fpga chip unpacks the data packet issued, and lookup is issued to the corresponding data packet in each channel, then
Through MII bus transfer into corresponding physical chip, the light is transferred to after the physical chip is serialized
Power conversion device SFP1 is sent to Ethernet after row photoelectric conversion.
Wherein, the fpga chip is Lattice ECP3-17 fpga chip.
Specifically, as shown in Fig. 2, in down going channel, by wherein all the way for, other closed-circuit working principles are the same.CPU
The data for needing to be handed down to each channel are serialized with user-defined format package, then pass through SerDes serial-port st9
It is transferred to fpga chip, fpga chip is given out a contract for a project under to be unpacked, and is found out and is issued to the corresponding data content in each channel, then
Through MII bus transfer into corresponding PHY1 chip, data are transferred to photoelectric conversion after being serialized through PHY chip
Device SFP1 is sent to Ethernet through t1 after row photoelectric conversion.
Referring in addition to Fig. 3, in actual use, the operation of data uplink be it is such, 100 m ethernet signal pass through optical electrical
Conversion module is converted to electric signal, then through the serial channel SerDes enter 100 m ethernet physical chip unstringed and when
Clock restores, and (is user oneself inside fpga chip followed by MII bus transfer to Lattice ECP3-17 fpga chip
The solution write/package logic module, uplink/downlink channel selecting module, data cache module, what Lattice manufacturer provided
The IP kernels such as MAC, SGMII, SerDes), fpga chip in turn caches the data packet of 8 data feedback channels, while recording number
According to the timestamp and channel number of packet.Then to all data packets according to the customized format group packet of user.After group packet, pass through
MAC core carries out ether encapsulating packet, passes through GMII bus transfer to SGMII core after package, device is transferred to by SGMII core again
SerDes core, SerDes core are reported to T1040 after serializing data packet.
And the operation of data downstream is then as follows, the data and control that T1040 will be issued by the customized format of user are ordered
Group packet is enabled, then carries out ether encapsulating packet.Data packet is unpacked by SerDes channel transfer to FPGA, FPGA after package,
Then data packet is sent to respectively by corresponding channel by selector, then turned by 100 m ethernet PHY serialization and optical electrical
Mold changing block is sent to Ethernet after being converted to optical signal.
The embodiment of the present invention provides a kind of method of data communication, and fpga chip receives the parallel letter that physical chip is sent
Number, the parallel signal is ethernet signal after photoelectric conversion becomes electric signal, to preset the format transmission of serial signal
Signal after carrying out serioparallel exchange to the physical chip；The fpga chip extracts the data packet in the parallel signal,
And after being handled the data packet according to preset format, it is sent to CPU, is realizing that multichannel Ethernet and single cpu are two-way
While communication, the resource of CPU preciousness can be occupied less, bandwidth availability ratio is improved, steadily by multichannel 100 m ethernet signal
While acquisition, a large amount of interruption will not be generated when uploading data, to reduce the occupancy to cpu resource, on the whole
Improve system performance.
It is a kind of the functional block diagram of the device of data communication provided in an embodiment of the present invention with reference to Fig. 4, Fig. 4.
In Fig. 4, the device of the data communication includes:
First receiving module 401, for the parallel signal that physical chip is sent, the parallel signal is ethernet signal
After photoelectric conversion becomes electric signal, serioparallel exchange is carried out to the physical chip to preset the format transmission of serial signal
Signal afterwards；
Preferably, first receiving module 401, is used for:
The ethernet signal enters electrooptical device SFP1, becomes electric signal after photoelectric conversion, with SerDes
Serial signal format transmission to the physical chip, the physical chip to the electric signal of SerDes serial signal format into
Row unstrings, and the electric signal after unstringing is become parallel signal, and pass through MII bus transfer to the fpga chip.
First processing module 402, for extracting the data packet in the parallel signal, and by the data packet according to default
After format is handled, it is sent to CPU.
Preferably, the first processing module 402, is used for:
The data packet of the parallel signal of at least one data feedback channel is cached in turn, and record corresponding timestamp and
Channel number packages to all data packets according to preset format；
After group packet, ether encapsulating is carried out by MAC core and is wrapped, it is described by GMII bus transfer to SGMII core after package
Data packet after package is transferred to SerDes core again by SGMII core, and the SerDes core is reported to institute after serializing data packet
State CPU.
Preferably, described device further include:
Second receiving module, for receive the CPU by SerDes serial-port be sent to each channel to preset
Format package, serialization data packet；
Second processing module, for unpacking to the data packet issued, lookup is issued to the corresponding data in each channel
Packet, then institute is transferred to after the physical chip is serialized into corresponding physical chip by MII bus transfer
Electrooptical device SFP1 is stated, is sent to Ethernet after row photoelectric conversion.
Wherein, the fpga chip is Lattice ECP3-17 fpga chip.
The embodiment of the present invention provides a kind of device of data communication, and fpga chip receives the parallel letter that physical chip is sent
Number, the parallel signal is ethernet signal after photoelectric conversion becomes electric signal, to preset the format transmission of serial signal
Signal after carrying out serioparallel exchange to the physical chip；The fpga chip extracts the data packet in the parallel signal,
And after being handled the data packet according to preset format, it is sent to CPU, is realizing that multichannel Ethernet and single cpu are two-way
While communication, the resource of CPU preciousness can be occupied less, bandwidth availability ratio is improved, steadily by multichannel 100 m ethernet signal
It is that will not generate a large amount of interruption uploading data, to reduce the occupancy to cpu resource, on the whole while acquisition
Improve system performance.
Describe the technical principle of the embodiment of the present invention in conjunction with specific embodiments above.These descriptions are intended merely to explain this
The principle of inventive embodiments, and it cannot be construed to the limitation to protection scope of the embodiment of the present invention in any way.Based on herein
Explanation, those skilled in the art, which does not need to pay for creative labor, can associate the other specific of the embodiment of the present invention
Embodiment, these modes are fallen within the protection scope of the embodiment of the present invention.
Claims (7)
1. a kind of method of data communication, which is characterized in that the described method includes:
Fpga chip receives the parallel signal that physical chip is sent, and the parallel signal is that ethernet signal passes through photoelectric conversion
After becoming electric signal, to preset the signal after the format transmission of serial signal carries out serioparallel exchange to the physical chip；
The fpga chip extracts the data packet in the parallel signal, and the data packet is handled according to preset format
Afterwards, it is sent to CPU；
The fpga chip extracts the data packet in the parallel signal, and the data packet is handled according to preset format
Afterwards, it is sent to CPU, comprising:
The fpga chip in turn caches the data packet of the parallel signal of at least one data feedback channel, and records corresponding
Timestamp and channel number package to all data packets according to preset format；
After group packet, ether encapsulating packet is carried out by MAC core, passes through GMII bus transfer to SGMII core, the SGMII after package
Data packet after package is transferred to SerDes core again by core, and the SerDes core is reported to the CPU after serializing data packet.
2. the method according to claim 1, wherein the fpga chip receives the parallel of physical chip transmission
Signal, the parallel signal are ethernet signal after photoelectric conversion becomes electric signal, are passed with presetting the format of serial signal
Signal after the defeated progress serioparallel exchange to the physical chip, comprising:
The ethernet signal enters electrooptical device SFP1, becomes electric signal after photoelectric conversion, serial with SerDes
Signal format is transferred to the physical chip, and the physical chip solves the electric signal of SerDes serial signal format
String, and the electric signal after unstringing is become into parallel signal, and pass through MII bus transfer to the fpga chip.
3. according to the method described in claim 2, it is characterized in that, the method also includes:
The CPU with preset format package, serialization, serially leads to the data packet for needing to be handed down to each channel by SerDes
Road is transferred to the fpga chip；
The fpga chip unpacks the data packet issued, and lookup is issued to the corresponding data packet in each channel, then passes through
MII bus transfer is transferred to the photoelectricity after the physical chip is serialized and turns into corresponding physical chip
Parallel operation part SFP1, is sent to Ethernet after row photoelectric conversion.
4. according to the method described in claim 3, it is characterized in that, the fpga chip is Lattice ECP3-17 FPGA core
Piece.
5. a kind of device of data communication, which is characterized in that described device includes:
First receiving module, for the parallel signal that physical chip is sent, the parallel signal is that ethernet signal passes through light
After electricity conversion becomes electric signal, to preset the letter after the format transmission of serial signal carries out serioparallel exchange to the physical chip
Number；
First processing module, for extracting the data packet in the parallel signal, and by the data packet according to preset format into
After row processing, it is sent to CPU；
The first processing module, is used for:
The data packet of the parallel signal of at least one data feedback channel is cached in turn, and records corresponding timestamp and channel
Number, it is packaged to all data packets according to preset format；
After group packet, ether encapsulating packet is carried out by MAC core, passes through GMII bus transfer to SGMII core, the SGMII after package
Data packet after package is transferred to SerDes core again by core, and the SerDes core is reported to the CPU after serializing data packet.
6. device according to claim 5, which is characterized in that first receiving module is used for:
The ethernet signal enters electrooptical device SFP1, becomes electric signal after photoelectric conversion, serial with SerDes
Signal format is transferred to the physical chip, and the physical chip solves the electric signal of SerDes serial signal format
String, and the electric signal after unstringing is become into parallel signal, and pass through MII bus transfer to fpga chip.
7. device according to claim 6, which is characterized in that described device further include:
Second receiving module, for receive the CPU by SerDes serial-port be sent to each channel with preset format
Package, serialization data packet；
Second processing module, for unpacking to the data packet issued, lookup is issued to the corresponding data packet in each channel, then
Through MII bus transfer into corresponding physical chip, the light is transferred to after the physical chip is serialized
Power conversion device SFP1 is sent to Ethernet after row photoelectric conversion.
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| CN106782295B (en) * | 2016-12-26 | 2019-04-09 | 西安诺瓦电子科技有限公司 | LED box |
| CN107888519A (en) * | 2017-11-14 | 2018-04-06 | 湖北三江航天红峰控制有限公司 | A kind of local gigabit ethernet switch |
| CN108563607A (en) * | 2018-04-13 | 2018-09-21 | 成都赫尔墨斯科技股份有限公司 | A kind of device and method for improving communication and processing speed in avionics system |
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| CN2660795Y (en) * | 2003-12-03 | 2004-12-01 | 深圳市首迈通信技术有限公司 | Optical fiber Ethernet exchanger and monitor modular for same |
| CN102932489A (en) * | 2012-10-28 | 2013-02-13 | 中国电子科技集团公司第十研究所 | Multi-channel ARINC429 bus interface |
| CN103401741A (en) * | 2013-08-14 | 2013-11-20 | 北京泽华源科技有限公司 | Integrated circuit and data processing method |
| CN105099828A (en) * | 2015-08-25 | 2015-11-25 | 南京理工大学 | High performance network tester and the testing method thereof |
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| US20030226050A1 (en) * | 2000-12-18 | 2003-12-04 | Yik James Ching-Shau | Power saving for mac ethernet control logic |
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|---|---|---|---|---|
| CN2660795Y (en) * | 2003-12-03 | 2004-12-01 | 深圳市首迈通信技术有限公司 | Optical fiber Ethernet exchanger and monitor modular for same |
| CN102932489A (en) * | 2012-10-28 | 2013-02-13 | 中国电子科技集团公司第十研究所 | Multi-channel ARINC429 bus interface |
| CN103401741A (en) * | 2013-08-14 | 2013-11-20 | 北京泽华源科技有限公司 | Integrated circuit and data processing method |
| CN105099828A (en) * | 2015-08-25 | 2015-11-25 | 南京理工大学 | High performance network tester and the testing method thereof |
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