CN103401741A - Integrated circuit and data processing method - Google Patents
Integrated circuit and data processing method Download PDFInfo
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- CN103401741A CN103401741A CN2013103527178A CN201310352717A CN103401741A CN 103401741 A CN103401741 A CN 103401741A CN 2013103527178 A CN2013103527178 A CN 2013103527178A CN 201310352717 A CN201310352717 A CN 201310352717A CN 103401741 A CN103401741 A CN 103401741A
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Abstract
The invention relates to an integrated circuit and a data processing method. The integrated circuit comprises a serial signal receiving module, a 10G physical layer decoding module, a filtering module and a processing module, wherein the serial signal receiving module is used for deserializing received SFI to obtain parallel data flows; the 10G physical layer decoding module is used for decoding the parallel data flows to obtain Ethernet data packets; the filtering module is connected with the 10G physical layer decoding module, and is used for analyzing the Ethernet data packets and caching the Ethernet data packets consistent with filter parameters; the processing module is connected with the filtering module, and is used for reading the cached Ethernet data packets in a multicasting form and in a broadcasting form, revising the Ethernet data packets in a multicasting form and in a broadcasting form as an Ethernet data packet in a unicasting form, and sending the Ethernet data packet in a unicasting form according to the gigabit Ethernet or 100M Ethernet interface standard. The integrated circuit and the data processing method achieve the conversion from the 10G Ethernet multicast data flow to the 100M or gigabit Ethernet data flow, simplify the terminal design, and lower the cost.
Description
Technical field
The present invention relates to communication technical field, relate in particular to a kind of integrated circuit and data processing method.
Background technology
The 10G Ethernet also claims ten thousand mbit ethernets, and standard was passed through at IEEE in July, 2002.The 10G Ethernet comprises 10GBASE-X, 10GBASE-R, 10GBASE-W and based on the 10GBASE-T of copper cable etc. (2006 by).10GBASE-R is a kind of serial line interface of the 64B/66B of use coding, and data flow is 10.000Gbit/s, thereby the clock rate that produces is 10.3Gbit/s.10GBASE-W is Wide Area Network interface, and compatible with SONET OC-192, its clock is 9.953Gbit/s, and data flow is 9.585Gbit/s.The form that the 10G Ethernet still uses with 10Mbps is identical with the 100Mbps Ethernet in the past, it allows directly to be upgraded to express network.Same frame format and the flow control mode that uses IEEE 802.3 standards.In addition, the 10G Ethernet uses and has defined the management object identical with Ethernet by IEEE 802.3 groups.
In recent years, Broadcast and TV system also uses optical fiber to transmit the TV signal of broadcasting.And, in order to solve the problem of the limited and Bandwidth-Constrained of channel number that the modulation-demodulation technique that adopts in existing transmission means brings, a kind of novel broadcasting and TV fiber entering household scheme has been proposed: digital TV broadcast signal is adopted the mode one-way transmission of 10Gbps User Datagram Protoco (UDP) (User Data Protocol, UDP) data flow with multicast or broadcasting.
This scheme is held to register one's residence in the past and is all adopted passive optical-fiber network, fully phase out modulation-demodulation technique, for broadcasting service provides enough abundant bandwidth, and because broadcasting service is that an optical fiber is shifted huge numbers of families onto, its resource that takies especially backbone network and the local side device resource considerably less, can save system cost; In addition, solved the two-way interactive problem with the combination of passive optical-fiber network (Passive Optical Network, PON) technology.
But in this scheme, conventional receiving device comprises 10G bidirectional light receiving and transmitting module and the 10G Ethernet switching chip of supporting bidirectional transmit-receive.For only needing the broadcasting audio-video frequency content of downward one-way transmission, its two-way function that does not fully use has caused a kind of waste; The input and output speed of 10G Ethernet switching chip is all 10Gbps simultaneously, for the user, even many station terminals, need the radio and television bandwidth of rating simultaneously also usually to be no more than 100Mbps, therefore the output of 10Gbps design has not only caused the wasting of resources, and the switch end of 10Gbps is received and dispatched at a high speed interface and also significantly strengthened complexity and the cost of receiving terminal overall design.And, the packet of registering one's residence in this scheme is the packet of multicast or the forms of broadcasting, user's local area network (LAN) directly forwarding can cause a terminal request data flow in all ethernet layers broadcasting, certainly will take other users' band width in physical, and the waste local network resource.
Summary of the invention
Technical problem
In view of this, the technical problem to be solved in the present invention is to provide a kind of integrated circuit and data processing method, can either realize the unidirectional reception of 10Gbps data, can realize again the conversion process of multicast packet to unicast data, can also be converted to the 10G Ethernet interface 100,000,000 and/or gigabit ethernet interface of existing main flow terminal, reach the design of simplifying terminal and the purpose that reduces the terminal holistic cost.
Solution
In order to solve the problems of the technologies described above,, according to one embodiment of the invention, provide a kind of integrated circuit, comprising:
The serial signal receiver module, be used for the high-speed differential signal SFI that is not less than 10Gbps that receives is gone here and there and changes, and obtains parallel data stream;
10G physical layer decoder module, be connected with described serial signal receiver module, is used for described parallel data stream is decoded, and obtains the Ethernet data bag;
Filtering module, be connected with described 10G physical layer decoder module, is used for described Ethernet data bag is resolved, and Ethernet data bag that will be consistent with filter parameter carries out buffer memory; And
Processing module, be connected with described filtering module, Ethernet data bag for the multicast form and the forms of broadcasting that read buffer memory, and the Ethernet data of described multicast form and the forms of broadcasting is guaranteed the repair free of charge the Ethernet data bag that changes the clean culture form into, and send the Ethernet data bag of described clean culture form according to gigabit Ethernet or 100 m ethernet interface specification.
For said integrated circuit, in a kind of possible implementation, described serial signal receiver module comprises:
Clock and data recovery (Clock Data Recovery, CDR) unit, be used for recovering input clock and serial data stream from described SFI differential signal, and described serial data stream gone here and there and changed, and obtains parallel data stream.
For said integrated circuit, in a kind of possible implementation, described 10G physical layer decoder module comprises:
The piece lock unit, be connected with described clock and data recovery unit, is used for by searching the piece synchronous head of described parallel data stream, finds block boundary, and described parallel data stream is treated to blocks of data stream;
Descrambler, be connected with described lock unit, is used for described blocks of data is flow to capable data descrambling; And
Decoding unit, be connected with described descrambler, is used for the data block of the stream of the blocks of data after descrambling is separated with controll block, and removes the piece synchronous head, obtains the Ethernet data bag.
For said integrated circuit, in a kind of possible implementation, described filtering module comprises:
Buffer, be connected with described decoding unit, is used for the described Ethernet data bag of buffer memory;
Filter, be connected with described buffer, be used for described Ethernet data bag is resolved, field and filter parameter that parsing is obtained compare, and abandoning the Ethernet data bag of with arbitrary filter parameter, all misfitting, wherein said filter parameter comprises the purpose IP address of IP packet and the destination interface of protocol fields and UDP message bag; And
The buffering area control unit, be connected with described filter, and the Ethernet data bag buffer memory that is used for will be not abandoned by described filter is to built-in or external buffering area.
For said integrated circuit, in a kind of possible implementation, described processing module comprises:
The processing data packets unit, be connected with described buffer, be used for reading from described buffer the Ethernet data bag of multicast form and the forms of broadcasting of buffer memory, the Ethernet data bag that a plurality of destinations are needed copies, and determine MAC destination address and the IP destination address that this Ethernet data bag need to be sent to, and by MAC destination address and/or 32 purpose IP addresses of revising this Ethernet data bag, this Ethernet data is guaranteed the repair free of charge the Ethernet data bag that changes the clean culture form into; And
output control unit, be connected with described processing data packets unit, be used for according to IEEE802.3 and IEEE802.3u 100 m ethernet medium independent interface (Media Independent Interface, MII), simplify medium independent interface (Reduced MII, RMII) and/or gigabit Ethernet gigabit medium independent interface (Gigabit Medium Independent Interface, GMII), gigabit medium independent interface (Reduced Gigabit Media Independent Interface, RGMII) regulation, the form of the Ethernet data bag of described clean culture form with parallel data signal sent.
, for said integrated circuit, in a kind of possible implementation, also comprise:
Input bag resolution unit, be used for to receive the Ethernet input packet from 100 m ethernet MII, RMII interface and/or gigabit Ethernet GMII, RGMII interface, the lang method of going forward side by side resolves to draw any one or more in source MAC, target MAC (Media Access Control) address, source IP address, purpose IP address, protocol fields, destination interface and the control command of described Ethernet input packet; And
The control logic unit, be connected with described processing data packets unit, described input bag resolution unit and described filter, be used for providing parameter configuration and control to described processing data packets unit and described filter based on the data that receive from serial control interface and/or described input bag resolution unit.
In order to solve the problems of the technologies described above, according to another embodiment of the present invention, provide a kind of data processing method, adopt said integrated circuit to carry out:
For above-mentioned data processing method, in a kind of possible implementation, described step 10 specifically comprises:
Clock and data recovery unit in step 101, described serial signal receiver module recovers input clock from described SFI, and described SFI is gone here and there and changes, and obtains parallel data stream.
For above-mentioned data processing method, in a kind of possible implementation, described step 20 specifically comprises:
Piece lock unit in step 201, described 10G physical layer decoder module, by searching the piece synchronous head in described serial data stream, finds block boundary, and described serial data stream is treated to blocks of data stream;
Descrambler in step 202, described 10G physical layer decoder module flows to capable data descrambling to described blocks of data; And
The data block of the blocks of data stream of the decoding unit in step 203, described 10G physical layer decoder module after with descrambling is separated with controll block, and removes the piece synchronous head, obtains the Ethernet data bag.
For above-mentioned data processing method, in a kind of possible implementation, described step 30 specifically comprises:
The described Ethernet data bag of buffer buffer memory in step 301, described filtering module;
Filter in step 302, described filtering module is resolved described Ethernet data bag, field and filter parameter that parsing is obtained compare, and abandoning the Ethernet data bag of with arbitrary filter parameter, all misfitting, wherein said filter parameter comprises the purpose IP address of IP packet and the destination interface of protocol fields and UDP message bag; And
The Ethernet data bag buffer memory that buffering area control unit in step 303, described filtering module will be not be abandoned by described filter is to built-in or external buffering area.
For above-mentioned data processing method, in a kind of possible implementation, described step 40 specifically comprises:
Processing data packets unit in step 401, described processing module reads the Ethernet data bag of multicast form and the forms of broadcasting of buffer memory from described buffer, the Ethernet data bag that a plurality of destinations are needed copies, determine MAC destination address and IP destination address that this Ethernet data bag need to be sent to, and by MAC destination address and/or 32 purpose IP addresses of revising this Ethernet data bag, this Ethernet data is guaranteed the repair free of charge the Ethernet data bag that changes the clean culture form into; And
Output control unit in step 402, described processing module according in IEEE802.3 and IEEE802.3u to the regulation of 100 m ethernet MII, RMII interface and/or gigabit Ethernet GMII, RGMII interface, the form of the Ethernet data bag of described clean culture form with parallel data signal sent.
, for above-mentioned data processing method, in a kind of possible implementation, before described step 40, also comprise:
Input bag resolution unit in step 50, described integrated circuit receives the Ethernet input packet from 100 m ethernet MII, RMII interface and/or gigabit Ethernet GMII, RGMII interface, and the lang method of going forward side by side resolves to draw any one or more in source MAC, target MAC (Media Access Control) address, source IP address, purpose IP address, protocol fields, destination interface and the control command of described Ethernet input packet; And
Control logic unit in step 60, described integrated circuit provides parameter configuration and control to described processing data packets unit and described filter based on the data that receive from serial control interface and/or described input bag resolution unit.
Beneficial effect
By all parts being integrated on same circuit, the embodiment of the present invention is by being integrated in 10G physical layer process (PHY) parts and Ethernet packet parsing processing unit on an integrated circuit, simplified global design, cost more than 50%, for the 10G fiber entering household provides technical support; Secondly embodiment of the present invention copies and converts to unicast data with multicast and broadcast data and transmits, and has solved multicast message and has taken the problem of local band width in physical.
According to below with reference to accompanying drawing to detailed description of illustrative embodiments, it is clear that further feature of the present invention and aspect will become.
Description of drawings
The accompanying drawing that is included in specification and forms the part of specification shows exemplary embodiment of the present invention, feature and aspect together with specification, and is used for explaining principle of the present invention.
The structural representation of the integrated circuit that Fig. 1 provides for one embodiment of the invention;
The structural representation of the integrated circuit that Fig. 2 provides for another embodiment of the present invention;
The flow chart of the data processing method that Fig. 3 provides for another embodiment of the present invention;
The flow chart of the data processing method that Fig. 4 provides for another embodiment of the present invention;
Fig. 5 is the schematic diagram of descrambling step of the present invention;
Fig. 6 is the schematic diagram of decoding step of the present invention;
Fig. 7 (a), (b) and (c) be respectively different message format schematic diagrames.
Embodiment
Describe various exemplary embodiments of the present invention, feature and aspect in detail below with reference to accompanying drawing.The identical same or analogous element of Reference numeral presentation function in accompanying drawing.Although the various aspects of embodiment shown in the drawings, unless otherwise indicated, needn't draw accompanying drawing in proportion.
Here special-purpose word " exemplary " means " as example, embodiment or illustrative ".Here needn't be interpreted as being better than or being better than other embodiment as " exemplary " illustrated any embodiment.
In addition,, for better explanation the present invention, provided numerous details in embodiment hereinafter.It will be appreciated by those skilled in the art that and there is no these details, the present invention can implement equally.In the other example, method, means, element and the circuit known for everybody are not described in detail, so that highlight purport of the present invention.
The structural representation of the integrated circuit that Fig. 1 provides for one embodiment of the invention, as shown in Figure 1, integrated circuit 10 comprises serial signal receiver module 1,10G physical layer decoder module 2, filtering module 3 and processing module 4.
Wherein, serial signal receiver module 1 is used for the high-speed differential signal that is not less than 10Gbps (High speed Differential Signal, SFI) that receives is gone here and there and conversion process, obtains parallel data stream; 10G physical layer decoder module 2 is connected with serial signal receiver module 1, is used for this parallel data stream is decoded to obtain the Ethernet data bag; Filtering module 3 is connected with 10G physical layer decoder module 2, is used for the Ethernet data bag is resolved, and Ethernet data bag that will be consistent with filter parameter carries out buffer memory; Processing module 4 is connected with filtering module 3, Ethernet data bag for the multicast form and the forms of broadcasting that read buffer memory, the Ethernet data of multicast form and the forms of broadcasting is guaranteed the repair free of charge the Ethernet data bag that changes the clean culture form into, and sent the Ethernet data bag of described modification clean culture form according to gigabit Ethernet or 100 m ethernet interface specification.
the structural representation of the integrated circuit that Fig. 2 provides for another embodiment of the present invention, as shown in Figure 2, integrated circuit 20 comprises: the clock and data recovery unit 11 that constitutes serial signal receiver module 1, constitute the piece lock unit 21 of 10G physical layer decoder module 2, descrambler 22 and 64B/66B codeword decoding unit 23, constitute the FIFO fifo buffer 31 of filtering module 3, Ethernet IP filter 32 and buffering area control unit 33, constitute processing data packets unit 41 and the FE/GE output control unit 42 of processing module 4, and FE/GE input bag resolution unit 5 and control logic unit 6.
Wherein, clock and data recovery unit 11 is used for recovering input clock signal and serial data stream from SFI, and this serial data stream is gone here and there and changed, and obtains parallel data stream.particularly, clock and data recovery unit 11 take the input the 156.25MHz reference clock as basic clock, built-in phase-locked loop (Phase Locked Loop, PLL) the high speed reference clock after the circuit evolving multiple frequence, the high speed reference clock carries out edge sampling and data sampling to the high-speed differential signal that receives after phase interpolator separately, built-in state machine is adjusted phase interpolator according to the result of sampling, to follow the tracks of the slight change of phase difference, serial clock signal and serial data stream thus are restored, this serial data stream is gone here and there and changed, and with the piece lock unit 21 that recovers the clock signal obtain and parallel data stream and output to rear class.
G(x)=1+x^39+x^58，
Adopt shift register and XOR adder to realize descrambling in the present embodiment.
64B/66B codeword decoding unit 23 is connected with descrambler 22, is used for the blocks of data stream after descrambling is judged, data block is separated with controll block, and remove the synchronous head of the 2bit of piece.The MAC layer data that obtains thus is exactly the Ethernet data bag, deposits this Ethernet data bag in first in first out (First Input First Output, FIFO) buffer 31 and preserves.
Ethernet IP filter 32 is connected with FIFO buffer 31, is used for reading the Ethernet data bag according to the regulation of IEEE802.3ae XGMII with the speed of 156.25MHz from FIFO buffer 31, and this Ethernet data bag is filtered.Tool is sayed it, and Ethernet IP filter 32 comprises one group of packet filtering, and the parameter of each filter comprises: IP destination address and UDP destination slogan.At first Ethernet IP filter 32 carries out syntax parsing according to IEEE802.3 to the Ethernet data bag, obtains target MAC (Media Access Control) address and the type field of Ethernet data bag.For the IP packet, 32 of Ethernet IP filters are further resolved 32 purpose IP addresses and the 8 bit protocol fields of IP bag; For the UDP message bag, 32 of Ethernet IP filters further parse 16 destination slogans of UDP message bag, then the field that parsing is obtained and each filter parameters compare respectively, the MAC bag that to all misfit with all filter parameter directly abandons, namely filter out the MAC bag of with all filter parameter, all misfitting, and the MAC that will fit like a glove with any filter parameters bag stays, and be sent to buffering area control unit 33 and carry out buffer memory, the message format of various packets is as Fig. 7 (a) and (b) with (c).
Buffering area control unit 33 is connected with Ethernet IP filter 32, and the filtered MAC bag buffer memory that is used for burst is sent is to built-in or external buffering area.Consider the shake of broadcasting of the shake of each level router of IP network itself and source server or encoding device, the buffering area of design needs to preserve the above burst input data of 100ms.Calculate take the user side data volume as 100Mbps, buffering area needs greater than 10Mbits, adopt fifo structure, the burst writing speed of buffering area will be higher than 10Gbps, adopt parallel 64 interfaces, write clock speed is 156.25MHz,, if need the larger data volume of buffer memory, can realize by external 16 DDR2 or DDR3 SDRAM memory.
Processing data packets unit 41 is connected with buffering area control unit 33, be used for reading from buffering area the Ethernet data bag of multicast form and the forms of broadcasting of buffer memory, determine MAC destination address and IP destination address that this Ethernet data bag need to be sent to, and by Ethernet destination address (being the MAC destination address) and/or 32 purpose IP addresses of revising this Ethernet data bag, this Ethernet data is guaranteed the repair free of charge the Ethernet data bag that changes the clean culture form into.Particularly, the Ethernet data bag is read from buffering area in processing data packets unit 41, this processing data packets unit 41 checks each Ethernet data bag, the Ethernet data of multicast form and the forms of broadcasting is guaranteed the repair free of charge and changed unicast packet into, enable to transmit at local area network (LAN) in the mode of point-to-point clean culture; And determine MAC destination address and the IP destination address that the packets need of reading sends to; When the Ethernet data bag need to send to a plurality of destination address, this packet is copied and is converted to unicast packet again, be sent to respectively different destination addresses same message is copied a plurality of unicast packet that obtain, then the message of Ethernet data bag is modified, revised context comprises: Ethernet destination address, 32 purpose IP addresses, 16 stem checks and, the CRC check and.
FE/GE output control unit 42 is connected with processing data packets unit 41, for the Ethernet data bag after reception ﹠ disposal, according in IEEE802.3 and IEEE802.3u to the regulation of 100 m ethernet MII, RMII interface and/or gigabit Ethernet GMII, RGMII interface, the form of the Ethernet data bag of clean culture form with parallel data signal sent.
FE/GE input bag resolution unit 5 is connected with FE/GE output control unit 42, be used for to receive the Ethernet data bag from MII, RMII interface and/or GMII, RGMII interface, carry out syntax parsing according to the IEEE802.3 regulation and obtain source MAC, target MAC (Media Access Control) address, the 32 potential source IP addresses of packet, 32 purpose IP addresses and 8 bit protocol fields.For udp protocol, further parse 16 destination interfaces of UDP bag, resolve the data byte of the packet of specifying udp port in the mode of arranging in advance, obtain various instructions from outside, comprising information such as the parameter of Ethernet IP filter 32 arrange.
The flow chart of the data processing method that Fig. 3 provides for another embodiment of the present invention, as shown in Figure 3, this data processing method is carried out by said integrated circuit, comprising:
The flow chart of the data processing method that Fig. 4 provides for another embodiment of the present invention, in conjunction with shown in Figure 2, the method comprises:
Clock and data recovery unit 11 in step 101, serial signal receiver module 1 recovers input clock and serial data stream from the SFI that is not less than 10Gbps that receives, and this serial data stream is gone here and there and changed, and obtains parallel data stream.
22 pairs of blocks of data of descrambler in step 202,10G physical layer decoder module 2 flow to capable data descrambling, as shown in Figure 5.
64B/66B codeword decoding unit 23 in step 203,10G physical layer decoder module 2 separates the data block of the stream of the blocks of data after descrambling with controll block, and removes the piece synchronous head, obtains the Ethernet data bag.
This Ethernet data bag of FIFO buffer 31 buffer memorys in step 301, filtering module 3;
32 pairs of these Ethernet data bags of Ethernet IP filter in step 302, filtering module 3 carry out syntax parsing, further parse 32 purpose IP addresses of IP packet and 8 bit protocol fields, and 16 destination interfaces that parse the UDP bag; Field and filter parameter that parsing is obtained compare, and abandon the Ethernet data bag of with arbitrary filter parameter, all misfitting; This filter parameter comprises: the destination slogan of the destination address of purpose IP packet and UDP message bag, as shown in Figure 6.
Buffering area control unit 33 in step 303, filtering module 3 will send to built-in or external buffering area with the Ethernet data bag that any filter parameters fits like a glove.
Processing data packets unit 41 in step 401, processing module 4 reads the Ethernet data bag of multicast form and the forms of broadcasting of buffer memory from buffering area, if a plurality of IP destinations need this packet, need to copy this packet, and determine MAC destination address and the IP destination address that this Ethernet data bag need to be sent to, and by MAC destination address and/or 32 purpose IP addresses of revising this Ethernet data bag, this Ethernet data is guaranteed the repair free of charge the Ethernet data bag that changes the clean culture form into;
FE/GE output control unit 42 in step 402, processing module 4 receives amended Ethernet data bag, according in IEEE802.3 and IEEE802.3u to the regulation of 100 m ethernet MII, RMII interface and/or gigabit Ethernet GMII, RGMII interface, the form of amended Ethernet data bag with parallel data signal sent, and described gigabit Ethernet or 100 m ethernet interface specification comprise one of RMII, MII, GMII or RGMII interface specification at least.
In a kind of possible implementation, as shown in Figure 4, also comprised before step 401:
The Ethernet data bag that FE/GE in step 50, integrated circuit 10 input bag resolution unit 5 receives from MII, RMII interface and/or GMII, RGMII interface, the lang method of going forward side by side resolve to draw any one or more in source MAC, target MAC (Media Access Control) address, source IP address, purpose IP address, protocol fields, destination interface and the control command of Ethernet input packet;
Those of ordinary skills can recognize, each exemplary cell and algorithm steps in embodiment described herein can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions realize with hardware or software form actually, depend on application-specific and the design constraint of technical scheme.The professional and technical personnel can realize described function for specific application choice diverse ways, but this realization should not thought and exceeds scope of the present invention.
, if the form of computer software of using realizes described function and as production marketing independently or while using, can think to a certain extent that all or part of (part that for example prior art is contributed) of technical scheme of the present invention is with the form embodiment of computer software product.This computer software product is stored in the storage medium of embodied on computer readable usually, comprises that some instructions are used so that computer equipment (can be personal computer, server or the network equipment etc.) is carried out all or part of step of various embodiments of the present invention method.And aforesaid storage medium comprises the various media that can be program code stored such as USB flash disk, portable hard drive, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disc or CD.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion by described protection range with claim.
Claims (12)
1. an integrated circuit, is characterized in that, comprising:
The serial signal receiver module, be used for the high-speed differential signal SFI that is not less than 10Gbps that receives is gone here and there and changes, and obtains parallel data stream;
10G physical layer decoder module, be connected with described serial signal receiver module, is used for described parallel data stream is decoded, and obtains the Ethernet data bag;
Filtering module, be connected with described 10G physical layer decoder module, is used for described Ethernet data bag is resolved, and Ethernet data bag that will be consistent with filter parameter carries out buffer memory; And
Processing module, be connected with described filtering module, Ethernet data bag for the multicast form and the forms of broadcasting that read buffer memory, and the Ethernet data of described multicast form and the forms of broadcasting is guaranteed the repair free of charge the Ethernet data bag that changes the clean culture form into, and send the Ethernet data bag of described clean culture form according to gigabit Ethernet or 100 m ethernet interface specification.
2. integrated circuit according to claim 1, is characterized in that, described serial signal receiver module comprises:
The clock and data recovery unit, be used for recovering input clock and serial data stream from described SFI, and described serial data stream gone here and there and changed, and obtains parallel data stream.
3. integrated circuit according to claim 2, is characterized in that, described 10G physical layer decoder module comprises:
The piece lock unit, be connected with described clock and data recovery unit, is used for by searching the piece synchronous head of described parallel data stream, finds block boundary, and described parallel data stream is treated to blocks of data stream;
Descrambler, be connected with described lock unit, is used for described blocks of data is flow to capable data descrambling; And
Decoding unit, be connected with described descrambler, is used for the data block of the stream of the blocks of data after descrambling is separated with controll block, and removes the piece synchronous head, obtains the Ethernet data bag.
4. integrated circuit according to claim 3, is characterized in that, described filtering module comprises:
Buffer, be connected with described decoding unit, is used for the described Ethernet data bag of buffer memory;
Filter, be connected with described buffer, be used for described Ethernet data bag is resolved, field and filter parameter that parsing is obtained compare, and abandoning the Ethernet data bag of with arbitrary filter parameter, all misfitting, wherein said filter parameter comprises the purpose IP address of IP packet and the destination interface of protocol fields and UDP message bag; And
The buffering area control unit, be connected with described filter, and the Ethernet data bag buffer memory that is used for will be not abandoned by described filter is to built-in or external buffering area.
5. integrated circuit according to claim 4, is characterized in that, described processing module comprises:
The processing data packets unit, be connected with described buffering area control unit, be used for reading from described buffering area the Ethernet data bag of multicast form and the forms of broadcasting of buffer memory, the Ethernet data bag that a plurality of destinations are needed copies, determine MAC destination address and IP destination address that this Ethernet data bag need to be sent to, and by MAC destination address and/or 32 purpose IP addresses of revising this Ethernet data bag, this Ethernet data is guaranteed the repair free of charge the Ethernet data bag that changes the clean culture form into; And
Output control unit, be connected with described processing data packets unit, be used for according to IEEE802.3 and IEEE802.3u the regulation of 100 m ethernet MII, RMII interface and/or gigabit Ethernet GMII, RGMII interface is sent the form of the Ethernet data bag of described clean culture form with parallel data signal.
6. integrated circuit according to claim 5, is characterized in that, also comprises:
Input bag resolution unit, be used for to receive the Ethernet input packet from 100 m ethernet MII, RMII interface and/or gigabit Ethernet GMII, RGMII interface, the lang method of going forward side by side resolves to draw any one or more in source MAC, target MAC (Media Access Control) address, source IP address, purpose IP address, protocol fields, destination interface and the control command of described Ethernet input packet; And
The control logic unit, be connected with described processing data packets unit, described input bag resolution unit and described filter, be used for providing parameter configuration and control to described processing data packets unit and described filter based on the data that receive from serial control interface and/or described input bag resolution unit.
7. a data processing method, is characterized in that, adopts the described integrated circuit of claim 1-6 any one to carry out:
Step 10, utilize the serial signal receiver module in described integrated circuit go here and there and change the SFI that is not less than 10Gbps that receives, obtain parallel data stream;
Step 20, utilize the 10G physical layer decoder module in described integrated circuit to decode to described parallel data stream, obtain the Ethernet data bag;
Step 30, utilize the filtering module in described integrated circuit to resolve described Ethernet data bag, Ethernet data bag that will be consistent with filter parameter carries out buffer memory; And
Step 40, utilize processing module in described integrated circuit to read the Ethernet data bag of multicast form and the forms of broadcasting of buffer memory, the Ethernet data of described multicast form and the forms of broadcasting is guaranteed the repair free of charge the Ethernet data bag that changes the clean culture form into, and sent the Ethernet data bag of described clean culture form according to gigabit Ethernet or 100 m ethernet interface specification.
8. data processing method according to claim 7, is characterized in that, described step 10 specifically comprises:
Clock and data recovery unit in step 101, described serial signal receiver module recovers input clock and serial data stream from described SFI, and described serial data stream is gone here and there and changed, and obtains parallel data stream.
9. data processing method according to claim 8, is characterized in that, described step 20 specifically comprises:
Piece lock unit in step 201, described 10G physical layer decoder module, by searching the piece synchronous head in described parallel data stream, finds block boundary, and described parallel data stream is treated to blocks of data stream;
Descrambler in step 202, described 10G physical layer decoder module flows to capable data descrambling to described blocks of data; And
The data block of the blocks of data stream of the decoding unit in step 203, described 10G physical layer decoder module after with descrambling is separated with controll block, and removes the piece synchronous head, obtains the Ethernet data bag.
10. data processing method according to claim 9, is characterized in that, described step S30 specifically comprises:
The described Ethernet data bag of buffer buffer memory in step 301, described filtering module;
Filter in step 302, described filtering module is resolved described Ethernet data bag, field and filter parameter that parsing is obtained compare, and abandoning the Ethernet data bag of with arbitrary filter parameter, all misfitting, wherein said filter parameter comprises the purpose IP address of IP packet and the destination interface of protocol fields and UDP message bag; And
The Ethernet data bag buffer memory that buffering area control unit in step 303, described filtering module will be not be abandoned by described filter is to built-in or external buffering area.
11. data processing method according to claim 10, is characterized in that, described step 40 specifically comprises:
Processing data packets unit in step 401, described processing module reads the Ethernet data bag of multicast form and the forms of broadcasting of buffer memory from described buffering area, the Ethernet data bag that a plurality of destinations are needed copies, and determine MAC destination address and the IP destination address that this Ethernet data bag need to be sent to, and by MAC destination address and/or 32 purpose IP addresses of revising this Ethernet data bag, this Ethernet data is guaranteed the repair free of charge the Ethernet data bag that changes the clean culture form into; And
Output control unit in step 402, described processing module according in IEEE802.3 and IEEE802.3u to the regulation of 100 m ethernet MII, RMII interface and/or gigabit Ethernet GMII, RGMII interface, the form of the Ethernet data bag of described clean culture form with parallel data signal sent.
12. data processing method according to claim 11, is characterized in that, before described step 40, also comprises:
Input bag resolution unit in step 50, described integrated circuit receives the Ethernet input packet from 100 m ethernet MII, RMII interface and/or gigabit Ethernet GMII, RGMII interface, and the lang method of going forward side by side resolves to draw any one or more in source MAC, target MAC (Media Access Control) address, source IP address, purpose IP address, protocol fields, destination interface and the control command of described Ethernet input packet; And
Control logic unit in step 60, described integrated circuit provides parameter configuration and control to described processing data packets unit and described filter based on the data that receive from serial control interface and/or described input bag resolution unit.
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