CN211554216U

CN211554216U - Fusion detection processing circuit of switch cabinet partial discharge signal

Info

Publication number: CN211554216U
Application number: CN201922368919.7U
Authority: CN
Inventors: 陈�峰; 张帆; 胡翔; 孔亚广; 缪宇峰; 冯姗姗; 姜伊欣; 陈悦; 余桂华; 俞啸玲; 郑中庭
Original assignee: Hangzhou Dianzi University; Hangzhou Power Equipment Manufacturing Co Ltd; Hangzhou Power Supply Co of State Grid Zhejiang Electric Power Co Ltd
Current assignee: Hangzhou Dianzi University; Hangzhou Power Equipment Manufacturing Co Ltd; Hangzhou Power Supply Co of State Grid Zhejiang Electric Power Co Ltd
Priority date: 2019-12-24
Filing date: 2019-12-24
Publication date: 2020-09-22
Anticipated expiration: 2029-12-24

Abstract

The application discloses signal's fusion detection processing circuit is put in cubical switchboard office includes: a first detection circuit for detecting a ground wave, a second detection circuit for detecting an ultrasonic wave, and a third detection circuit for detecting a high-frequency wave; the first filter circuit, the second filter circuit and the third filter circuit are sequentially connected with the first detection circuit, the second detection circuit and the third detection circuit; the summation amplifying circuit is respectively connected with the first filter circuit, the second filter circuit and the third filter circuit and is used for carrying out signal superposition amplification; the transmitting circuit is connected with the summing amplifying circuit and used for transmitting signals; and the receiving device is used for receiving the signal transmitted by the transmitting circuit. By applying the scheme of the application, the partial discharge signal can be effectively detected and processed, and more accurate signal analysis results can be obtained.

Description

Fusion detection processing circuit of switch cabinet partial discharge signal

Technical Field

The utility model relates to a signal processing technology field especially relates to a signal's fusion detection processing circuit is put in cubical switchboard office.

Background

In an insulation system of an electrical apparatus, the electric field intensity of each part is often unequal, when the electric field intensity of a local area reaches the breakdown field intensity of the dielectric of the area, a discharge occurs in the area, but the discharge does not penetrate between two conductors applying voltage, namely the whole insulation system does not break down, and the insulation performance is still maintained, and the phenomenon is called partial discharge. Partial discharge is a ubiquitous problem in insulation, and under certain conditions, the partial discharge can cause the reduction of insulation performance, even cause serious conditions such as fire and the like, and threaten the safe operation of a system.

Partial discharge is a very complicated physical process, and in the process of occurrence, a discharge signal can be simultaneously expressed in the forms of electricity, sound, light, heat and the like.

At present, for the expression form of the partial discharge signal, a plurality of detection methods of the partial discharge signal are correspondingly generated, such as a geoelectric wave detection method, an ultrasonic detection method, an ultra high frequency detection method, a portable partial discharge detector based on the UHF method, a GIS partial discharge online detection of 330kV, and the like. However, these methods have respective disadvantages, for example, the geoelectric wave detection method cannot detect on-line, the signal attenuation detected by the ultrasonic wave detection method is too large, and the detection distance is limited; the cost of the ultra-high frequency detection method is too high. Particularly, in practical applications, the frequencies of the partial discharge signals are different and irregularly following under different occasions, so that the conventional detection method is difficult to be applied to complicated application scenarios. For example, if the intensity of the ground wave in the partial discharge signal is low and the intensity of the ultrasonic wave is high at a certain time, a more accurate analysis result cannot be obtained if the detection and analysis of the partial discharge signal is performed by the ground wave detection method.

In summary, how to effectively detect and process the partial discharge signal is a technical problem that needs to be solved by those skilled in the art.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a signal's integration detection processing circuit is put in cubical switchboard office to carry out the office effectively and put the detection and the processing of signal.

In order to solve the technical problem, the utility model provides a following technical scheme:

a fusion detection processing circuit of a switch cabinet partial discharge signal comprises:

a first detection circuit for detecting a ground wave, a second detection circuit for detecting an ultrasonic wave, and a third detection circuit for detecting a high-frequency wave;

the first filter circuit, the second filter circuit and the third filter circuit are sequentially connected with the first detection circuit, the second detection circuit and the third detection circuit;

the summation amplifying circuit is respectively connected with the first filter circuit, the second filter circuit and the third filter circuit and is used for carrying out signal superposition amplification;

the transmitting circuit is connected with the summing amplifying circuit and used for transmitting signals;

and the receiving device is used for receiving the signal transmitted by the transmitting circuit.

Preferably, the method further comprises the following steps: and the analog switch circuits are respectively connected with the first filter circuit, the second filter circuit, the third filter circuit and the summing and amplifying circuit and are used for receiving selection signals and outputting each signal which accords with the selection signals in the received output signals of the three filter circuits to the summing and amplifying circuit.

Preferably, the analog switch circuit comprises a first multi-path analog switch chip;

a first input end of the first multi-path analog switch chip is connected with an output end of the first filter circuit, and a first output end of the first multi-path analog switch chip is connected with a first input end of the summing and amplifying circuit; when the first control end of the first multi-path analog switch chip receives a first control signal, the first output end of the first multi-path analog switch chip is conducted with the first input end of the first multi-path analog switch chip;

a second input end of the first multi-path analog switch chip is connected with an output end of the second filter circuit, and a second output end of the first multi-path analog switch chip is connected with a second input end of the summing and amplifying circuit; when the second control end of the first multi-path analog switch chip receives a second control signal, the second output end of the first multi-path analog switch chip is conducted with the second input end of the first multi-path analog switch chip;

a third input end of the first multi-path analog switch chip is connected with an output end of the third filter circuit, and a third output end of the first multi-path analog switch chip is connected with a third input end of the summing and amplifying circuit; and when the third control end of the first multi-path analog switch chip receives a third control signal, the third output end of the first multi-path analog switch chip is conducted with the third input end of the first multi-path analog switch chip.

Preferably, the summing amplification circuit includes:

the first resistor is used as a first input end of the summing amplification circuit at a first end, and the second end of the first resistor is connected with the inverting input end of the first operational amplifier;

the first end of the second resistor is used as the second input end of the summing amplifying circuit, and the second end of the second resistor is connected with the inverting input end of the first operational amplifier;

the first end of the third resistor is used as a third input end of the summing amplifying circuit, and the second end of the third resistor is connected with the inverting input end of the first operational amplifier;

the non-inverting input end of the first operational amplifier is connected with the second end of the second resistor, and the output end of the first operational amplifier is used as the output end of the summing and amplifying circuit;

the fourth resistor with the first end grounded;

and the first end of the fifth resistor is connected with the inverting input end of the first operational amplifier, and the second end of the fifth resistor is connected with the output end of the first operational amplifier.

Preferably, the first filter circuit is a fourth-order active low-pass filter circuit;

the second filter circuit is a fourth-order program-controlled active band-pass filter circuit;

the third filter circuit is a fourth-order program-controlled active high-pass filter circuit.

Preferably, the transmitting circuit is: and a transmitting circuit for converting the received electric signal into a sound signal and transmitting the sound signal.

Preferably, the first detection circuit includes a first pre-stage circuit for detecting a ground wave, and a first range selection circuit connected to the first pre-stage circuit and the first filter circuit, respectively;

the second detection circuit comprises a second pre-stage circuit for detecting ultrasonic waves and a second gear selection circuit which is respectively connected with the second pre-stage circuit and the second filter circuit;

the third detection circuit comprises a third preceding stage circuit for detecting high-frequency waves and a third gear selection circuit which is respectively connected with the third preceding stage circuit and the third filter circuit;

still include in the integration detection processing circuit of signal is put in cubical switchboard office: the first analog-to-digital conversion circuit, the second analog-to-digital conversion circuit and the third analog-to-digital conversion circuit are sequentially connected with the first filter circuit, the second filter circuit and the third filter circuit;

the controller is connected with the first analog-to-digital conversion circuit, the second analog-to-digital conversion circuit, the third analog-to-digital conversion circuit, the first gear selection circuit, the second gear selection circuit and the third gear selection circuit, and is used for selecting a gear of the first gear selection circuit according to an output signal of the first analog-to-digital conversion circuit, selecting a gear of the second gear selection circuit according to an output signal of the second analog-to-digital conversion circuit, and selecting a gear of the third gear selection circuit according to an output signal of the third analog-to-digital conversion circuit;

the first gear selection circuit, the second gear selection circuit and the third gear selection circuit are gear selection circuits at least comprising 2 gears, and circuit equivalent resistances of the gear selection circuits under different gears are different for any one gear selection circuit.

Preferably, the first gear selection circuit includes: the first relay, the second relay, the first triode, the second triode, the sixth resistor, the seventh resistor and the eighth resistor;

a first control pin of the first relay receives a high level signal, and a second control pin of the first relay is connected with a collector electrode of the first triode; the input end of a first controlled branch of the first relay is used for receiving earth electric wave signals detected by the first preceding stage circuit, and the output end of the first controlled branch of the first relay is connected with the first end of a sixth resistor; the input end of a second controlled branch of the first relay is used for receiving earth electric wave signals detected by the first preceding stage circuit, and the output end of the second controlled branch of the first relay is connected with the first end of a seventh resistor;

a first control pin of the second relay receives a high level signal, and a second control pin of the second relay is connected with a collector electrode of a second triode; the input end of a first controlled branch of the second relay is used for receiving earth electric wave signals detected by the first preceding stage circuit, and the output end of the first controlled branch of the second relay is connected with the first end of an eighth resistor; the input end of a second controlled branch of the second relay is used for receiving earth electric wave signals detected by the first preceding stage circuit, and the output end of the second controlled branch of the second relay is suspended;

the emitting electrode of the first triode is grounded, and the base electrode of the first triode is connected with the controller; the emitter of the second triode is grounded, and the base of the second triode is connected with the controller; and the second end of the sixth resistor, the second end of the seventh resistor and the second end of the eighth resistor are connected with each other and used as the output end of the first gear selection circuit.

Preferably, the first gear selection circuit further includes:

the cathode of the first diode is connected with a first control pin of the first relay, and the anode of the first diode is connected with a second control pin of the first relay;

the first end of the first capacitor is connected with the second end of the ninth resistor, and the second end of the first capacitor is connected with the anode of the first diode;

the ninth resistor with a first end connected with the cathode of the first diode;

the first end of the tenth resistor is connected with the base electrode of the first triode, and the second end of the tenth resistor is connected with the emitting electrode of the first triode;

the cathode of the second diode is connected with the first control pin of the second relay, and the anode of the second diode is connected with the second control pin of the second relay;

the first end of the second capacitor is connected with the second end of the eleventh resistor, and the second end of the second capacitor is connected with the anode of the second diode;

the eleventh resistor with a first end connected with the cathode of the second diode;

and the twelfth resistor is connected with the base electrode of the second triode at the first end and the emitter electrode of the second triode at the second end.

In the scheme of this application, consider in practical application, the frequency of partial discharge signal under the different occasions is different, consequently, this application detects earth's electric wave through first detection circuitry, and simultaneously, detect the ultrasonic wave through second detection circuitry, and detect the high frequency wave through third detection circuitry, after summation amplifier circuit carries out signal fusion, the signal transmission after will fusing is to receiving arrangement through transmitting circuit again, make the scheme of this application can be based on the ground electric wave, ultrasonic wave and high frequency wave carry out the integrated analysis of partial discharge signal. Therefore, even if the frequency of the partial discharge signal changes in different scenes, the acquisition and analysis of the partial discharge signal are simultaneously carried out on the earth electric wave, the ultrasonic wave and the high-frequency wave, so that the method can effectively adapt to complex actual scenes, and the situation that an accurate analysis result cannot be obtained due to the fact that a single detection method is adopted in the traditional scheme is avoided. Therefore, the scheme of the application can effectively detect and process the partial discharge signal, and is beneficial to obtaining a more accurate signal analysis result.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a fusion detection processing circuit for partial discharge signals of a switch cabinet according to the present invention;

fig. 2a is a schematic circuit diagram of a first analog-to-digital conversion circuit according to an embodiment of the present invention;

fig. 2b is a schematic circuit diagram of a second analog-to-digital conversion circuit according to an embodiment of the present invention;

fig. 2c is a schematic circuit diagram of a second analog-to-digital conversion circuit according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of a first gear selection circuit according to an embodiment of the present invention;

fig. 4a is a schematic circuit diagram of a fourth-order active low-pass filter circuit according to an embodiment of the present invention;

fig. 4b is a schematic circuit diagram of a fourth-order program-controlled active band-pass filter circuit according to an embodiment of the present invention;

fig. 4c is a schematic circuit structure diagram of a fourth-order program-controlled active high-pass filter circuit according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of an analog switch circuit according to an embodiment of the present invention;

fig. 6 is a schematic circuit diagram of a summing amplifier circuit according to an embodiment of the present invention.

Detailed Description

The core of the utility model is to provide a signal's integration detection and processing circuit is put in cubical switchboard office, can carry out the office effectively and put the detection and the processing of signal, be favorable to obtaining more accurate signal analysis result.

In order to make the technical field better understand the solution of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings and the detailed description. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a fusion detection processing circuit for a switch cabinet partial discharge signal according to the present invention, where the fusion detection processing circuit for the switch cabinet partial discharge signal may include:

a first detection circuit 11 for detecting a ground wave, a second detection circuit 12 for detecting an ultrasonic wave, and a third detection circuit 13 for detecting a high-frequency wave.

A first filter circuit 21, a second filter circuit 22, and a third filter circuit 23 connected to the first detection circuit 11, the second detection circuit 12, and the third detection circuit 13 in this order;

a summing and amplifying circuit 30 connected to the first filter circuit 21, the second filter circuit 22, and the third filter circuit 23, respectively, for performing signal superposition amplification;

a transmitting circuit 40 connected to the summing amplifier circuit 30 for signal transmission;

receiving means 50 for receiving the signal transmitted by the transmitting circuit 40.

Specifically, the specific circuit configurations of the first detection circuit 11, the second detection circuit 12, and the third detection circuit 13 may be set and adjusted according to actual needs, and the corresponding functions of the detection circuits may be adaptively completed. Further, in an embodiment of the present invention, in consideration of practical applications, the amplitude of the partial discharge signal may change except for the frequency, so that the circuit of the present application can be more effectively adapted to complex practical scenarios, in this embodiment, the first detection circuit 11 may include a first pre-stage circuit for detecting the ground electric wave, and a first gear selection circuit connected to the first pre-stage circuit and the first filter circuit 21, respectively;

correspondingly, the second detection circuit 12 includes a second pre-stage circuit for detecting ultrasonic waves, and a second gear selection circuit respectively connected to the second pre-stage circuit and the second filter circuit 22;

the third detection circuit 13 may include a third preceding circuit for detecting a high frequency wave, and a third stage selection circuit connected to the third preceding circuit and the third filter circuit 23, respectively.

The first gear selection circuit, the second gear selection circuit and the third gear selection circuit are all gear selection circuits at least comprising 2 gears, and aiming at any one gear selection circuit, the circuit equivalent resistances of the gear selection circuit under different gears are different.

The fusion detection processing circuit for the partial discharge signals of the switch cabinet in this embodiment further includes: a first analog-to-digital conversion circuit, a second analog-to-digital conversion circuit and a third analog-to-digital conversion circuit which are connected with the first filter circuit 21, the second filter circuit 22 and the third filter circuit 23 in sequence;

the controller is connected with the first analog-to-digital conversion circuit, the second analog-to-digital conversion circuit, the third analog-to-digital conversion circuit, the first gear selection circuit, the second gear selection circuit and the third gear selection circuit and is used for selecting the gear of the first gear selection circuit according to an output signal of the first analog-to-digital conversion circuit, selecting the gear of the second gear selection circuit according to an output signal of the second analog-to-digital conversion circuit and selecting the gear of the third gear selection circuit according to an output signal of the third analog-to-digital conversion circuit.

The circuit composition of the first analog-to-digital conversion circuit, the second analog-to-digital conversion circuit and the third analog-to-digital conversion circuit can be set and adjusted according to actual needs. For example, fig. 2a, fig. 2b and fig. 2c sequentially show circuit structures of a first analog-to-digital conversion circuit, a second analog-to-digital conversion circuit and a third analog-to-digital conversion circuit in an embodiment. In fig. 2a, 2b and 2c, the network labels OUT _1, OUT _2 and OUT _3 sequentially indicate the output signals of the first filter circuit 21, the second filter circuit 22 and the third filter circuit 23, and the SDO1, the SDO2 and the SDO3 sequentially indicate the output signals of the first analog-to-digital conversion circuit, the second analog-to-digital conversion circuit and the third analog-to-digital conversion circuit, which need to be output to the controller.

The controller may be generally selected as a DSP controller, and may select the gear of the first gear selection circuit based on the output signal of the first analog-to-digital conversion circuit. For example, when the controller determines that the amplitude of the signal output from the first filter circuit 21 belongs to the interval [0, a ], the first gear selection circuit is controlled to be in the first gear, when the controller determines that the amplitude of the signal output from the first filter circuit 21 belongs to the interval (a, b ], the first gear selection circuit is controlled to be in the second gear, when the controller determines that the amplitude of the signal output from the first filter circuit 21 belongs to the interval (b, + ∞ ], the first gear selection circuit is controlled to be in the third gear. Or different circuits, can realize respective functions, and does not influence the implementation of the utility model.

Because the controller in this embodiment can adjust the gears of the first gear selection circuit, the second gear selection circuit and the third gear selection circuit, and the circuit equivalent resistances of the gear selection circuits under different gears are different for any one gear selection circuit, when the amplitude of the local amplifier signal changes, the scheme of the present application can adaptively adjust the range according to the amplitude change, that is, adjust the equivalent resistance of each gear selection circuit, so that the circuit of the present application can be effectively applied to a complex actual scene.

In a specific embodiment of the present invention, referring to fig. 3, the first gear selecting circuit includes: a first relay K1, a second relay K2, a first triode Q1, a second triode Q2, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8;

a first control pin of the first relay K1 receives a high level signal, and a second control pin of the first relay K1 is connected with a collector electrode of a first triode Q1; the input end of a first controlled branch of the first relay K1 is used for receiving a ground electric wave signal detected by a first front-stage circuit, and the output end of the first controlled branch of the first relay K1 is connected with the first end of a sixth resistor R6; the input end of a second controlled branch of the first relay K1 is used for receiving a ground electric wave signal detected by the first front-stage circuit, and the output end of the second controlled branch of the first relay K1 is connected with the first end of a seventh resistor R7;

a first control pin of the second relay K2 receives a high level signal, and a second control pin of the second relay K2 is connected with a collector electrode of a second triode Q2; the input end of a first controlled branch of the second relay K2 is used for receiving a ground electric wave signal detected by the first front-stage circuit, and the output end of the first controlled branch of the second relay K2 is connected with the first end of an eighth resistor R8; the input end of a second controlled branch of the second relay K2 is used for receiving a ground electric wave signal detected by the first front-stage circuit, and the output end of the second controlled branch of the second relay K2 is suspended;

the emitter of the first triode Q1 is grounded, and the base of the first triode Q1 is connected with the controller; the emitter of the second triode Q2 is grounded, and the base of the second triode Q2 is connected with the controller; the second terminal of the sixth resistor R6, the second terminal of the seventh resistor R7, and the second terminal of the eighth resistor R8 are all connected to each other and serve as the output terminal of the first gear selection circuit.

In the embodiment of fig. 3, gear selection is achieved based on the first relay K1 and the second relay K2. In fig. 3, the first control pin of the first relay K1 is labeled as 1, and receives a high signal, i.e., STM _ VCC in fig. 3. A second control pin of the first relay K1, labeled 10, is connected to the collector of the first transistor Q1. The first controlled branch of the first relay K1 is a first controlled branch composed of four pins, i.e., a pin 2, a pin 3, a pin 8, and a pin 9, and the pin 3 and the pin 8 are connected to each other as an input terminal of the first controlled branch, and receive a ground electric wave signal detected by the first previous stage circuit, which is denoted by a network reference VPP _ IN 1. The output end of the first controlled branch of the first relay K1 is connected to the first end of the sixth resistor R6. The second controlled branch of the first relay K1 is a controlled branch composed of four pins, i.e., a pin 4, a pin 3, a pin 8 and a pin 7, the pin 3 and the pin 8 are connected to serve as an input terminal of the second controlled branch of the first relay K1 for receiving the ground electric wave signal detected by the first front-stage circuit, and an output terminal of the second controlled branch of the first relay K1 is connected to the first terminal of the seventh resistor R7.

The branch of the second relay K2 is connected in parallel with the branch of the first relay K1, and the circuit structure is the same, so the description is not repeated. As can be seen from the circuit connection relationship in fig. 3, the controller can control whether the first control pin of the first relay K1 and the second control pin of the first relay K1 are connected or not by controlling the connection and disconnection of the first transistor Q1, so as to control whether the resistance value of the branch in which the first relay K1 is located is equal to R6 or R7. And it is noted that the controller is not shown in fig. 3.

Since the branch of the second relay K2 is connected in parallel with the branch of the first relay K1, in this embodiment, the equivalent resistance of the first gear selection circuit can take four values, one of which is equal to R6, the other is equal to R7, the other is equal to the parallel equivalent resistance of R6 and R8, and the fourth is equal to the parallel equivalent resistance of R7 and R8.

In the embodiment, gear selection is realized based on the first relay K1 and the second relay K2, the circuit is simple in structure and high in reliability, four gears are selected through the parallel connection of the branch where the second relay K2 is located and the branch where the first relay K1 is located, the number of the gears is large, and actual requirements can be met.

In the embodiment of fig. 3, the first gear selection circuit is taken as an example to explain the specific circuit configuration of the first gear selection circuit, and the specific circuit configurations of the second gear selection circuit and the third gear selection circuit may be the same as or different from this, and may implement the corresponding functions. Of course, if the circuits are configured identically, the models of the related devices may also need to be adjusted accordingly, for example, the resistance values of the respective resistors need to be adjusted accordingly.

Further, in an embodiment of the present invention, the first gear selecting circuit further includes:

a first diode D1 having a cathode connected to a first control pin of the first relay K1 and an anode connected to a second control pin of the first relay K1;

a first capacitor C1 having a first terminal connected to a second terminal of the ninth resistor R9 and a second terminal connected to an anode of the first diode D1;

a ninth resistor R9 having a first terminal connected to the cathode of the first diode D1;

a tenth resistor R10 having a first end connected to the base of the first transistor Q1 and a second end connected to the emitter of the first transistor Q1;

a second diode D2 having a cathode connected to the first control pin of the second relay K2 and an anode connected to the second control pin of the second relay K2;

a second capacitor C2 having a first terminal connected to the second terminal of the eleventh resistor R11 and a second terminal connected to the anode of the second diode D2;

an eleventh resistor R11 having a first terminal connected to the cathode of the second diode D2;

and the twelfth resistor R12 is connected with the base electrode of the second triode Q2 at the first end and the emitter electrode of the second triode Q2 at the second end.

Referring to fig. 3, the first capacitor C1 is arranged, so that the stability of voltage is guaranteed, and the situation that the on-off of two controlled branches of the first relay K1 is frequently switched when STM _ VCC is unstable is avoided. The second capacitor C2 functions in the same way. The tenth resistor R10 can avoid the mis-conduction of the first transistor Q1, that is, when the base of the first transistor Q1 does not receive the high level signal sent by the controller, the base is grounded through the tenth resistor R10, so the mis-conduction is not easy to occur, and the function of the twelfth resistor R12 is the same as that.

In addition, in the embodiment of fig. 3, a current limiting resistor R13 is further provided between the first transistor Q1 and the controller, and a current limiting resistor R14 is provided between the second transistor Q2 and the controller. TS1 is a magnetic bead disposed between the first pre-stage circuit and the first gear selection circuit, and plays the role of isolation, and is equivalent to a 0 Ω resistor. The specific structure of the first pre-stage circuit is not shown in fig. 3, and the related sensor and the related circuit structure may be referred to the existing design.

The first filter circuit 21 is connected with the first detection circuit 11, the second filter circuit 22 is connected with the second detection circuit 12, the third filter circuit 23 is connected with the third detection circuit 13, and the specific circuit composition of the first filter circuit 21, the second filter circuit 22 and the third filter circuit 23 can be set and adjusted according to requirements.

For example, in an embodiment of the present invention, the first filter circuit 21 is a fourth-order active low-pass filter circuit, which can effectively filter out high-frequency interference signals in the ground waves. The second filter circuit 22 is a fourth-order program-controlled active band-pass filter circuit, which can effectively filter out interference signals in the ultrasonic signals. The third filter circuit 23 is a fourth-order program-controlled active high-pass filter circuit, which can effectively filter low-frequency interference signals in high-frequency waves.

It should be noted that the ground wave in the present application generally refers to a signal with a frequency of 10MHz or less, while the ultrasonic wave in the present application generally refers to a signal with a frequency of 20KHz to 40KHz, and the high frequency wave generally refers to a signal with a frequency of 100KHz or more.

The specific circuit composition of the fourth-order active low-pass filter circuit, the fourth-order program-controlled active band-pass filter circuit and the fourth-order program-controlled active high-pass filter circuit can be adjusted according to actual needs. For example, fig. 4a discloses a fourth-order active low-pass filter circuit in a specific case, the device types in fig. 4a may also be set and adjusted as needed, for example, four operational amplifiers may be selected as ADA 4857. Furthermore, the method is simple. The network reference VPP _ OUT1 in fig. 4a may represent the output signal of the first detection circuit 11, and the network reference OUT _1 may represent the output signal of the first filter circuit 21. Accordingly, the network reference VPP _ OUT2 in fig. 4b may represent the output signal of the second detection circuit 12, and the network reference OUT _2 may represent the output signal of the second filter circuit 22. The network reference VPP _ OUT3 in fig. 4c may represent the output signal of the third detection circuit 13, and the network reference OUT _3 may represent the output signal of the third filter circuit 23.

The summing amplifier 30 is connected to the first filter circuit 21, the second filter circuit 22, and the third filter circuit 23, respectively, and can perform signal superposition amplification.

Further, in an embodiment of the present invention, a switch circuit may be further provided between each of the filter circuits and the summing and amplifying circuit 30, so that the kind of the signal to be superimposed may be freely selected.

That is, in a specific embodiment of the present invention, the present invention may further include: and the analog switch circuits are respectively connected with the first filter circuit 21, the second filter circuit 22, the third filter circuit 23 and the summing and amplifying circuit 30, and are used for receiving the selection signals and outputting each signal which is in accordance with the selection signals in the received output signals of the three filter circuits to the summing and amplifying circuit 30.

The specific circuit configuration of the analog switch circuit can be set and selected as required, for example, in the embodiment of fig. 5, the analog switch circuit specifically includes a first multi-way analog switch chip U11;

a first input terminal of the first multi-way analog switch chip U11 is connected to an output terminal of the first filter circuit 21, as indicated by the net reference OUT _ 1. A first output terminal of the first multi-path analog switch chip U11 is connected to a first input terminal of the summing amplifier circuit 30, as indicated by the network reference VOUT _ 1; when the first control terminal of the first multi-way analog switch chip U11 receives the first control signal, the first output terminal of the first multi-way analog switch chip U11 is conducted with the first input terminal of the first multi-way analog switch chip U11.

A second input terminal of the first multi-path analog switch chip U11 is connected to the output terminal of the second filter circuit 22, as indicated by the net reference character OUT _2, and a second output terminal of the first multi-path analog switch chip U11 is connected to a second input terminal of the summing and amplifying circuit 30, as indicated by the net reference character VOUT _ 2; when the second control end of the first multi-path analog switch chip U11 receives a second control signal, the second output end of the first multi-path analog switch chip U11 is conducted with the second input end of the first multi-path analog switch chip U11;

a third input terminal of the first multi-path analog switch chip U11 is connected to the output terminal of the third filter circuit 23, which is denoted by a net reference character OUT _3, and a third output terminal of the first multi-path analog switch chip U11 is connected to a third input terminal of the summing and amplifying circuit 30, which is denoted by a net reference character VOUT _ 3; when the third control terminal of the first multi-path analog switch chip U11 receives the third control signal, the third output terminal of the first multi-path analog switch chip U11 is connected to the third input terminal of the first multi-path analog switch chip U11.

For example, in fig. 5, when the pin of the network tag GPIO0 is at a high level, the first control terminal of the first multi-way analog switch chip U11 receives the first control signal, and at this time, the first output terminal of the first multi-way analog switch chip U11 and the first input terminal of the first multi-way analog switch chip U11 are turned on, that is, the summing and amplifying circuit 30 can receive the ground electric wave signal. Correspondingly, when the pin of the network reference GPIO0 is a low-level signal, the first output terminal of the first multi-path analog switch chip U11 and the first input terminal of the first multi-path analog switch chip U11 are not turned on, that is, the summing and amplifying circuit 30 cannot receive the ground wave signal. Of course, in this example, when the pin at which the GPIO0 is located is at a high level, the first output terminal of the first multi-channel analog switch chip U11 is connected to the first input terminal of the first multi-channel analog switch chip U11, and in other situations, the connection may be controlled at a low level, which does not affect the implementation of the present invention. And the pin of the GPIO0 can be controlled by the relevant controller to control the level state.

GPIO1 and GPIO2 are used to control whether the summing amplifier circuit 30 can receive an ultrasonic signal and whether a high-frequency signal can be received, respectively, similarly to GPIO 0. The model of the first multi-channel analog switch chip U11 in fig. 5 is CD4066B, and in other cases, it can be adjusted appropriately as needed.

The analog switch circuit in the embodiment is realized by the first multi-path analog switch chip U11, and the circuit is simple and convenient to implement.

In an embodiment of the present invention, referring to fig. 6, the summing and amplifying circuit 30 includes:

a first resistor R1 having a first terminal as a first input terminal of the summing and amplifying circuit 30 and a second terminal connected to an inverting input terminal of the first operational amplifier OP 1;

a second resistor R2 having a first terminal serving as a second input terminal of the summing and amplifying circuit 30 and a second terminal connected to an inverting input terminal of the first OP 1;

a third resistor R3 having a first terminal serving as a third input terminal of the summing and amplifying circuit 30 and a second terminal connected to an inverting input terminal of the first OP 1;

the non-inverting input end of the first operational amplifier OP1 is connected with the second end of the fourth resistor R4, and the output end of the first operational amplifier OP1 is used as the output end of the summing and amplifying circuit 30;

a fourth resistor R4 with a first end connected to ground;

a fifth resistor R5 having a first terminal connected to the inverting input terminal of the first operational amplifier OP1 and a second terminal connected to the output terminal of the first operational amplifier OP 1.

In fig. 6, the types of the respective devices can be set and adjusted as needed, for example, the first operational amplifier OP1 can be an LTC6228 operational amplifier, and the circuit configuration of the summing and amplifying circuit 30 in fig. 6 is simple and convenient to implement.

The transmitting circuit 40 needs to transmit the signal output by the summing and amplifying circuit 30 to the receiving device 50, and after the receiving device 50 receives the signal transmitted by the transmitting circuit 40, the analysis and processing of the signal can be performed. In a specific embodiment of the present invention, the transmitting circuit 40 is: and a transmitting circuit 40 for converting the received electric signal into a sound signal and transmitting the sound signal. The received electric signals are converted into sound signals to be transmitted, so that the isolation between the superior circuit and the inferior circuit is favorably realized, the interference caused by the signals in the transmission process is favorably reduced, and the accuracy of the subsequent signal analysis result is favorably improved. The specific circuit structure of the transmitting circuit 40 and the receiving device 50 can be set and selected according to the requirement.

In the scheme of this application, in consideration of in practical application, the frequency of partial discharge signal under different occasions is different, therefore, this application detects earth electric wave through first detection circuitry 11, simultaneously, detects the ultrasonic wave through second detection circuitry 12, and detect high frequency wave through third detection circuitry 13, after summing amplifier circuit 30 carries out signal fusion, the signal after will fusing is sent to receiving arrangement 50 through transmitting circuit 40 again, make the scheme of this application can be based on earth electric wave, ultrasonic wave and high frequency wave carry out the integrated analysis of partial discharge signal. Therefore, even if the frequency of the partial discharge signal changes in different scenes, the acquisition and analysis of the partial discharge signal are simultaneously carried out on the earth electric wave, the ultrasonic wave and the high-frequency wave, so that the method can effectively adapt to complex actual scenes, and the situation that an accurate analysis result cannot be obtained due to the fact that a single detection method is adopted in the traditional scheme is avoided. Therefore, the scheme of the application can effectively detect and process the partial discharge signal, and is beneficial to obtaining a more accurate signal analysis result.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, article, or apparatus that comprises the element.

The principle and the implementation of the present invention are explained herein by applying specific examples, and the above descriptions of the embodiments are only used to help understand the technical solution and the core idea of the present invention. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, the present invention can be further modified and modified, and such modifications and modifications also fall within the protection scope of the appended claims.

Claims

1. A fusion detection processing circuit of a partial discharge signal of a switch cabinet is characterized by comprising:

2. The circuit for detecting and processing fusion of partial discharge signals of a switch cabinet according to claim 1, further comprising: and the analog switch circuits are respectively connected with the first filter circuit, the second filter circuit, the third filter circuit and the summing and amplifying circuit and are used for receiving selection signals and outputting each signal which accords with the selection signals in the received output signals of the three filter circuits to the summing and amplifying circuit.

3. The circuit for detecting and processing the fusion of the partial discharge signals of the switch cabinet according to claim 2, wherein the analog switch circuit comprises a first multi-path analog switch chip;

4. The circuit for detecting and processing fusion of partial discharge signals of a switch cabinet according to claim 3, wherein the summing and amplifying circuit comprises:

the fourth resistor with the first end grounded;

5. The circuit for detecting and processing the fusion of the partial discharge signals of the switch cabinet according to claim 1, wherein the first filter circuit is a fourth-order active low-pass filter circuit;

6. The circuit for detecting and processing fusion of partial discharge signals of a switch cabinet according to claim 1, wherein the transmitting circuit is: and a transmitting circuit for converting the received electric signal into a sound signal and transmitting the sound signal.

7. The circuit for detecting and processing fusion of partial discharge signals of a switch cabinet according to any one of claims 1 to 6, wherein the first detection circuit comprises a first pre-stage circuit for detecting ground waves, and a first gear selection circuit connected to the first pre-stage circuit and the first filter circuit, respectively;

8. The circuit for detecting and processing fusion of partial discharge signals of a switch cabinet according to claim 7, wherein the first gear selection circuit comprises: the first relay, the second relay, the first triode, the second triode, the sixth resistor, the seventh resistor and the eighth resistor;

9. The circuit for detecting and processing fusion of partial discharge signals of a switch cabinet according to claim 8, wherein the first gear selection circuit further comprises: