CN211554173U - Three-level topology inverter circuit power device detection circuit - Google Patents
Three-level topology inverter circuit power device detection circuit Download PDFInfo
- Publication number
- CN211554173U CN211554173U CN201922207454.7U CN201922207454U CN211554173U CN 211554173 U CN211554173 U CN 211554173U CN 201922207454 U CN201922207454 U CN 201922207454U CN 211554173 U CN211554173 U CN 211554173U
- Authority
- CN
- China
- Prior art keywords
- resistor
- diode
- operational amplifier
- inverter circuit
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Inverter Devices (AREA)
Abstract
A three-level topological inverter circuit power device detection circuit comprises: when the detection circuit judges that the voltage output value is within a preset voltage range, the detection circuit controls the two insulated gate bipolar transistors to have different level signals, and when the reset signal is at a preset logic level, the power device of the three-level topology inverter circuit is abnormal. The utility model provides the high reliability and the security of product, and can realize effectual protection, it is easy and simple to handle.
Description
Technical Field
The utility model belongs to the technical field of inverter circuit detection circuitry, concretely relates to topology inverter circuit power device detection circuitry of three levels.
Background
In the field of power electronic application, a three-level topology inverter circuit is generally used to implement an inverter function, and a common three-level topology inverter circuit is shown in fig. 1 and 2, where fig. 1 is a T-type three-level inverter topology diagram and fig. 2 is an I-type three-level inverter topology diagram. Due to the introduction of the point loop in the topology, the BUS capacitor is generally designed by connecting positive and negative BUS in series. When a single-point fault occurs to a power device in a midpoint loop, if reliable detection protection is not available, half bridge arms are easily caused to be in short circuit, so that a single-side BUS is enabled to be in short circuit, and a BUS capacitor is easily damaged by overvoltage or even is in fire. Particularly in PV-inverter applications, since the dc side of PV is generally free of short-circuit protection fuse or open-circuit control, the constant superimposition of PV energy at the short-circuit point can have serious consequences.
The existing inverter circuit power device has no hardware detection and protection circuit, so that the risk is high; if the IGBT short-circuit current is used for protection, a special driving chip is needed, and the cost is high; parameters need to be corrected for different IGBTs, and expansibility is poor.
SUMMERY OF THE UTILITY MODEL
In order to solve the above problem, the utility model provides a three-level topology inverter circuit power device detection circuitry, a serial communication port, include:
the three-level topological inverter circuit is used for realizing the inversion of the circuit; the three-level topology inverter circuit comprises two insulated gate bipolar transistors and a voltage output end, wherein each insulated gate bipolar transistor is correspondingly connected with a level signal for controlling the insulated gate bipolar transistor;
the detection circuit is used for detecting two level signals for controlling the two insulated gate bipolar transistors and judging whether the voltage output value of the voltage output end is within a preset voltage range or not; the detection circuit is respectively connected with two level signals for controlling the two insulated gate bipolar transistors;
the sampling circuit is used for sampling the voltage output value of the three-level topology inverter circuit; the sampling circuit is connected with the voltage output end;
when the detection circuit judges that the voltage output value is within a preset voltage range, the level signals of the two insulated gate bipolar transistors are controlled to be different, and when a reset signal is at a preset logic level, a power device of the three-level topology inverter circuit is abnormal.
Preferably, the three-level topology inverter circuit includes a T-type three-level topology inverter circuit or an I-type three-level topology inverter circuit.
Preferably, the detection circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a first operational amplifier, a second operational amplifier, a triode, and a first capacitor, a first end of the first resistor is connected to an upper limit voltage bit of the preset voltage range and a second end of the first resistor is connected to a positive input terminal of the first operational amplifier, a first end of the second resistor is connected to a negative input terminal of the first operational amplifier and a second end of the second resistor is connected to the voltage output terminal of the three-level topology inverter circuit, a first end of the third resistor is connected to a positive input terminal of the first operational amplifier and a second end of the third resistor is connected to an output terminal of the first operational amplifier, a first end of the fourth resistor is connected to an output end of the first operational amplifier and a second end is connected to a cathode of the first diode, a first end of the fifth resistor is connected to an anode of the first diode and a second end is connected to a first preset positive potential, a first end of the sixth resistor is connected to the voltage output end and a second end is connected to a positive input end of the second operational amplifier, a first end of the seventh resistor is connected to a lower limit voltage of the preset voltage range and a second end is connected to a negative input end of the second operational amplifier, a first end of the eighth resistor is connected to a positive input end of the second operational amplifier and a second end is connected to an output end of the second operational amplifier, a first end of the ninth resistor is connected to an output end of the second operational amplifier and a second end is connected to a cathode of the second diode, a first end of the tenth resistor is connected with a second preset positive potential, a second end of the eleventh resistor is connected with the anode of the third diode, a first end of the eleventh resistor is connected with the anode of the third diode, a second end of the eleventh resistor is connected with the base of the triode, a first end of the twelfth resistor is connected with the base of the triode, a second end of the twelfth resistor is grounded, the anode of the first diode, the anode of the second diode, the anode of the fifth diode and the anode of the sixth diode are all connected with a fault signal output end, the cathode of the third diode is connected with a first insulated gate bipolar transistor in the three-level topological inverter circuit, the anode of the fourth diode is connected with the anode of the third diode, the cathode of the fourth diode is connected with a fourth insulated gate bipolar transistor in the three-level topological inverter circuit, and the cathode of the fifth diode is connected with a Reset signal end of the detection circuit, the cathode of the sixth resistor is connected with the collector of the triode, the emitter of the triode is grounded, the anode of the first capacitor is connected with the base of the triode, and the cathode of the first capacitor is grounded.
Preferably, the first preset positive potential and the second preset positive potential are both 3.3V.
Preferably, the sampling circuit includes a first resistor string, an eighteenth resistor, a nineteenth resistor, a second resistor string, a twenty-fifth resistor, a second capacitor, a third capacitor, a fourth capacitor and a third operational amplifier, a first end of the first resistor string is connected to the L _ a terminal of the three-level topology inverter circuit and a second end is connected to the positive input terminal of the third operational amplifier, a first end of the eighteenth resistor is connected to the positive input terminal of the third operational amplifier and a second end is connected to the output terminal of the third operational amplifier, a first end of the nineteenth resistor string is connected to the output terminal of the third operational amplifier and a second end is connected to the voltage output terminal of the three-level topology inverter circuit, a first end of the second resistor string is connected to the Bus _ N terminal of the three-level topology inverter circuit and a second end is connected to the negative input terminal of the third operational amplifier, the first end of the twenty-fifth resistor is connected with the negative input end of the third operational amplifier, the second end of the twenty-fifth resistor is connected with a third preset positive potential, the second capacitor is connected with the eighteenth resistor in parallel, the third capacitor is connected with the twenty-fifth resistor in parallel, the first end of the fourth capacitor is connected with the voltage output end, and the second end of the fourth capacitor is grounded.
Preferably, the third preset positive potential is 6V.
Preferably, the first resistor string includes one or more of a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor and a seventeenth resistor connected in series in sequence.
Preferably, the second resistor string includes one or more of a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor and a twenty-fourth resistor connected in series in sequence.
Compared with the prior art, utility model's beneficial effect does:
(1) the reliability and the safety of the product are improved, effective protection can be realized, and the operation is simple and convenient;
(2) judging whether the power device is abnormal or not by detecting the midpoint potential in switch-by-switch cycles; meanwhile, the related reset circuit is assisted, and the detection precision is improved by a delay circuit; and timely protection is carried out by a software or hardware method by utilizing the detected abnormal signal.
Drawings
For ease of illustration, the invention is described in detail by the following detailed description and accompanying drawings.
FIG. 1 is a prior art T-type three-level inverter topology;
FIG. 2 is a prior art I-type three-level inverter topology;
fig. 3 is a schematic block diagram of a three-level topology inverter circuit power device detection circuit provided by the present invention;
fig. 4 is a circuit diagram of a detection circuit in the power device detection circuit of the three-level topology inverter circuit provided by the present invention;
fig. 5 is a circuit diagram of a sampling circuit in a detection circuit of a three-level topology inverter circuit power device provided by the present invention;
fig. 6 is a logic diagram of a three-level topology inverter circuit power device detection circuit provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described below with reference to specific embodiments shown in the accompanying drawings. It should be understood that these descriptions are exemplary only, and are not intended to limit the scope of the invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
It should be noted that, in order to avoid obscuring the invention with unnecessary details, only the structures and/or processing steps closely related to the solution according to the invention are shown in the drawings, and other details not relevant to the invention are omitted.
Referring to fig. 3, in an embodiment of the present application, the present application provides a three-level topology inverter circuit power device detection circuit, including:
the three-level topological inverter circuit is used for realizing the inversion of the circuit; the three-level topology inverter circuit comprises two insulated gate bipolar transistors and a voltage output end, wherein each insulated gate bipolar transistor is correspondingly connected with a level signal for controlling the insulated gate bipolar transistor;
the detection circuit is used for detecting two level signals for controlling the two insulated gate bipolar transistors and judging whether the voltage output value of the voltage output end is within a preset voltage range or not; the detection circuit is respectively connected with two level signals for controlling the two insulated gate bipolar transistors;
the sampling circuit is used for sampling the voltage output value of the three-level topology inverter circuit; the sampling circuit is connected with the voltage output end;
when the detection circuit judges that the voltage output value is within a preset voltage range, the level signals of the two insulated gate bipolar transistors are controlled to be different, and when a reset signal is at a preset logic level, a power device of the three-level topology inverter circuit is abnormal.
Referring to fig. 1 and 2, in the embodiment of the present application, the three-level topology inverter circuit includes a T-type three-level topology inverter circuit (see fig. 1) or an I-type three-level topology inverter circuit (see fig. 2), and details of the components are not repeated here.
As shown in fig. 4, in the embodiment of the present application, the detection circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode, a first operational amplifier a1, a second operational amplifier a2, a transistor Q1, and a first capacitor C1, a first end of the first resistor R1 is connected to an upper limit voltage level (V _ H) of the predetermined voltage range, a second end of the first resistor R1 is connected to a positive input terminal of the first operational amplifier a1, a first end of the second resistor R2 is connected to a negative terminal of the first operational amplifier a1 and a negative terminal of the first operational amplifier R3634 is connected to a topological level (V _ H) of the first operational amplifier a topological output terminal of the first operational amplifier a topological circuit, a first terminal of the third resistor R3 is connected to the positive input terminal of the first operational amplifier a1 and a second terminal thereof is connected to the output terminal of the first operational amplifier a1, a first terminal of the fourth resistor R4 is connected to the output terminal of the first operational amplifier a1 and a second terminal thereof is connected to the cathode of the first diode D1, a first terminal of the fifth resistor R5 is connected to the anode of the first diode D1 and a second terminal thereof is connected to a first preset positive potential, a first terminal of the sixth resistor R6 is connected to the voltage output terminal (V _ smaple) and a second terminal thereof is connected to the positive input terminal of the second operational amplifier a2, a first terminal of the seventh resistor R7 is connected to the lower limit voltage level (V _ L) of the preset voltage range and a second terminal thereof is connected to the negative input terminal of the second operational amplifier a2, a first terminal of the eighth resistor R8 is connected to the positive input terminal of the second operational amplifier a2 and a second terminal thereof is connected to the second input terminal thereof An output terminal of an amplifier a2, a first terminal of the ninth resistor R9 is connected to an output terminal of the second operational amplifier a2 and a second terminal is connected to a cathode of the second diode D2, a first terminal of the tenth resistor R10 is connected to a second preset positive potential and a second terminal is connected to an anode of the third diode D3, a first terminal of the eleventh resistor R11 is connected to an anode of the third diode D3 and a second terminal is connected to a base of the transistor Q1, a first terminal of the twelfth resistor R12 is connected to a base of the transistor Q1 and a second terminal is grounded, an anode of the first diode D1, an anode of the second diode D2, an anode of the fifth diode D5 and an anode of the sixth diode are connected to a Fault signal output terminal (Fault _ R), a cathode of the third diode D3 is connected to a first insulated gate bipolar transistor (IGBT1) in the three-level topology inverter circuit, an anode of the fourth diode D4 is connected to an anode of the third diode D3, a cathode of the fourth diode D5 is connected to a fourth insulated gate bipolar transistor (IGBT4) in the three-level topology inverter circuit, a cathode of the fifth diode D5 is connected to a Reset signal terminal of the detection circuit, a cathode of the sixth resistor R6 is connected to a collector of the transistor Q1, an emitter of the transistor Q1 is grounded, and an anode of the first capacitor C1 is connected to a base of the transistor Q1, and a cathode of the first capacitor C1 is grounded.
In an embodiment of the present application, the first preset positive potential and the second preset positive potential are both 3.3V.
As shown in fig. 5, in the embodiment of the present application, the sampling circuit includes a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor 15, a sixteenth resistor 16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a third operational amplifier A3, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor 15, the sixteenth resistor 16 and the seventeenth resistor R17 are sequentially connected in series, the thirteenth resistor R13 is further connected to the L _ a terminal of the three-level topology inverter circuit, the seventeenth resistor R17 is further connected to the positive input terminal of the third operational amplifier R3, the eighteenth resistor R18 is connected to the positive input terminal of the third operational amplifier A3 An output terminal of the third operational amplifier A3, a first terminal of the nineteenth resistor R19 is connected to an output terminal of the third operational amplifier A3, a second terminal of the nineteenth resistor R19 is connected to the voltage output terminal (V _ smaple) of the three-level topology inverter circuit, the twentieth resistor R20, the twenty-first resistor R21, the twenty-second resistor R22, the twenty-third resistor R23, and the twenty-fourth resistor R24 are sequentially connected in series, the twentieth resistor R20 is further connected to a Bus _ N terminal of the three-level topology inverter circuit, the twenty-fourth resistor R24 is further connected to a negative input terminal of the third operational amplifier A3, a first terminal of the twenty-fifth resistor R25 is connected to a negative input terminal of the third operational amplifier A3, a second terminal of the twenty-fourth resistor R24 is connected to a third preset positive potential, the second capacitor C2 is connected to the eighteenth resistor R18 in parallel, and the third capacitor C3 is connected to the twenty-fifth resistor R25, the first end of the fourth capacitor C4 is connected to the voltage output terminal (V _ smaple) and the second end is grounded.
In the embodiment of the present application, the third preset positive potential is 6V.
As shown in fig. 6, the operation mode of the power device detection circuit of the three-level topology inverter circuit provided in the embodiment of the present application is as follows:
(1) when the inverter circuit works in the positive half cycle of the mains supply, the IGBT4 is closed, and the PWM4 signal is at a high level. When the IGBT1 is turned off, the signal PWM1 is at a high level, the triode Q1 is conducted at the moment, and a signal at a Fault signal output end (Fault _ R) of the detection circuit is at a low level, which indicates that no Fault signal exists; when the IGBT1 is switched on, the signal PWM1 is at a low level, the triode Q1 is cut off, the signal of the Fault signal output end (Fault _ R) of the detection circuit depends on the voltage value sampled by the sampling circuit, and if the sampling voltage is higher than the upper limit voltage V _ H, the signal of the Fault signal output end (Fault _ R) of the detection circuit is at a low level, which indicates that the power device normally works; if the sampling voltage is lower than the upper limit voltage V _ H and higher than the lower limit voltage V _ L, the Fault signal output end (Fault _ R) signal of the detection circuit is at a high level, which indicates that the power device is abnormal.
(2) When the inverter circuit works in the negative half cycle of the mains supply, the IGBT1 is closed, and the PWM1 signal is at a high level. When the IGBT4 is closed, the signal PWM4 is at a high level, the triode Q1 is conducted at the moment, and a signal at the Fault signal output end (Fault _ R) of the detection circuit is at a low level, which indicates that no Fault signal exists; when the IGBT4 is turned on, the signal PWM4 is low, and the transistor Q1 is turned off. The signal of the Fault signal output end (Fault _ R) of the detection circuit depends on the voltage value sampled by the sampling circuit, and if the sampling voltage is lower than the lower limit voltage V _ L, the signal of the Fault signal output end (Fault _ R) of the detection circuit is at a low level, which indicates that the power device normally works; if the sampling voltage is lower than the upper limit voltage V _ H and higher than the lower limit voltage V _ L, the Fault signal output end (Fault _ R) signal of the detection circuit is at a high level, which indicates that the power device works abnormally.
(3) When the detection circuit works in a Reset mode, the Reset signal is at a low level, and a Fault signal output end (Fault _ R) signal of the detection circuit is at a low level and has no Fault signal.
The truth table of this example is shown in the following table:
in the embodiment, in a three-level inversion topology (taking a T-type as an example), the middle point of a bridge arm generally has only 3 stable potentials, + BUS, N, -BUS; meanwhile, the three potentials depend on the on or off of the IGBT1 and the IGBT4 tube; if the power device is abnormal, the midpoint potential is certain to be abnormal when the IGBT1 and the IGBT4 are switched on; judging whether the power device is abnormal or not by detecting the midpoint potential in switch-by-switch cycles; meanwhile, related reset circuits are assisted for shielding some special working modes; the detection precision is improved by delaying the line, and the false triggering protection is avoided; and timely protection is carried out by a software or hardware method by utilizing the detected abnormal signal.
Compared with the prior art, utility model's beneficial effect does:
(1) the reliability and the safety of the product are improved, effective protection can be realized, and the operation is simple and convenient;
(2) judging whether the power device is abnormal or not by detecting the midpoint potential in switch-by-switch cycles; meanwhile, the related reset circuit is assisted, and the detection precision is improved by a delay circuit; and timely protection is carried out by a software or hardware method by utilizing the detected abnormal signal.
It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (8)
1. A three-level topology inverter circuit power device detection circuit is characterized by comprising:
the three-level topological inverter circuit is used for realizing the inversion of the circuit; the three-level topology inverter circuit comprises two insulated gate bipolar transistors and a voltage output end, wherein each insulated gate bipolar transistor is correspondingly connected with a level signal for controlling the insulated gate bipolar transistor;
the detection circuit is used for detecting two level signals for controlling the two insulated gate bipolar transistors and judging whether the voltage output value of the voltage output end is within a preset voltage range or not; the detection circuit is respectively connected with two level signals for controlling the two insulated gate bipolar transistors;
the sampling circuit is used for sampling the voltage output value of the three-level topology inverter circuit; the sampling circuit is connected with the voltage output end;
when the detection circuit judges that the voltage output value is within a preset voltage range, the level signals of the two insulated gate bipolar transistors are controlled to be different, and when a reset signal is at a preset logic level, a power device of the three-level topology inverter circuit is abnormal.
2. The three-level topology inverter circuit power device detection circuit of claim 1, wherein the three-level topology inverter circuit comprises a T-type three-level topology inverter circuit or an I-type three-level topology inverter circuit.
3. The power device detection circuit of claim 1, wherein the detection circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a first operational amplifier, a second operational amplifier, a triode, and a first capacitor, wherein a first end of the first resistor is connected to an upper voltage limit of the predetermined voltage range and a second end of the first resistor is connected to a positive input terminal of the first operational amplifier, a first end of the second resistor is connected to a negative input terminal of the first operational amplifier and a second end of the second resistor is connected to the voltage output terminal of the three-level topology inverter circuit, a first end of the third resistor is connected with the positive input end of the first operational amplifier and a second end is connected with the output end of the first operational amplifier, a first end of the fourth resistor is connected with the output end of the first operational amplifier and a second end is connected with the cathode of the first diode, a first end of the fifth resistor is connected with the anode of the first diode and a second end is connected with a first preset positive potential, a first end of the sixth resistor is connected with the voltage output end and a second end is connected with the positive input end of the second operational amplifier, a first end of the seventh resistor is connected with the lower limit voltage potential of the preset voltage range and a second end is connected with the negative input end of the second operational amplifier, a first end of the eighth resistor is connected with the positive input end of the second operational amplifier and a second end is connected with the output end of the second operational amplifier, a first end of the ninth resistor is connected to the output end of the second operational amplifier, a second end of the ninth resistor is connected to the cathode of the second diode, a first end of the tenth resistor is connected to a second preset positive potential, a second end of the tenth resistor is connected to the anode of the third diode, a first end of the eleventh resistor is connected to the anode of the third diode, a second end of the eleventh resistor is connected to the base of the triode, a first end of the twelfth resistor is connected to the base of the triode, a second end of the twelfth resistor is grounded, the anode of the first diode, the anode of the second diode, the anode of the fifth diode and the anode of the sixth diode are all connected to a fault signal output end, the cathode of the third diode is connected to the first insulated gate bipolar transistor in the three-level topology inverter circuit, the anode of the fourth diode is connected to the anode of the third diode, and the cathode of the fourth diode is connected to the fourth insulated gate bipolar transistor in the three-level topology inverter circuit The cathode of the fifth diode is connected with a Reset signal end of the detection circuit, the cathode of the sixth resistor is connected with the collector of the triode, the emitter of the triode is grounded, the anode of the first capacitor is connected with the base of the triode, and the cathode of the first capacitor is grounded.
4. The three-level topology inverter circuit power device detection circuit of claim 3, wherein the first predetermined positive potential and the second predetermined positive potential are both 3.3V.
5. The power device detection circuit of claim 1, wherein the sampling circuit comprises a first resistor string, an eighteenth resistor, a nineteenth resistor, a second resistor string, a twenty-fifth resistor, a second capacitor, a third capacitor, a fourth capacitor and a third operational amplifier, the first resistor string has a first end connected to the L _ a terminal of the three-level topological inverter circuit and a second end connected to the positive input terminal of the third operational amplifier, the eighteenth resistor has a first end connected to the positive input terminal of the third operational amplifier and a second end connected to the output terminal of the third operational amplifier, the nineteenth resistor has a first end connected to the output terminal of the third operational amplifier and a second end connected to the voltage output terminal of the three-level topological inverter circuit, the second resistor string has a first end connected to the Bus _ N terminal of the three-level topological inverter circuit and a second end connected to the Bus _ N terminal of the three-level topological inverter circuit The negative input end of the third operational amplifier is connected, the first end of the twenty-fifth resistor is connected with the negative input end of the third operational amplifier, the second end of the twenty-fifth resistor is connected with a third preset positive potential, the second capacitor is connected with the eighteenth resistor in parallel, the third capacitor is connected with the twenty-fifth resistor in parallel, the first end of the fourth capacitor is connected with the voltage output end, and the second end of the fourth capacitor is grounded.
6. The three-level topology inverter circuit power device detection circuit of claim 5, wherein the third predetermined positive potential is 6V.
7. The three-level topology inverter circuit power device detection circuit of claim 5, wherein the first resistor string comprises one or more of a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor and a seventeenth resistor connected in series in sequence.
8. The three-level topology inverter circuit power device detection circuit of claim 5, wherein the second resistor string comprises one or more of a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor and a twenty-fourth resistor connected in series in sequence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922207454.7U CN211554173U (en) | 2019-12-11 | 2019-12-11 | Three-level topology inverter circuit power device detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922207454.7U CN211554173U (en) | 2019-12-11 | 2019-12-11 | Three-level topology inverter circuit power device detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211554173U true CN211554173U (en) | 2020-09-22 |
Family
ID=72505301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922207454.7U Active CN211554173U (en) | 2019-12-11 | 2019-12-11 | Three-level topology inverter circuit power device detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211554173U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112731114A (en) * | 2020-12-30 | 2021-04-30 | 浙江华晟金属制品有限公司 | Instrument for quickly measuring thyristor and capacitor in series inverter circuit |
-
2019
- 2019-12-11 CN CN201922207454.7U patent/CN211554173U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112731114A (en) * | 2020-12-30 | 2021-04-30 | 浙江华晟金属制品有限公司 | Instrument for quickly measuring thyristor and capacitor in series inverter circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN201549882U (en) | Insulated gate dipole transistor protection device | |
| WO2021031642A1 (en) | Flying capacitor-type npc three-level topology | |
| CN109888739B (en) | MOSFET short-circuit protection circuit for drive axle | |
| CN201766490U (en) | Driving circuit based on IGBT bridge-type switch topology and protecting module thereof | |
| CN201523211U (en) | Power circuit of finished electric automobile controller | |
| CN105939148B (en) | Photovoltaic cell monitoring device | |
| CN103904622A (en) | IGBT overcurrent protection circuit | |
| CN102377326B (en) | Insulated gate bipolar transistor (IGBT)-bridge-switch-topology-based driving circuit and protection module thereof | |
| CN109659905A (en) | A kind of IPM overcurrent and thermal-shutdown circuit | |
| CN104466912B (en) | A kind of linear voltage regulator with short-circuit protection | |
| CN204131388U (en) | Pfc circuit and air conditioner | |
| CN211554173U (en) | Three-level topology inverter circuit power device detection circuit | |
| CN107634504B (en) | Protection control device, the protection controller of PFC pfc circuit | |
| CN206865122U (en) | A kind of overload protecting circuit for telecommunication circuit | |
| CN110837020A (en) | Three-level topology inverter circuit power device detection circuit | |
| CN107425811A (en) | The monitoring device and photovoltaic generating system of photovoltaic resistor | |
| CN204089573U (en) | A kind ofly carry bridge IGBT driver under three full-bridges of insulating power supply | |
| CN209562148U (en) | A kind of IPM overcurrent and thermal-shutdown circuit | |
| CN112596000A (en) | Method and device for detecting reverse connection of PV input ends of photovoltaic inverters | |
| CN103280775B (en) | Insulated gate bipolar transistor Parallel opertation dynamic delay current foldback circuit | |
| CN208158100U (en) | A kind of output overvoltage protection circuit and the power supply comprising the circuit | |
| EP4262039A1 (en) | Circuit protection method, system and apparatus | |
| CN110299696A (en) | T-type three-level current transformer and its short-circuit protection circuit | |
| CN203415942U (en) | Fault signal processing circuit | |
| CN103595286A (en) | Dead-time compensation method and circuit used for bipolar modulation inverter bridge |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |