CN211528974U - In-place signal detection circuit - Google Patents
In-place signal detection circuit Download PDFInfo
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- CN211528974U CN211528974U CN201922192759.5U CN201922192759U CN211528974U CN 211528974 U CN211528974 U CN 211528974U CN 201922192759 U CN201922192759 U CN 201922192759U CN 211528974 U CN211528974 U CN 211528974U
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- 238000001514 detection method Methods 0.000 title claims abstract description 24
- 239000003990 capacitor Substances 0.000 claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 9
- 230000003287 optical effect Effects 0.000 claims description 15
- 239000007787 solid Substances 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 6
- 230000001419 dependent effect Effects 0.000 claims description 3
- 238000001914 filtration Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 229910000831 Steel Inorganic materials 0.000 description 3
- 239000010959 steel Substances 0.000 description 3
- 238000005259 measurement Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
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Abstract
The utility model discloses a signal detection circuitry targets in place, including tubular metal resonator, stopper, its characterized in that: the detection circuit further comprises a PIN terminal, a first PIN of the PIN terminal is electrically connected with the metal tube and a third capacitor C3 respectively, the first PIN is grounded, wherein the third capacitor C3 is electrically connected with a third PIN of the PIN terminal through a twelfth resistor R12, the twelfth resistor R12 is also electrically connected with a seventh resistor R7, and a VCC power supply is electrically connected with the third PIN of the PIN terminal through the seventh resistor R7; the utility model discloses after carrying out filtering to the signal to shake, the poor condition of contact, the rethread is than the level and is eliminated the shake influence to can select whether to prolong trigger signal's output time through the function switch, thereby greatly improved signal detection ground accuracy and stability target in place.
Description
Technical Field
The utility model relates to a signal detection circuitry targets in place.
Background
The fixed-length in-place signal of the steel pipe of the pipe cutting machine in the industry does not use a sensor, most of electrical processes are conducted with 0V electricity on the whole equipment, the steel pipe is used as a conductor to impact a metal limiting block, and the limiting block is connected with the input end of the leakage type PLC to provide an input signal, so that whether the steel pipe is in place or not is judged.
In the pipe cutting machine industry, a signal detection scheme for feeding a pipe to a cutting position needs to be accurate and stable, the cutting precision of the pipe cannot be influenced, and the consistency and the repeatability of a sensor are required to have good performance parameter indexes.
Because tubular product is at the moment of reaching the spacing piece of location, its contact reliability is not always good, because inertia can appear bounce many times, and final tubular product and dog are contactless to lead to PLC to not receive the signal.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model is to overcome prior art's defect, provide a signal detection circuitry targets in place.
In order to solve the technical problem, the utility model provides a following technical scheme:
the utility model relates to a signal detection circuitry targets in place, including tubular metal resonator, stopper, its characterized in that: the detection circuit further comprises a PIN terminal, a first PIN of the PIN terminal is electrically connected with the metal tube and a third capacitor C3 respectively, the first PIN is grounded, wherein the third capacitor C3 is electrically connected with a third PIN of the PIN terminal through a twelfth resistor R12, the twelfth resistor R12 is also electrically connected with a seventh resistor R7, and a VCC power supply is electrically connected with the third PIN of the PIN terminal through the seventh resistor R7; the third PIN of the PIN terminal is further electrically connected to the limiting block, one end of a ninth resistor R9, and one end of a second voltage regulator D2, respectively, wherein the other end of the second voltage regulator D2 is electrically connected to the third PIN of the timer chip and one end of the zener diode, respectively, the other end of the zener diode is grounded, wherein the other end of the ninth resistor R9 is electrically connected to one end of a second polarity capacitor C2 and the non-inverting input terminal of the operational amplifier, respectively, wherein the other end of the second polarity capacitor C2 is grounded, wherein the inverting input terminal of the operational amplifier is electrically connected to one end of a second resistor R2 and one end of a sixth resistor R6, respectively, wherein the other end of the second resistor R2 is connected to the VCC power supply, wherein the other end of the sixth resistor R6 is grounded, and the eighth end of the operational amplifier is connected to the VCC power supply, the fourth end of the operational amplifier is grounded, the output end of the operational amplifier is electrically connected with the second pin of the timer chip and one end of a fifth resistor R5 respectively, and the other end of the fifth resistor R5 is connected with a VCC power supply.
Preferably, the detection circuit further comprises an optical solid state relay chip, a first pin of the optical solid state relay chip is electrically connected with a second pin of the toggle switch chip through an eleventh resistor R11, a second pin of the optical solid state relay chip is electrically connected with a fifth pin of the toggle switch chip through a light emitting diode, a third pin of the optical solid state relay chip is electrically connected with a fourth pin of the wire arranging seat chip, and a fourth pin of the optical solid state relay chip is electrically connected with a third pin of the wire arranging seat chip; the first pin of the toggle switch chip is connected with a VCC power supply, the third pin of the toggle switch chip is electrically connected with the third pin of the timer chip, the fourth pin of the toggle switch chip is grounded, and the sixth pin of the toggle switch chip is electrically connected with the second pin of the timer chip.
Preferably, the first pin of the timer chip is electrically connected to one end of a fourth capacitor C4 and one end of a fifth capacitor C5, respectively, and is grounded, wherein the other end of the fourth capacitor C4 is electrically connected to one end of an eighteenth resistor R18, the sixth pin of the timer chip, and the seventh pin thereof, respectively, and wherein the other end of the fifth capacitor C5 is electrically connected to the fifth pin of the timer chip; the other end of the eighteenth resistor R18 is electrically connected to the fourth pin and the eighth pin of the timer chip, respectively, and is connected to a VCC power supply.
Preferably, the first pin of the wire holder chip is electrically connected to the positive electrode of the 24V power supply and one end of the first fuse FU1, wherein the other end of the first fuse FU1 is electrically connected to one end of a first diode D1, the other end of the first diode D1 is electrically connected to one end of a third voltage regulator D3, one end of a first voltage dependent resistor RV1 and one end of a first inductor L1 respectively, wherein the other end of the first inductor L1 is electrically connected to one end of the first polarity capacitor C1 and the first pin of the first linear power chip U1, the second pin of the first linear power supply chip U1, the other end of the first polarity capacitor C1, the other end of the third voltage regulator tube D3 and the other end of the first piezoresistor RV1 are electrically connected with the second pin of the wire arranging seat chip, and the second pin of the wire arranging seat chip is also connected with the negative electrode of a 24V power supply.
Preferably, the third pin of the first linear power chip U1 is electrically connected to one end of a second polarity capacitor C2 and the first end of a common mode inductor, respectively, and the other end of the second polarity capacitor C2 is electrically connected to the second pin of the bus bar chip and the second end of the common mode inductor, respectively.
Preferably, a third end of the common mode inductor is electrically connected to one end of a sixth polar capacitor C6, the second pin of the second linear power chip U2, one end of a third polar capacitor C3, and the second pin of the isolation power chip, a fourth end of the common mode inductor is electrically connected to the other end of the sixth polar capacitor C6 and the first pin of the second linear power chip U2, and a third pin of the second linear power chip U2 is electrically connected to the other end of the third polar capacitor C3 and the first pin of the isolation power chip.
Preferably, the third pin of the isolated power chip is electrically connected to one end of the fourth polar capacitor C4, one end of the fifth polar capacitor C5, and one end of the first capacitor C1, respectively, and is grounded; and a fourth pin of the isolated power supply chip is electrically connected with the other end of the fourth polar capacitor C4, the other end of the fifth polar capacitor C5 and the other end of the first capacitor C1 through a second inductor L2 respectively, and is connected with a VCC power supply.
The utility model discloses the beneficial effect who reaches is:
the utility model discloses after carrying out filtering to the signal to shake, the poor condition of contact, the rethread is than the level and is eliminated the shake influence to can select whether to prolong trigger signal's output time through the function switch, thereby greatly improved signal detection ground accuracy and stability target in place.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a partial circuit diagram of the present invention;
FIG. 2 is a partial circuit diagram of the present invention;
FIG. 3 is a partial circuit diagram of the present invention;
FIG. 4 is a partial circuit diagram of the present invention;
FIG. 5 is a graph of actual measurement data of the present invention;
FIG. 6 is a graph of actual measurement data of the present invention;
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are presented herein only to illustrate and explain the present invention, and not to limit the present invention.
Example 1
Fig. 1 to fig. 4 constitute in this embodiment the utility model discloses complete circuit diagram, as shown in fig. 1 to fig. 4, a signal detection circuitry targets in place, including tubular metal resonator, stopper, its characterized in that: the detection circuit further comprises a PIN terminal, a first PIN of the PIN terminal is electrically connected with the metal tube and a third capacitor C3 respectively, the first PIN is grounded, wherein the third capacitor C3 is electrically connected with a third PIN of the PIN terminal through a twelfth resistor R12, the twelfth resistor R12 is also electrically connected with a seventh resistor R7, and a VCC power supply is electrically connected with the third PIN of the PIN terminal through the seventh resistor R7; the third PIN of the PIN terminal is further electrically connected to the limiting block, one end of a ninth resistor R9, and one end of a second voltage regulator D2, respectively, wherein the other end of the second voltage regulator D2 is electrically connected to the third PIN of the timer chip and one end of the zener diode, respectively, the other end of the zener diode is grounded, wherein the other end of the ninth resistor R9 is electrically connected to one end of a second polarity capacitor C2 and the non-inverting input terminal of the operational amplifier, respectively, wherein the other end of the second polarity capacitor C2 is grounded, wherein the inverting input terminal of the operational amplifier is electrically connected to one end of a second resistor R2 and one end of a sixth resistor R6, respectively, wherein the other end of the second resistor R2 is connected to the VCC power supply, wherein the other end of the sixth resistor R6 is grounded, the eighth end of the operational amplifier is connected to the VCC power supply, and the fourth end of the operational amplifier is grounded, the output end of the operational amplifier is electrically connected with the second pin of the timer chip and one end of a fifth resistor R5 respectively, wherein the other end of the fifth resistor R5 is connected with a VCC power supply; the detection circuit also comprises an optical solid state relay chip, wherein a first pin of the optical solid state relay chip is electrically connected with a second pin of the toggle switch chip through an eleventh resistor R11, a second pin of the optical solid state relay chip is electrically connected with a fifth pin of the toggle switch chip through a light emitting diode, a third pin of the optical solid state relay chip is electrically connected with a fourth pin of the wire arranging seat chip, and a fourth pin of the optical solid state relay chip is electrically connected with a third pin of the wire arranging seat chip; the first pin of the toggle switch chip is connected with a VCC power supply, the third pin of the toggle switch chip is electrically connected with the third pin of the timer chip, the fourth pin of the toggle switch chip is grounded, and the sixth pin of the toggle switch chip is electrically connected with the second pin of the timer chip; the first pin of the timer chip is electrically connected with one end of a fourth capacitor C4 and one end of a fifth capacitor C5 respectively, and is grounded, wherein the other end of the fourth capacitor C4 is electrically connected with one end of an eighteenth resistor R18, the sixth pin and the seventh pin of the timer chip respectively, and wherein the other end of the fifth capacitor C5 is electrically connected with the fifth pin of the timer chip; the other end of the eighteenth resistor R18 is electrically connected with the fourth pin and the eighth pin of the timer chip respectively and is connected with a VCC power supply; the first pin of the bus bar chip is electrically connected to the anode of the 24V power supply and one end of the first fuse FU1, wherein the other end of the first fuse FU1 is electrically connected to one end of a first diode D1, the other end of the first diode D1 is electrically connected to one end of a third voltage regulator D3, one end of a first voltage dependent resistor RV1 and one end of a first inductor L1 respectively, wherein the other end of the first inductor L1 is electrically connected to one end of the first polarity capacitor C1 and the first pin of the first linear power chip U1, the second pin of the first linear power supply chip U1, the other end of the first polarity capacitor C1, the other end of the third voltage regulator tube D3 and the other end of the first piezoresistor RV1 are electrically connected with the second pin of the wire arranging seat chip, and the second pin of the wire arranging seat chip is also connected with the negative electrode of a 24V power supply; a third pin of the first linear power chip U1 is electrically connected to one end of a second polar capacitor C2 and a first end of a common mode inductor, respectively, wherein the other end of the second polar capacitor C2 is electrically connected to a second pin of the rower socket chip and a second end of the common mode inductor, respectively; a third end of the common mode inductor is electrically connected with one end of a sixth polar capacitor C6, a second pin of a second linear power chip U2, one end of a third polar capacitor C3 and a second pin of an isolation power chip respectively, a fourth end of the common mode inductor is electrically connected with the other end of the sixth polar capacitor C6 and a first pin of a second linear power chip U2 respectively, and a third pin of the second linear power chip U2 is electrically connected with the other end of the third polar capacitor C3 and the first pin of the isolation power chip respectively; the third pin of the isolated power chip is electrically connected with one end of a fourth polar capacitor C4, one end of a fifth polar capacitor C5 and one end of a first capacitor C1 respectively, and is grounded; and a fourth pin of the isolated power supply chip is electrically connected with the other end of the fourth polar capacitor C4, the other end of the fifth polar capacitor C5 and the other end of the first capacitor C1 through a second inductor L2 respectively, and is connected with a VCC power supply.
As shown in fig. 5, when the original signal is not in good contact after being impacted (CH1 waveform), the original signal is processed by the in-place signal processing module to obtain reliable and stable long-time output, thereby effectively avoiding the response problem of the lower computer. (0-1S can be set).
As shown in fig. 6, when the original signal has poor contact such as jitter, intermittence and the like in the process of impacting a limit block (CH1), the signal is still stably output after being processed.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing embodiments, or equivalents may be substituted for elements thereof. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. The utility model provides a signal detection circuitry targets in place, includes tubular metal resonator, stopper, its characterized in that: the detection circuit further comprises a PIN terminal, a first PIN of the PIN terminal is electrically connected with the metal tube and a third capacitor C3 respectively, the first PIN is grounded, wherein the third capacitor C3 is electrically connected with a third PIN of the PIN terminal through a twelfth resistor R12, the twelfth resistor R12 is also electrically connected with a seventh resistor R7, and a VCC power supply is electrically connected with the third PIN of the PIN terminal through the seventh resistor R7; the third PIN of the PIN terminal is further electrically connected to the limiting block, one end of a ninth resistor R9, and one end of a second voltage regulator D2, respectively, the other end of the second voltage regulator D2 is electrically connected to the third PIN of the timer chip and one end of the zener diode, respectively, the other end of the zener diode is grounded, wherein the other end of the ninth resistor R9 is electrically connected to one end of a second polarity capacitor C2 and the non-inverting input terminal of the operational amplifier, respectively, wherein the other end of the second polarity capacitor C2 is grounded, wherein the inverting input terminal of the operational amplifier is electrically connected to one end of a second resistor R2 and one end of a sixth resistor R6, respectively, wherein the other end of the second resistor R2 is connected to the VCC power supply, wherein the other end of the sixth resistor R6 is grounded, the eighth end of the operational amplifier is connected to the VCC power supply, and the fourth end of the operational amplifier is grounded, the output end of the operational amplifier is electrically connected with the second pin of the timer chip and one end of a fifth resistor R5 respectively, wherein the other end of the fifth resistor R5 is connected with a VCC power supply.
2. The in-place signal detection circuit as claimed in claim 1, wherein: the detection circuit also comprises an optical solid state relay chip, wherein a first pin of the optical solid state relay chip is electrically connected with a second pin of the toggle switch chip through an eleventh resistor R11, a second pin of the optical solid state relay chip is electrically connected with a fifth pin of the toggle switch chip through a light emitting diode, a third pin of the optical solid state relay chip is electrically connected with a fourth pin of the wire arranging seat chip, and a fourth pin of the optical solid state relay chip is electrically connected with a third pin of the wire arranging seat chip; the first pin of the toggle switch chip is connected with a VCC power supply, the third pin of the toggle switch chip is electrically connected with the third pin of the timer chip, the fourth pin of the toggle switch chip is grounded, and the sixth pin of the toggle switch chip is electrically connected with the second pin of the timer chip.
3. The in-place signal detection circuit as claimed in claim 2, wherein: the first pin of the timer chip is electrically connected with one end of a fourth capacitor C4 and one end of a fifth capacitor C5 respectively, and is grounded, wherein the other end of the fourth capacitor C4 is electrically connected with one end of an eighteenth resistor R18, the sixth pin and the seventh pin of the timer chip respectively, and wherein the other end of the fifth capacitor C5 is electrically connected with the fifth pin of the timer chip; the other end of the eighteenth resistor R18 is electrically connected to the fourth pin and the eighth pin of the timer chip, respectively, and is connected to a VCC power supply.
4. A bit signal detection circuit as claimed in claim 3, wherein: the first pin of the bus bar chip is electrically connected to the anode of the 24V power supply and one end of the first fuse FU1, wherein the other end of the first fuse FU1 is electrically connected to one end of a first diode D1, the other end of the first diode D1 is electrically connected to one end of a third voltage regulator D3, one end of a first voltage dependent resistor RV1 and one end of a first inductor L1 respectively, wherein the other end of the first inductor L1 is electrically connected to one end of the first polarity capacitor C1 and the first pin of the first linear power chip U1, the second pin of the first linear power supply chip U1, the other end of the first polarity capacitor C1, the other end of the third voltage regulator tube D3 and the other end of the first piezoresistor RV1 are electrically connected with the second pin of the wire arranging seat chip, and the second pin of the wire arranging seat chip is also connected with the negative electrode of a 24V power supply.
5. The bit signal detection circuit of claim 4, wherein: the third pin of the first linear power chip U1 is electrically connected to one end of a second polar capacitor C2 and the first end of a common mode inductor, respectively, wherein the other end of the second polar capacitor C2 is electrically connected to the second pin of the rower block chip and the second end of the common mode inductor, respectively.
6. The bit signal detection circuit of claim 5, wherein: the third end of the common mode inductor is electrically connected with one end of a sixth polar capacitor C6, the second pin of a second linear power chip U2, one end of a third polar capacitor C3 and the second pin of an isolation power chip respectively, the fourth end of the common mode inductor is electrically connected with the other end of the sixth polar capacitor C6 and the first pin of the second linear power chip U2 respectively, and the third pin of the second linear power chip U2 is electrically connected with the other end of the third polar capacitor C3 and the first pin of the isolation power chip respectively.
7. The bit signal detection circuit of claim 6, wherein: the third pin of the isolated power chip is electrically connected with one end of a fourth polar capacitor C4, one end of a fifth polar capacitor C5 and one end of a first capacitor C1 respectively, and is grounded; and a fourth pin of the isolated power supply chip is electrically connected with the other end of the fourth polar capacitor C4, the other end of the fifth polar capacitor C5 and the other end of the first capacitor C1 through a second inductor L2 respectively, and is connected with a VCC power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922192759.5U CN211528974U (en) | 2019-12-10 | 2019-12-10 | In-place signal detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922192759.5U CN211528974U (en) | 2019-12-10 | 2019-12-10 | In-place signal detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211528974U true CN211528974U (en) | 2020-09-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922192759.5U Expired - Fee Related CN211528974U (en) | 2019-12-10 | 2019-12-10 | In-place signal detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211528974U (en) |
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2019
- 2019-12-10 CN CN201922192759.5U patent/CN211528974U/en not_active Expired - Fee Related
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Granted publication date: 20200918 |