CN117031186B - Detonator chip testing system and method - Google Patents
Detonator chip testing system and method Download PDFInfo
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- CN117031186B CN117031186B CN202310990204.3A CN202310990204A CN117031186B CN 117031186 B CN117031186 B CN 117031186B CN 202310990204 A CN202310990204 A CN 202310990204A CN 117031186 B CN117031186 B CN 117031186B
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- 238000012360 testing method Methods 0.000 title claims abstract description 121
- 238000000034 method Methods 0.000 title claims description 4
- 238000001514 detection method Methods 0.000 claims abstract description 58
- 238000004891 communication Methods 0.000 claims abstract description 18
- 239000003990 capacitor Substances 0.000 claims description 66
- 238000011990 functional testing Methods 0.000 claims description 3
- 230000008054 signal transmission Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005422 blasting Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005474 detonation Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/01—Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F42—AMMUNITION; BLASTING
- F42C—AMMUNITION FUZES; ARMING OR SAFETY MEANS THEREFOR
- F42C21/00—Checking fuzes; Testing fuzes
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
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Abstract
The invention provides a detonator chip testing system and a detonator chip testing method, which can meet different testing requirements aiming at different types of chips and have good universality; the upper computer is connected with a data service platform configured with a chip code to be tested, and is used for sending an operation instruction to the lower computer, obtaining a test result according to the information returned by the lower computer and the called chip code to be tested, and issuing a sorting signal according to the test result; the lower computer includes: the test equipment is connected with the upper computer and is used for sending a test instruction to at least one chip to be tested according to the operation instruction, determining test parameters according to response information of the chip to be tested and sending the test parameters to the upper computer; the test parameters comprise communication detection parameters, current detection parameters and frequency detection parameters; and the sorting machine is connected with the upper computer and is used for sorting the yield of the chips to be tested according to the pipe sorting signals.
Description
Technical Field
The invention relates to the technical field of detonator chip testing, in particular to a detonator chip testing system and method.
Background
As a core control component of the digital electronic detonator, the special chip of the electronic control module determines the time precision and blasting effect of blasting, and after the special chip of the general electronic control module is subjected to middle measurement and encapsulation, in order to reduce the reject ratio, reduce the loss cost and avoid the flow of the reject product module to a client terminal, the chip needs to be subjected to functional detection such as current, communication, bridging wire, detonation, delay precision, ignition capability and the like, so as to judge whether the chip is qualified or not; however, with the update of the special chip of the electronic control module, different tests are required to be performed for different types of chips, but the existing market equipment cannot be used universally, that is, the test system for different chips is not available in the market at present, and thus the test requirement cannot be met, so that the development of enterprises is limited.
Disclosure of Invention
Aiming at the problems, the invention provides a detonator chip testing system and a detonator chip testing method, which can meet different testing requirements aiming at different types of chips and have good universality.
The invention adopts the following technical scheme: the detonator chip testing system comprises an upper computer and a lower computer and is characterized in that: the upper computer is connected with a data service platform configured with a chip code to be tested, and is used for sending an operation instruction to the lower computer, obtaining a test result according to the information returned by the lower computer and the called chip code to be tested, and issuing a sorting signal according to the test result;
The lower computer includes:
the test equipment is connected with the upper computer and is used for sending a test instruction to at least one chip to be tested according to the operation instruction, determining test parameters according to response information of the chip to be tested and sending the test parameters to the upper computer; the test parameters comprise communication detection parameters, current detection parameters and frequency detection parameters;
And the sorting machine is connected with the upper computer and is used for sorting the yield of the chips to be tested according to the pipe sorting signals.
Further, the test equipment is provided with a power panel, a test panel and an interface panel; the power panel is connected with the test panel and used for providing power for the test panel; the test board is connected with the interface board and the chip to be tested and is used for providing functional test of the chip to be tested; the interface board is connected with the sorting machine and the upper computer and is used for providing a signal interface to realize signal transmission with the sorting machine and the upper computer;
further, a control module, a driving module, a detection module and a bus exchange module are arranged on the test board, wherein the driving module is connected with the control module, the detection module and the bus exchange module and is used for providing driving signals for the detection module and the bus exchange module; the detection module is connected with the control module, the driving module and the bus exchange module, and is used for performing functional detection on the chip to be detected and feeding back detection parameters to the control module; the bus exchange module is connected with the chip to be tested and is used for exchanging bus signals;
Further, the control module adopts a singlechip, the driving module and the detection module are both connected with the singlechip, and the singlechip is connected with the separator and the upper computer through the interface board;
Further, the driving module comprises a MOS tube driver U1, resistors R1-R5 and capacitors C1 and C2, one end of the resistor R1 is connected with pins 2 and 4 of the MOS tube driver U1, the other end of the resistor R1 is connected with a power supply 3.3V, one end of the resistor R2 is connected with pin 1 of the MOS tube driver U1, one end of the resistor R3 is connected with pin 8 of the MOS tube driver U1, the other ends of the resistors R2 and R3 are both connected with a bus voltage VBUS, one end of the capacitor C2 is connected with the bus voltage VBUS, the other end of the capacitor C2 is grounded, one end of the resistor R5 is connected with pin 5 of the MOS tube driver U1, the other end of the resistor R5 is connected with one end of the resistor R4 and one end of the capacitor C1, the other ends of the resistor R4 and the capacitor C1 are connected with each other and then grounded, and the pin 4 of the MOS tube driver U1 is connected with the single chip microcomputer;
Further, the detection module comprises a current sensing amplifier U2, an operational amplifier U3, a filter U4, a comparator U5, resistors R6-R22, capacitors C3-C11 and fuses F1 and F2; The 5 pins of the MOS tube driver U1 are connected with one ends of the resistors R6 and R7, the 7 pin of the MOS tube driver U1 is connected with one end of the resistor R8, the other end of the resistor R6 is connected with the 12 pin of the current sense amplifier U2, the 4 pin of the current sense amplifier U2 is grounded after being connected with the resistor R10, the other end of the resistor R7 is connected with one end of the resistor R9, one end of the fuse F1 and the 8 pin of the current sense amplifier U2, the other end of the resistor R9 is grounded, the other end of the resistor R8 is connected with one end of the fuse F2, One end of the capacitor C3 is connected with one end of the capacitor C4 and the 7 pin of the current sense amplifier U2 and then connected with the voltage V-6102, and the other end of the capacitor C3 is connected with the 6 pin of the current sense amplifier U2; The pin 4 of the current sensing amplifier U2 is connected with the pin 3 of the operational amplifier U3, the pin 5 of the operational amplifier U3 is connected with one end of the resistor R11, the pin 6 of the operational amplifier U3 is connected with one ends of the resistors R12 and R13, the other end of the resistor R13 is grounded, the pin 7 of the operational amplifier U3 is connected with one end of the resistor R14 and the other end of the resistor R12, the other end of the resistor R14 is connected with one end of the capacitor C6, the other ends of the capacitor C6 and the resistor R13 are grounded, the pin 8 of the operational amplifier U3 is connected with one end of the capacitor C5 and then is powered by 3.3V, The other end of the capacitor C5 is grounded; One end of the resistor R15 is connected with pins 1 and 2 of the operational amplifier U3 and the other end of the resistor R11, the other end of the resistor R15 is connected with one end of the capacitor C11, the other end of the capacitor C11 is connected with one end of the resistor R16 and pin 3 of the filter U4, the other end of the resistor R16 is connected with pin 4 of the filter U4 and then grounded, the resistor R17 is connected between pins 1 and 8 of the filter U4, one end of the resistor R18 is connected with pin 6 of the filter U4, the other end of the resistor R18 is connected with one end of the capacitor C8, the other end of the capacitor C8 is grounded, the pin 7 of the filter U4 is connected with one end of the capacitor C7 and then connected with a power supply 5V, and the other end of the capacitor C7 is grounded; One end of the resistor R21 is connected with one end of the resistor R22, the other end of the resistor R21 is connected with a power supply 3.3V, the other end of the resistor R22 is grounded, the 4 pin of the comparator U5 is connected with one ends of the resistors R19 and R20, the other end of the resistor R20 is connected with the power supply 3.3V, the other end of the resistor R19 is connected with the capacitor C10 and then grounded, the 5 pin of the comparator U5 is connected with one end of the capacitor C9 and then connected with the power supply 5V, and the 2 pin of the comparator U5 is connected with the other end of the capacitor C9 and then grounded;
Further, the bus exchange module comprises a relay JD1, resistors R23 and R24, a MOS tube Q1, a diode D1 and a light emitting diode LED1; the relay JD1 is characterized in that the 6 pin of the relay JD1 is connected with the other end of the fuse F1, the 3 pin of the relay JD1 is connected with the other end of the fuse F2, the 2,4,5 and 7 pins of the relay JD1 are all connected with the chip to be tested, the 1 pin of the relay JD1 is connected with the cathode of the diode D1 and one end of the resistor R24 and then connected with the power supply 5V, the other end of the resistor R24 is connected with the anode of the light emitting diode LED1, the cathode of the light emitting diode LED1 is connected with the anode of the diode D1, the 8 pin of the relay JD1 and the drain electrode of the MOS tube Q1, the grid electrode of the MOS tube Q1 is connected with one end of the resistor R23 and then connected with the single chip microcomputer, and the source electrode of the MOS tube Q1 is connected with the other end of the resistor R23 and then grounded;
the detonator chip testing method is characterized by comprising the following steps of:
Transmitting a test instruction to at least one chip to be tested according to the acquired operation instruction, and determining a test parameter according to response information of the chip to be tested; the test parameters comprise communication detection parameters, current detection parameters and frequency detection parameters;
judging whether the test of the chip to be tested is qualified or not based on the comparison of the test parameters and preset conditions;
and obtaining a branch pipe signal according to the judging result, and sorting and storing the branch pipe signal according to the yield.
Further, determining the test parameters comprises the steps of:
s1.1, before testing, binding a chip type template to be tested by a data service platform, and calling the template by an upper computer;
S1.2, an upper computer issues an operation instruction to test equipment, and the communication, current and frequency function test is carried out on the chip to be tested according to the test instruction;
S1.3, after the test is completed, sending test result parameters to the upper computer;
Further, judging whether the chip to be tested is qualified or not includes the following steps:
S2.1, comparing the test result parameters with the templates called in the upper computer;
s2.2, if the conditions are met, judging that the chip to be tested is qualified in test; if the conditions are not met, judging that the chip to be tested is unqualified, and issuing a pipe distributing signal to a sorting machine, wherein the sorting machine sorts and stores the chip to be tested according to the judging results of communication, current and frequency tests.
The invention has the beneficial effects that the invention can perform effective function test on the packaged module chip, can meet different test requirements for different chips, can sort according to test results, is convenient for analysis, and has better use value.
Drawings
FIG. 1 is a block diagram of the structure of the present invention;
FIG. 2 is a schematic diagram of the circuitry on the test board of the present invention;
FIG. 3 is a schematic diagram of the connection of modules on a test board according to the present invention;
fig. 4 is a schematic structural view of the test apparatus of the present invention.
Detailed Description
As shown in fig. 1 to 4, the detonator chip test system of the invention comprises an upper computer and a lower computer, wherein the upper computer is connected with a data service platform configured with a chip code to be tested, and is used for sending an operation instruction to the lower computer, obtaining a test result according to information returned by the lower computer and the called chip code to be tested, and issuing a sorting signal according to the test result;
The lower computer includes:
The test equipment is connected with the upper computer and is used for sending a test instruction to at least one chip to be tested according to the operation instruction, determining a test parameter according to response information of the chip to be tested and sending the test parameter to the upper computer; the test parameters comprise communication detection parameters, current detection parameters and frequency detection parameters;
And the sorting machine is connected with the upper computer and is used for sorting the yield of the chips to be tested according to the sorting signals.
The test equipment is provided with a power panel, a test panel and an interface panel; the power panel is connected with the test panel and used for providing power for the test panel, such as each bus power supply, a relay power supply, a singlechip power supply and an operational amplifier power supply;
The test board is connected with the interface board and the chip to be tested and is used for providing functional tests (communication detection, current detection and frequency detection) of the chip to be tested;
The interface board is connected with the sorting machine and the upper computer and used for providing a signal interface and realizing signal transmission with the sorting machine and the upper computer.
The test board is provided with a control module, a driving module, a detection module and a bus exchange module, wherein the driving module is connected with the control module, the detection module and the bus exchange module and is used for providing driving signals for the detection module and the bus exchange module; the detection module is connected with the control module, the driving module and the bus exchange module and is used for carrying out functional detection on the chip to be detected and feeding back detection parameters to the control module; the bus exchange module is connected with the chip to be tested and is used for exchanging bus signals; the control module adopts a singlechip (not shown in the figure), the driving module and the detection module are both connected with the singlechip, and the singlechip is connected with the sorting machine and the upper computer through the interface board.
The driving module comprises a MOS tube driver U1, resistors R1-R5 and capacitors C1 and C2, wherein the MOS tube driver U1 adopts a model IX4428NTR chip; one end of a resistor R1 is connected with pins 2 and 4 of the MOS tube driver U1, the other end of the resistor R1 is connected with a power supply 3.3V, one end of the resistor R2 is connected with pin 1 of the MOS tube driver U1, one end of the resistor R3 is connected with pin 8 of the MOS tube driver U1, the other ends of the resistor R2 and the resistor R3 are both connected with a bus voltage VBUS, one end of a capacitor C2 is connected with the bus voltage VBUS, the other end of the capacitor C2 is grounded, one end of the resistor R5 is connected with pin 5 of the MOS tube driver U1, the other end of the resistor R5 is connected with one end of the resistor R4 and one end of the capacitor C1, the other ends of the resistor R4 and the capacitor C1 are connected with each other and then grounded, and the pin 4 of the MOS tube driver U1 is connected with a single chip microcomputer.
The detection module comprises a current sensing amplifier U2, an operational amplifier U3, a filter U4, a comparator U5, resistors R6-R22, capacitors C3-C11 and fuses F1 and F2; the current sensing amplifier U2 adopts a model LTC6102IMS8# PBF chip, the operational amplifier U3 adopts a model RS8552XK chip, the filter U4 adopts a model AD623ARZ-R7 chip, and the comparator U5 adopts a model LMV331IDBVR chip; the 5 pin of the MOS tube driver U1 is connected with one ends of the resistors R6 and R7, the 7 pin of the MOS tube driver U1 is connected with one end of the resistor R8, the other end of the resistor R6 is connected with the 12 pin of the current sense amplifier U2, the 4 pin of the current sense amplifier U2 is grounded after passing through the connecting resistor R10, the other end of the resistor R7 is connected with one end of the resistor R9, one end of the fuse F1 and the 8 pin of the current sense amplifier U2, the other end of the resistor R9 is grounded, the other end of the resistor R8 is connected with one end of the fuse F2, one end of the capacitor C3 is connected with one end of the capacitor C4 and the 7 pin of the current sense amplifier U2 and then connected with the voltage V-6102, The voltage V-6102 is the power supply of the current sense amplifier U2, and the other end of the capacitor C3 is connected with the 6 pin of the current sense amplifier U2; The 4 pin of the current sense amplifier U2 is connected with the 3 pin of the operational amplifier U3, the 5 pin of the operational amplifier U3 is connected with one end of a resistor R11, the 6 pin of the operational amplifier U3 is connected with one ends of resistors R12 and R13, the other end of the resistor R13 is grounded, the 7 pin of the operational amplifier U3 is connected with one end of a resistor R14 and the other end of the resistor R12, the other end of the resistor R14 is connected with one end of a capacitor C6, the other ends of the capacitor C6 and the resistor R13 are grounded, the 8 pin of the operational amplifier U3 is connected with one end of a capacitor C5 and then is connected with a power supply 3.3V, and the other end of the capacitor C5 is grounded; One end of a resistor R15 is connected with pins 1 and 2 of an operational amplifier U3 and the other end of a resistor R11, the other end of the resistor R15 is connected with one end of a capacitor C11, the other end of the capacitor C11 is connected with one end of a resistor R16 and pin 3 of a filter U4, the other end of the resistor R16 is connected with pin 4 of the filter U4 and then grounded, a resistor R17 is connected between pins 1 and 8 of the filter U4, one end of a resistor R18 is connected with pin 6 of the filter U4, the other end of the resistor R18 is connected with one end of a capacitor C8, the other end of the capacitor C8 is grounded, pin 7 of the filter U4 is connected with one end of a capacitor C7 and then connected with a power supply 5V, the other end of the capacitor C7 is grounded; One end of a resistor R21 is connected with one end of a resistor R22, the other end of the resistor R21 is connected with a power supply 3.3V, the other end of the resistor R22 is grounded, a pin 4 of a comparator U5 is connected with one ends of resistors R19 and R20, the other end of the resistor R20 is connected with the power supply 3.3V, the other end of the resistor R19 is connected with a capacitor C10 and then grounded, a pin 5 of the comparator U5 is connected with one end of the capacitor C9 and then connected with the power supply 5V, and a pin 2 of the comparator U5 is connected with the other end of the capacitor C9 and then grounded.
The bus exchange module comprises a relay JD1, resistors R23 and R24, a MOS tube Q1, a diode D1 and a light-emitting diode LED1; the other end of fuse F1 is connected to 6 feet of relay JD1, the other end of fuse F2 is connected to 3 feet of relay JD1, 2,4, 5, 7 feet of relay JD1 all connect in the chip that awaits measuring, in order to be used for detecting that the chip that awaits measuring just connects, all can communicate, connect power 5V after connecting evenly with the negative pole of diode D1, the one end of resistance R24, the positive pole of emitting diode LED1 is connected to the other end of resistance R24, the positive pole of emitting diode LED1 and diode D1, the 8 feet of relay JD1, MOS pipe Q1's drain electrode all is connected, MOS pipe Q1's grid is connected in the singlechip after being connected with one end of resistance R23, MOS pipe Q1's source is connected with the other end of resistance R23 ground.
In fig. 2, vbus_h is the bus voltage; the DATA_IN is connected to the singlechip; the existing model control device adopted by the singlechip.
A detonator chip testing method comprises the following steps:
transmitting a test instruction to at least one chip to be tested according to the acquired operation instruction, and determining a test parameter according to response information of the chip to be tested; the test parameters comprise communication detection parameters, current detection parameters and frequency detection parameters;
judging whether the test of the chip to be tested is qualified or not based on the comparison of the test parameters and preset conditions;
obtaining a branch pipe signal according to the judging result, and sorting and storing the branch pipe signal according to the yield;
Specifically, determining the test parameters includes the steps of:
S1.1, before testing, binding a chip type template to be tested by a data service platform, and calling the template by an upper computer;
S1.2, an upper computer issues an operation instruction to test equipment, and the communication, current and frequency function test is carried out on a chip to be tested according to the test instruction;
s1.3, after the test is completed, sending the test result parameters to an upper computer;
Judging whether the chip to be tested is qualified or not comprises the following steps:
S2.1, comparing the test result parameters with templates called in an upper computer;
S2.2, if the conditions are met, judging that the chip to be tested is qualified in test; if the conditions are not met, judging that the chip to be tested is unqualified, and sending a pipe sorting signal to a sorting machine, and sorting and storing the chip to be tested according to the judging results of communication, current and frequency tests.
The detection principle of the invention is as follows:
When the communication is detected: the MOS tube driver U1 sends a signal to a chip to be tested for communication, the chip to be tested returns with a current signal to cause current change, the current sense amplifier U2 detects the change, and then the captured pulse width is output to the singlechip through the DATA_IN end after filtering and comparison, and the singlechip analyzes the return DATA of the chip to be tested according to the duration time length of the high and low level of the pulse width to obtain communication detection parameters;
When the current is detected: the chip to be tested is connected to the test board until the current is stable, the singlechip acquires current detection parameters, and the current detection parameters are transmitted to the upper computer;
when frequency detection is performed: the MOS tube driver U1 sends a timing signal, the chip to be detected starts timing after receiving the timing signal, then sends a timing end signal after 1s, the chip to be detected stops timing, returns a count value in 1s, and then represents the frequency, and the frequency detection parameter is transmitted to the upper computer;
After the obtained detection parameters are transmitted to the upper computer, the upper computer corresponds to different test templates according to different chip codes, then the upper computer judges whether the chip to be detected is qualified according to preset conditions, if not, the upper computer sends out a management separation signal, and the chip to be detected can be separated and stored according to the unqualified detection items through the sorting machine according to different detection items, so that subsequent analysis is facilitated.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (4)
1. The detonator chip testing system comprises an upper computer and a lower computer and is characterized in that: the upper computer is connected with a data service platform configured with a chip code to be tested, and is used for sending an operation instruction to the lower computer, obtaining a test result according to the information returned by the lower computer and the called chip code to be tested, and issuing a sorting signal according to the test result;
The lower computer includes:
the test equipment is connected with the upper computer and is used for sending a test instruction to at least one chip to be tested according to the operation instruction, determining test parameters according to response information of the chip to be tested and sending the test parameters to the upper computer; the test parameters comprise communication detection parameters, current detection parameters and frequency detection parameters;
The sorting machine is connected with the upper computer and used for sorting the yield of the chips to be tested according to the pipe sorting signals; the test equipment is provided with a power panel, a test panel and an interface panel; the power panel is connected with the test panel and used for providing power for the test panel; the test board is connected with the interface board and the chip to be tested and is used for providing functional test of the chip to be tested; the interface board is connected with the sorting machine and the upper computer and is used for providing a signal interface to realize signal transmission with the sorting machine and the upper computer; the test board is provided with a control module, a driving module, a detection module and a bus exchange module, wherein the driving module is connected with the control module, the detection module and the bus exchange module and is used for providing driving signals for the detection module and the bus exchange module; the detection module is connected with the control module, the driving module and the bus exchange module, and is used for performing functional detection on the chip to be detected and feeding back detection parameters to the control module; the bus exchange module is connected with the chip to be tested and is used for exchanging bus signals;
The control module adopts a singlechip, the driving module and the detection module are both connected with the singlechip, and the singlechip is connected with the sorting machine and the upper computer through the interface board;
The driving module comprises a MOS tube driver U1, resistors R1-R5 and capacitors C1 and C2, wherein one end of the resistor R1 is connected with pins 2 and 4 of the MOS tube driver U1, the other end of the resistor R1 is connected with a power supply 3.3V, one end of the resistor R2 is connected with pin 1 of the MOS tube driver U1, one end of the resistor R3 is connected with pin 8 of the MOS tube driver U1, the other ends of the resistors R2 and R3 are both connected with a bus voltage VBUS, one end of the capacitor C2 is connected with the bus voltage VBUS, the other end of the capacitor C2 is connected with pin 5 of the MOS tube driver U1, the other end of the resistor R5 is connected with one end of the resistor R4 and one end of the capacitor C1, the other ends of the resistor R4 and the capacitor C1 are connected with the ground, and the pin 4 of the MOS tube driver U1 is connected with the singlechip;
the detection module comprises a current sensing amplifier U2, an operational amplifier U3, a filter U4, a comparator U5, resistors R6-R22, capacitors C3-C11 and fuses F1 and F2; The 5 pins of the MOS tube driver U1 are connected with one ends of the resistors R6 and R7, the 7 pin of the MOS tube driver U1 is connected with one end of the resistor R8, the other end of the resistor R6 is connected with the 12 pin of the current sense amplifier U2, the 4 pin of the current sense amplifier U2 is grounded after being connected with the resistor R10, the other end of the resistor R7 is connected with one end of the resistor R9, one end of the fuse F1 and the 8 pin of the current sense amplifier U2, the other end of the resistor R9 is grounded, the other end of the resistor R8 is connected with one end of the fuse F2, One end of the capacitor C3 is connected with one end of the capacitor C4 and the 7 pin of the current sense amplifier U2 and then connected with the voltage V-6102, and the other end of the capacitor C3 is connected with the 6 pin of the current sense amplifier U2; The pin 4 of the current sensing amplifier U2 is connected with the pin 3 of the operational amplifier U3, the pin 5 of the operational amplifier U3 is connected with one end of the resistor R11, the pin 6 of the operational amplifier U3 is connected with one ends of the resistors R12 and R13, the other end of the resistor R13 is grounded, the pin 7 of the operational amplifier U3 is connected with one end of the resistor R14 and the other end of the resistor R12, the other end of the resistor R14 is connected with one end of the capacitor C6, the other ends of the capacitor C6 and the resistor R13 are grounded, the pin 8 of the operational amplifier U3 is connected with one end of the capacitor C5 and then is powered by 3.3V, The other end of the capacitor C5 is grounded; One end of the resistor R15 is connected with pins 1 and 2 of the operational amplifier U3 and the other end of the resistor R11, the other end of the resistor R15 is connected with one end of the capacitor C11, the other end of the capacitor C11 is connected with one end of the resistor R16 and pin 3 of the filter U4, the other end of the resistor R16 is connected with pin 4 of the filter U4 and then grounded, the resistor R17 is connected between pins 1 and 8 of the filter U4, one end of the resistor R18 is connected with pin 6 of the filter U4, the other end of the resistor R18 is connected with one end of the capacitor C8, the other end of the capacitor C8 is grounded, the pin 7 of the filter U4 is connected with one end of the capacitor C7 and then connected with a power supply 5V, and the other end of the capacitor C7 is grounded; One end of the resistor R21 is connected with one end of the resistor R22, the other end of the resistor R21 is connected with a power supply 3.3V, the other end of the resistor R22 is grounded, the 4 pin of the comparator U5 is connected with one ends of the resistors R19 and R20, the other end of the resistor R20 is connected with the power supply 3.3V, the other end of the resistor R19 is connected with the capacitor C10 and then grounded, the 5 pin of the comparator U5 is connected with one end of the capacitor C9 and then connected with the power supply 5V, and the 2 pin of the comparator U5 is connected with the other end of the capacitor C9 and then grounded;
The bus exchange module comprises a relay JD1, resistors R23 and R24, a MOS tube Q1, a diode D1 and a light-emitting diode LED1; the three-phase power supply is characterized in that a6 pin of the relay JD1 is connected with the other end of the fuse F1, a3 pin of the relay JD1 is connected with the other end of the fuse F2, the 2,4, 5 and 7 pins of the relay JD1 are connected with the chip to be tested, the 1 pin of the relay JD1 is connected with the cathode of the diode D1 and one end of the resistor R24 and then connected with the power supply 5V, the other end of the resistor R24 is connected with the anode of the light emitting diode LED1, the cathode of the light emitting diode LED1 is connected with the anode of the diode D1, the 8 pin of the relay JD1 and the drain electrode of the MOS tube Q1, the grid electrode of the MOS tube Q1 is connected with one end of the resistor R23 and then connected with the single chip microcomputer, and the source electrode of the MOS tube Q1 is connected with the other end of the resistor R23 and then grounded.
2. A detonator chip testing method, characterized in that a detonator chip testing system as claimed in claim 1 is employed; the method comprises the following steps:
Transmitting a test instruction to at least one chip to be tested according to the acquired operation instruction, and determining a test parameter according to response information of the chip to be tested; the test parameters comprise communication detection parameters, current detection parameters and frequency detection parameters;
judging whether the test of the chip to be tested is qualified or not based on the comparison of the test parameters and preset conditions;
and obtaining a branch pipe signal according to the judging result, and sorting and storing the branch pipe signal according to the yield.
3. The detonator chip testing method of claim 2 wherein: determining the test parameters comprises the steps of:
s1.1, before testing, binding a chip type template to be tested by a data service platform, and calling the template by an upper computer;
S1.2, an upper computer issues an operation instruction to test equipment, and the communication, current and frequency function test is carried out on the chip to be tested according to the test instruction;
And S1.3, after the test is completed, sending the test result parameters to the upper computer.
4. A detonator chip testing method as claimed in claim 3 wherein: judging whether the chip to be tested is qualified or not comprises the following steps:
S2.1, comparing the test result parameters with the templates called in the upper computer;
s2.2, if the conditions are met, judging that the chip to be tested is qualified in test; if the conditions are not met, judging that the chip to be tested is unqualified, and issuing a pipe distributing signal to a sorting machine, wherein the sorting machine sorts and stores the chip to be tested according to the judging results of communication, current and frequency tests.
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| CN113552467A (en) * | 2021-06-28 | 2021-10-26 | 苏州裕太微电子有限公司 | Device and method for testing functions of chip system |
| CN115032523A (en) * | 2022-06-07 | 2022-09-09 | 浙江光特科技有限公司 | Chip automatic test method, system, computer equipment and storage medium |
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| CN112416676A (en) * | 2020-11-18 | 2021-02-26 | 上海磐启微电子有限公司 | Testing tool applied to testing chip |
| CN112612661B (en) * | 2020-12-17 | 2022-08-23 | 海光信息技术股份有限公司 | Chip system level test method, device and system |
| CN115752125A (en) * | 2022-11-23 | 2023-03-07 | 无锡盛景微电子股份有限公司 | Controllable voltage regulating circuit, method and test system for detonator test |
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| CN115032523A (en) * | 2022-06-07 | 2022-09-09 | 浙江光特科技有限公司 | Chip automatic test method, system, computer equipment and storage medium |
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