CN211508611U

CN211508611U - Controllable surge suppression circuit

Info

Publication number: CN211508611U
Application number: CN201922369324.3U
Authority: CN
Inventors: 麻海峰
Original assignee: Luoyang Longsheng Technology Co Ltd
Current assignee: Luoyang Longsheng Technology Co Ltd
Priority date: 2019-12-26
Filing date: 2019-12-26
Publication date: 2020-09-15
Anticipated expiration: 2029-12-26

Abstract

When an overvoltage surge is input into the controllable surge suppression circuit, the first voltage-regulator tube V4 is in a voltage-regulated state, surge voltage is absorbed by the MOS tube, and VOUT = V4-V5_G‑SThe output voltage can be clamped to the normal input voltage range of the back-end component. GS voltage of the MOS tube is controlled through the high/low level of TTL, so that the MOS tube is controlled to be switched on and off, and switching control is achieved. The circuit has the advantages of simple structure, low cost, flexible use, controllable switch, reliable work and wide application prospect in the aspect of surge suppression.

Description

Controllable surge suppression circuit

Technical Field

The utility model relates to a controllable surge suppression circuit.

Background

And if the airborne power supply meets the requirement of the power supply characteristic of the airplane, a GJB181 (A/B) power supply characteristic test is carried out. Wherein the voltage transient test requires that the power supply be capable of operating normally or not being damaged when an overvoltage surge is input.

If the surge suppression circuit is not provided, the back-end component does not work or is damaged if the working voltage of the back-end component is lower than the surge voltage when the overvoltage surge is input. After the surge suppression circuit is added, the input overvoltage surge can be clamped in a certain voltage range, so that end components are protected and are not damaged by overvoltage. The technical scheme of surge suppression in the prior art has the defects of complex structure, uncontrollable switch and high cost.

Disclosure of Invention

In order to solve the above problems, it is an object of the present invention to provide a controllable surge suppression circuit, which can clamp an input voltage and protect a rear-end element device when an overvoltage surge is input; and the switching operation can be carried out according to the TTL level. In order to achieve the purpose, the utility model adopts the following technical scheme:

a controllable surge suppression circuit comprises a three-terminal adjustable reference source N1, a 555 timer N2, a first diode V1, a photoelectric coupler V2, a second diode V3, a first voltage stabilizing diode V4, an MOS transistor V5, a third diode V6, a fourth diode V7, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a direct current input +28V, a direct current input +28VG, a TTL-and an output OUT;

a 1 end of a fourth resistor R4, a 1 end of a fifth resistor R5 and a D end of an MOS tube V5 are connected with a direct current input +28V end, an anode of a first diode V1 is connected with a 2 end of the fourth resistor R4, a cathode of a first diode V1 is connected with a 1 end of the first resistor R1, a 1 end of a three-end adjustable reference source N1, a 1 end of a first capacitor C1 and

pins

4 and 8 of a 555 timer N2, a 2 end of the first resistor R1, a 1 end of a second resistor R2 are connected with a reference end 3 of the three-end adjustable reference source N1, a 2 end of the fifth resistor R5 is connected with a cathode of a first voltage stabilizing diode V4, a cathode of a third diode V6 and an 8 end of a photocoupler V5, an anode of the first voltage stabilizing diode V4 is connected with an anode of a second diode V3, a G5 end of the MOS tube V5 is connected with a rear end of the MOS tube V6, a rear end of the MOS tube V596 and a timing capacitor V596, a timing end of the fourth resistor V596 and a timing end 6866 are connected with a 1 end of the fourth, A 2 terminal of an eighth resistor R8 and a 2 terminal of a ninth resistor R9 are connected, a 1 terminal of an eighth resistor R8 is connected with an 8 terminal of a 555 timer N2, a 7 terminal of a 555 timer N2 is connected with a 1 terminal of a ninth resistor R9, a 5 terminal of the 555 timer N2 is connected with a third capacitor C3 in series and then connected with a direct current input +28VG, a 3 terminal of the 555 timer N2 is connected with a seventh resistor R7 in series and a second capacitor C2 in series and then connected with a cathode of a fourth diode V7 and an anode of a third diode V6, and an anode of the fourth diode V7, a 5 terminal of a photocoupler V2 and an S terminal of an MOS transistor V5 are connected with an output OUT; the direct current input +28VG is connected with a second resistor R2, the 2 end of a three-section adjustable reference source N1, the 2 end of a first capacitor C1, the cathode of a second diode V3, the 1 end of a 555 timer N2 and the 2 end of a fourth capacitor C4, the TTL + is connected with the 2 end of a photoelectric coupler V2 after being connected with a third resistor R3 in series, and the TTL-is connected with the 3 end of the photoelectric coupler V2.

The model of the 555 timer N2 is NE555, the model of the photoelectric coupler V2 is TLP250, the models of the diodes V1, V3, V6 and V7 are 1N4007, the model of the MOS tube V5 is IRFP260, and the model of the three-section adjustable reference source N1 is TL 431.

Due to the adoption of the technical scheme, the utility model discloses have following superiority:

when an overvoltage surge is input into the controllable surge suppression circuit, the first voltage-stabilizing tube V4 is in a voltage-stabilizing state, surge voltage is absorbed by the MOS tube, and VOUT = V4-V5_G-SThe output voltage can be clamped to the normal input voltage range of the back-end component. GS voltage of the MOS tube is controlled through the high/low level of TTL, so that the MOS tube is controlled to be switched on and off, and switching control is achieved. The circuit has the advantages of simple structure, low cost, flexible use, controllable switch, reliable work and wide application prospect in the aspect of surge suppression.

Drawings

Fig. 1 is a schematic diagram of the controllable surge suppression circuit of the present invention.

Detailed Description

The technical solution of the present invention will be further described in detail with reference to the accompanying drawings and examples.

The controllable surge suppression circuit comprises a three-terminal adjustable reference source N1, a 555 timer N2, a first diode V1, a photoelectric coupler V2, a second diode V3, a first voltage stabilizing diode V4, an MOS transistor V5, a third diode V6, a fourth diode V7, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a direct current input +28V, a direct current input +28VG, a TTL +, TTL-and an output OUT;

pins

The utility model discloses controllable surge suppression circuit's theory of operation: an input +28V source is led into the three-section adjustable reference source N1 under the action of the fourth resistor R4 and the first diode V1, the output of the three-section adjustable reference source N1 is set in the normal input range of the 555 timer N2 under the action of the first resistor R1 and the second resistor R2, filtering is carried out through the first capacitor C1, and power is supplied to the 555 timer N2. The 555 timer N2 is set as an astable trigger through a ninth resistor R9, a fourth capacitor C4, a third capacitor C3 and an eighth resistor R8, outputs an oscillating square wave through the 3 end of the 555 timer N2, and forms a steady trigger level through the action of a seventh resistor R7, the second capacitor C2 and a third diode V6. After the trigger level is connected to the fifth resistor R5 and the first voltage regulator tube V4, the trigger level is connected to the 8 end of the photoelectric coupler V2, the G end of the MOS tube V5 is connected to the 6 end and the 7 end of the photoelectric coupler V2, and the S end of the MOS tube V5 is connected to the 5 end of the photoelectric coupler V2. By the characteristics of the photocoupler TLP250, the

output terminals

5 and 6, 7 are turned on when the input terminals are not conductive, and the

output terminals

8 and 6, 7 are turned on when the input terminals are conductive. When TTL is high level, the input end of the photoelectric coupler V2 is conducted, the

output ends

6, 7 and 8 are conducted, G of the MOS transistor V5 is connected to the trigger level, and the MOS transistor V5 is conducted; when TTL is low level, the input end of the photoelectric coupler V2 is not conducted, the

output ends

5, 6 and 7 are conducted, G and S of the MOS tube V5 are conducted, namely, the grid voltage is rapidly discharged, and the MOS tube V5 is disconnected.

When the power supply input voltage is in a normal power supply range, the first voltage-regulator tube V4 is in a cut-off state; when overvoltage surge is input, the first voltage-regulator tube V4 enters a voltage-stabilizing state, input surge voltage is absorbed by the MOS tube V5 under the combined action of the voltage-regulator tube and the MOS tube V5, most of the surge voltage is applied between DS of the MOS tube V5, and output OUT is equal to the voltage-stabilizing value of the first voltage-regulator tube V4 minus the GS voltage value of the MOS tube V5. The clamped output voltage value can be set by replacing the voltage stabilizing value of the first voltage stabilizing tube V4.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A controllable surge suppression circuit, comprising: the circuit comprises a three-terminal adjustable reference source N1, a 555 timer N2, a first diode V1, a photoelectric coupler V2, a second diode V3, a first voltage stabilizing diode V4, an MOS tube V5, a third diode V6, a fourth diode V7, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a direct current input +28V, a direct current input +28VG, a TTL-terminal and an output OUT;

a 1 end of a fourth resistor R4, a 1 end of a fifth resistor R5 and a D end of an MOS tube V5 are connected with a direct current input +28V end, an anode of a first diode V1 is connected with a 2 end of the fourth resistor R4, a cathode of a first diode V1 is connected with a 1 end of the first resistor R1, a 1 end of a three-end adjustable reference source N1, a 1 end of a first capacitor C1 and pins 4 and 8 of a 555 timer N2, a 2 end of the first resistor R1, a 1 end of a second resistor R2 are connected with a reference end 3 of the three-end adjustable reference source N1, a 2 end of the fifth resistor R5 is connected with a cathode of a first voltage stabilizing diode V4, a cathode of a third diode V6 and an 8 end of a photocoupler V5, an anode of the first voltage stabilizing diode V4 is connected with an anode of a second diode V3, a G5 end of the MOS tube V5 is connected with a rear end of the MOS tube V6, a rear end of the MOS tube V596 and a timing capacitor V596, a timing end of the fourth resistor V596 and a timing end 6866 are connected with a 1 end of the fourth, A 2 terminal of an eighth resistor R8 and a 2 terminal of a ninth resistor R9 are connected, a 1 terminal of an eighth resistor R8 is connected with an 8 terminal of a 555 timer N2, a 7 terminal of a 555 timer N2 is connected with a 1 terminal of a ninth resistor R9, a 5 terminal of the 555 timer N2 is connected with a third capacitor C3 in series and then connected with a direct current input +28VG, a 3 terminal of the 555 timer N2 is connected with a seventh resistor R7 in series and a second capacitor C2 in series and then connected with a cathode of a fourth diode V7 and an anode of a third diode V6, and an anode of the fourth diode V7, a 5 terminal of a photocoupler V2 and an S terminal of an MOS transistor V5 are connected with an output OUT; the direct current input +28VG is connected with a second resistor R2, the 2 end of a three-section adjustable reference source N1, the 2 end of a first capacitor C1, the cathode of a second diode V3, the 1 end of a 555 timer N2 and the 2 end of a fourth capacitor C4, the TTL + is connected with the 2 end of a photoelectric coupler V2 after being connected with a third resistor R3 in series, and the TTL-is connected with the 3 end of the photoelectric coupler V2.

2. A controllable surge suppression circuit according to claim 1, wherein: the model of the 555 timer N2 is NE555, the model of the photoelectric coupler V2 is TLP250, the models of the diodes V1, V3, V6 and V7 are 1N4007, the model of the MOS tube V5 is IRFP260, and the model of the three-section adjustable reference source N1 is TL 431.