CN211454280U - Analog key circuit and key control device - Google Patents
Analog key circuit and key control device Download PDFInfo
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- CN211454280U CN211454280U CN201922162874.8U CN201922162874U CN211454280U CN 211454280 U CN211454280 U CN 211454280U CN 201922162874 U CN201922162874 U CN 201922162874U CN 211454280 U CN211454280 U CN 211454280U
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Abstract
An analog key circuit and a key control device comprise a single chip microcomputer and a key module, wherein the key module comprises n keys, a first resistor, a second resistor, a capacitor, a third resistor and n fourth resistors; the first end of the analog digital signal IO port of the single chip microcomputer is positioned in the single chip microcomputer, and the second end of the analog digital signal IO port of the single chip microcomputer is connected with one end of a first resistor; the other end of the first resistor is respectively connected with one end of a second resistor R28 and the first ends of the n keys; a second resistor is connected with a capacitor in parallel; the other end of the second resistor is grounded; one end of the third resistor is grounded; the second end of the 1 st key is respectively connected with the other end of the third resistor and one end of the 1 st fourth resistor; the second end of the nth key is respectively connected with the other end of the (n-1) th fourth resistor and one end of the nth fourth resistor; the other end of the nth fourth resistor is connected with a power supply. The utility model discloses singlechip IO mouth resource has been practiced thrift.
Description
[ technical field ] A method for producing a semiconductor device
The utility model belongs to the technical field of electronic equipment, concretely relates to simulation keying circuit and button control device.
[ background of the invention ]
The existing single chip microcomputer is connected with the keys by connecting each I/O port with 1 key, and the mode consumes more IO ports.
As shown in FIG. 1, the MCU S3F8S45MCU I/O internal level is set to be pulled high, the button is pressed to pull the level of the S3F8S45MCU I/O port low, the S3F8S45MCU is pressed when the button is judged to be pulled low, when the button is released, the I/O port is changed to be high level, and the S3F8S45MCU is judged to be released.
When the DOWN key is pressed, the I/O (P4.5) of the S3F8S45MCU is grounded, the level is pulled low, and the S3F8S45MCU determines that the key is pressed. When the key DOWN is released, the I/O port (P4.5) of the S3F8S45MCU is disconnected with the ground, the level is pulled high, and the S3F8S45MCU judges that the key is released.
When the UP key is pressed, the I/O (P4.6) of the S3F8S45MCU is grounded, the level is pulled low, and the S3F8S45MCU judges that the key is pressed. When the key UP is released, the I/O port (P4.6) of the S3F8S45MCU is disconnected with the ground, the level is pulled high, and the S3F8S45MCU judges that the key is released.
When the key is pressed, the I/O (P3.0) of the S3F8S45MCU is grounded, the level is pulled low, and the S3F8S45MCU judges that the key is pressed. When the key ON/OFF is released, the I/O port (P3.0) of the S3F8S45MCU is disconnected from the ground, the level is pulled high, and the S3F8S45MCU judges that the key is released.
When the key TIME is pressed, the I/O (P3.1) of the S3F8S45MCU is grounded, the level is pulled low, and the S3F8S45MCU judges that the key is pressed. When the key TIME is released, the I/O port (P3.1) of the S3F8S45MCU is disconnected with the ground, the level is pulled high, and the S3F8S45MCU judges that the key is released.
When the key MODE is pressed, the I/O (P3.2) of the S3F8S45MCU is grounded, the level is pulled low, and the S3F8S45MCU judges that the key is pressed. When the key MODE is released, the I/O port (P3.2) of the S3F8S45MCU is disconnected with the ground, the level is pulled high, and the S3F8S45MCU judges that the key is released.
The keying circuit in the prior art needs to use a plurality of I/Os of the S3F8S45MCU, occupies pin resources of the S3F8S45MCU, and when a plurality of keys are needed, the condition that I/O port resources are insufficient occurs.
[ Utility model ] content
The utility model discloses one of the technical problem that will solve lies in providing a practice thrift the simulation keying circuit of singlechip pin resource.
The second technical problem to be solved in the present invention is to provide a key control device for saving pin resources of a single chip microcomputer.
The utility model discloses a realize like this:
an analog key circuit comprises a singlechip and a key module,
the single chip microcomputer comprises an analog digital signal IO port for receiving a key instruction;
the key module comprises n keys, a first resistor (R29), a second resistor (R28), a capacitor (C10), a third resistor (R27) and n fourth resistors; wherein n is a natural number;
the first end of the analog-digital signal IO port is positioned in the single chip microcomputer, and the second end of the analog-digital signal IO port is connected with one end of the first resistor (R29);
the other end of the first resistor (R29) is respectively connected with one end of the second resistor (R28) and the first ends of the n keys;
the second resistor (R28) is connected in parallel with the capacitor (C10); the other end of the second resistor (R28) is grounded;
one end of the third resistor (R27) is grounded;
the second end of the 1 st key is respectively connected with the other end of the third resistor (R27) and one end of the 1 st fourth resistor;
the second end of the 2 nd key is respectively connected with the other end of the 1 st fourth resistor and one end of the 2 nd fourth resistor;
the second end of the nth key is respectively connected with the other end of the (n-1) th fourth resistor and one end of the nth fourth resistor;
the other end of the nth fourth resistor is connected with a power supply.
Further, the single chip microcomputer is S3F8S45 MCU.
A key control device comprises the analog key circuit.
The utility model has the advantages that: the utility model discloses an analog key circuit only needs the IO mouth to an S3F8S45MCU, has practiced thrift S3F8S45 MCU' S IO mouth resource. When more keys need to be added, I/O ports to multiple S3F8S45 MCUs need not be occupied.
[ description of the drawings ]
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a prior art key circuit structure.
Fig. 2 is a schematic diagram of the key circuit structure of the present invention.
[ detailed description ] embodiments
Referring to fig. 2, the present invention provides an analog key circuit, which includes an S3F8S45MCU monolithic computer 1 and a key module 2.
And the AD port (P0.7) of the MCU singlechip 1 of the S3F8S45 is used for receiving a key instruction.
The key module 2 comprises 5 keys ON, UP +, MODE, DOWN-, TIME/FR, a first resistor R29(1K), a second resistor R28(1M), a capacitor C10(100nF), a third resistor R27(3K), a fourth resistor R26(10K), R25(5.1K), R24(13K), R23(20K), and R22 (1K).
The first end of the AD port (P0.7) of the S3F8S45MCU singlechip 1 is positioned in the singlechip, and the second end is connected with one end of a first resistor R29.
The other end of the first resistor R29 is respectively connected with one end of the second resistor R28 and the first ends of the 5 keys;
the second resistor R28 is connected with the capacitor C10 in parallel; the other end of the second resistor R28 is grounded;
one end of the third resistor R27 is grounded;
the second end of the 1 st key ON is respectively connected with the other end of the third resistor R27 and one end of the 1 st fourth resistor R26;
the second end of the 2 nd key UP + is respectively connected with the other end of the 1 st fourth resistor R26 and one end of the 2 nd fourth resistor R25;
the second end of the 3 rd key MODE is respectively connected with the other end of the 2 nd fourth resistor R26 and one end of the 3 rd fourth resistor R24;
the second end of the 4 th key DOWN-is respectively connected with the other end of the 3 rd fourth resistor R26 and one end of the 4 th fourth resistor R23;
the second end of the 5 th key TIME/FR is respectively connected with the other end of the 4 th fourth resistor and one end of the 5 th fourth resistor R22;
the other end of the 5 th fourth resistor R22 is connected with a 5V power supply.
The utility model discloses utilize the analog digital signal mouth of singlechip, analog voltage signal among the acquisition circuit, according to the different judgement of voltage which button is pressed.
When the key ON is pressed, the voltage value is 0.29V, and the AD port (P0.7) of the S3F8S45MCU collects and processes the voltage value and then judges that the voltage value is the key ON; when the key ON is released, the voltage value is 0V, the I/O port (P0.7) of the S3F8S45MCU collects and processes the voltage value and then judges that the voltage value is the key ON release;
when the key UP + is pressed down, the voltage value is 1.24V, and the AD port (P0.7) of the S3F8S45MCU collects and processes the voltage value and then judges that the voltage value is the key UP + pressed down; when the key UP + is released, the voltage value is 0V, and the acquisition and processing of an I/O port (P0.7) of the S3F8S45MCU then judges that the voltage value is the key UP + released;
when a key MODE is pressed, the voltage value is 1.72V, the AD port (P0.7) of the S3F8S45MCU collects and processes the voltage value and then judges that the voltage value is that the key MODE is pressed; when the key MODE is released, the voltage value is 0V, the I/O port (P0.7) of the S3F8S45MCU is used for collecting and processing, and then the voltage value is judged to be the key MODE release;
when the key DOWN is pressed, the voltage value is 2.95V, and the AD port (P0.7) of the S3F8S45MCU collects and processes the voltage value and then judges that the voltage value is the key DOWN; when the key is DOWN-released, the voltage value is 0V, and the I/O port (P0.7) of the S3F8S45MCU collects and processes the voltage value and then judges that the voltage value is the key DOWN-released;
when the key TIME/FR is pressed down, the voltage value is 4.89V, the AD port (P0.7) of the S3F8S45MCU collects and processes the voltage value and then judges that the voltage value is the key TIME/FR pressed down; when the key TIME/FR is released, the voltage value is 0V, the I/O port (P0.7) of the MCU S3F8S45 collects and processes the voltage value and then judges that the voltage value is the key TIME/FR released.
The utility model also provides a key control device, include as above simulation keying circuit.
The utility model discloses an analog key circuit only needs the IO mouth to an S3F8S45MCU, has practiced thrift S3F8S45 MCU' S IO mouth resource. When more keys need to be added, I/O ports to multiple S3F8S45 MCUs need not be occupied.
Although specific embodiments of the present invention have been described, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the claims appended hereto.
Claims (3)
1. The utility model provides an analog key circuit, includes singlechip and button module, its characterized in that:
the single chip microcomputer comprises an analog digital signal IO port for receiving a key instruction;
the key module comprises n keys, a first resistor (R29), a second resistor (R28), a capacitor (C10), a third resistor (R27) and n fourth resistors; wherein n is a natural number;
the first end of the analog-digital signal IO port is positioned in the single chip microcomputer, and the second end of the analog-digital signal IO port is connected with one end of the first resistor (R29);
the other end of the first resistor (R29) is respectively connected with one end of the second resistor (R28) and the first ends of the n keys;
the second resistor (R28) is connected in parallel with the capacitor (C10); the other end of the second resistor (R28) is grounded;
one end of the third resistor (R27) is grounded;
the second end of the 1 st key is respectively connected with the other end of the third resistor (R27) and one end of the 1 st fourth resistor;
the second end of the 2 nd key is respectively connected with the other end of the 1 st fourth resistor and one end of the 2 nd fourth resistor;
the second end of the nth key is respectively connected with the other end of the (n-1) th fourth resistor and one end of the nth fourth resistor;
the other end of the nth fourth resistor is connected with a power supply.
2. The analog keying circuit of claim 1, wherein: the type of the single chip microcomputer is S3F8S45 MCU.
3. A key control device is characterized in that: comprising an analog key circuit as claimed in claim 1 or 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922162874.8U CN211454280U (en) | 2019-12-06 | 2019-12-06 | Analog key circuit and key control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922162874.8U CN211454280U (en) | 2019-12-06 | 2019-12-06 | Analog key circuit and key control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211454280U true CN211454280U (en) | 2020-09-08 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922162874.8U Expired - Fee Related CN211454280U (en) | 2019-12-06 | 2019-12-06 | Analog key circuit and key control device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211454280U (en) |
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2019
- 2019-12-06 CN CN201922162874.8U patent/CN211454280U/en not_active Expired - Fee Related
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| Date | Code | Title | Description |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20200908 Termination date: 20201206 |