CN203574628U - Button expansion circuit - Google Patents

Abstract

The utility model discloses a button expansion circuit comprising a processor, the processor is provided with n external input interfaces, wherein n>=2; the button expansion circuit also comprises X buttons, wherein n<X<=C<n><1>+C<n><2>+...C<n><n-1>+C<n><n>; ends of n buttons of the X buttons are respectively connected to the n external input interfaces in a one to one correspondence manner; a number a of external input interfaces are selected in the n external input interfaces at will to form a set, b sets are selected in all, the b sets of external input interfaces are not completely identical to one another, wherein 1<=b<=C<n><a>, 2<=a<=n, one or more a can be selected, wherein the number a of external input interfaces in each set of external input interfaces are respectively connected to cathodes of a number a of diodes in a one to one correspondence manner, anodes of the number a of diodes are connected to one end of any button in the X buttons except for selected n buttons, and the other ends of the X buttons are connected to a power supply. According to the utility model, more buttons can be expanded by means of fewer external input interfaces, the response speed of the processor is accelerated, and the cost of the processor is relatively low.

Description

Button expanded circuit

Technical field

The utility model relates to a kind of for MCU(microcontroller) the button expanded circuit of/CPU (central processing unit)/processor systems such as single-chip microcomputer.

Background technology

Existing button expanded circuit has several as follows conventionally:

(1), the corresponding button of each outer input interface (IO): sort circuit takies maximum IO interfaces, does not realize expanded function, more to the outer input interface resource requirement of processor.

(2), the button of matrix-scanning mode expansion; The shortcoming of sort circuit is that the response speed of processor is slow, and multiple buttons there will be the judgement of mistake simultaneously or cannot judge while pressing, and the workload of software is larger simultaneously, and needs the interface of two types of input and output simultaneously.

(3) use analog input interface direct-detection button; The shortcoming of sort circuit is to need software to do a large amount of computing work, when processor is busy, cannot respond in time, and the quantity of button expansion depends on the precision of analog input interface, higher to the requirement of processor simulation input interface, cause the price comparison of processor high.

Utility model content

Technical problem to be solved in the utility model is to provide and can use less outer input interface to expand more button, and make processor response speed very fast, the lower-cost button expanded circuit of processor.

For solving the problems of the technologies described above, the button expanded circuit that the utility model provides, it comprises processor, processor is provided with n outer input interface, wherein n >=2; It is characterized in that:

It also comprises X button, wherein $n<X\&le;{\mathrm{<figure-callout\; id="1"\; label="C\; n"\; filenames="131209095316.png"\; state="\{\{state\}\}">C</figure-callout>}}_n^{}+{\mathrm{<figure-callout\; id="2"\; label="C\; n"\; filenames="131209095316.png"\; state="\{\{state\}\}">C</figure-callout>}}_n^{}+...+C_n^{n-1}+C_n^n;$

One end of n button in X button is connected to respectively n outer input interface one to one;

In n outer input interface, choosing arbitrarily a is one group, altogether chooses b group, and b group outer input interface is incomplete same each other, wherein 2≤a≤n, a can choose one or more, wherein a outer input interface in any one group of outer input interface is connected to respectively the negative pole of a diode one to one, the positive pole of a diode is all connected to the one end of removing any one button of selected n button in X button, and the other end of a described X button is all connected to power supply.

Adopt after above structure, the utility model compared with prior art, has advantages of following:

The utility model utilizes the unilateral conduction of diode, use little outer input interface just can realize the expansion of more button, diode plays the signal between two buttons of isolation, and software algorithm of the present utility model is very simple, can make processor respond in time, make processor response speed very fast, and processor be there is no to a requirement of analog input interface, can reduce the requirement of processor, the price of processor is reduced, make processor cost lower.

As improvement, described $X={\mathrm{<figure-callout\; id="1"\; label="C\; n"\; filenames="131209095316.png"\; state="\{\{state\}\}">C</figure-callout>}}_n^{}+{\mathrm{<figure-callout\; id="2"\; label="C\; n"\; filenames="131209095316.png"\; state="\{\{state\}\}">C</figure-callout>}}_n^{}+...+C_n^{n-1}+C_n^n,b=C_n^a,$ a={2，3，.......，n}。Now, in the certain situation of outside output interface, can expand maximum buttons.

Accompanying drawing explanation

Fig. 1 is the structural representation of the utility model embodiment mono-.

Fig. 2 is the structural representation of the utility model embodiment bis-.

Embodiment

Below in conjunction with the drawings and specific embodiments, the utility model is described in more detail.

Embodiment mono-,

As shown in Figure 1, in the present embodiment, the outer input interface of processor is 3, be respectively IO1, IO2 and IO3, button is 7, is respectively S1, S2, S3, S4, S5, S6 and S7, diode is 9, is respectively D1, D2, D3, D4, D5, D6, D7, D8 and D9.

One end of button S1, S2 and S3 is connected to respectively outer input interface IO1, IO2 and IO3 one to one, that is to say that one end of S1 is connected to IO3, and one end of S2 is connected to IO2, and one end of S3 is connected to IO1.

In 3 outer input interfaces, choosing arbitrarily two is one group, altogether choose 3 groups, 3 groups of outer input interfaces are incomplete same each other, that is to say that IO1 and IO2 are one group, IO1 and IO3 are one group, IO2 and IO3 are one group, IO1 is connected with the negative pole of D1, the positive pole of D1 is connected with one end of S4, IO2 is connected with the negative pole of D2, the positive pole of D2 is connected with one end of S4, IO1 is connected with the negative pole of D3, the positive pole of D3 is connected with one end of S5, IO3 is connected with the negative pole of D4, the positive pole of D4 is connected with one end of S5, IO2 is connected with the negative pole of D5, the positive pole of D5 is connected with one end of S6, IO3 is connected with the negative pole of D6, the positive pole of D6 is connected with one end of S6.

It is one group that 3 outer input interfaces are chosen 3, that is to say that IO1, IO2 and IO3 are one group, IO1 is connected with the negative pole of D7, the positive pole of D7 is connected with one end of S7, IO2 is connected with the negative pole of D8, the positive pole of D8 is connected with one end of S7, and IO3 is connected with the negative pole of D9, and the positive pole of D9 is connected with one end of S7.

The other end of described S1, S2, S3, S4, S5, S6 and S7 is all connected to 3V3 power supply.

Embodiment bis-,

As shown in Figure 2, in the present embodiment, the outer input interface of processor is 3, is respectively IO1, IO2 and IO3, and button is 6, is respectively S1, S2, S3, S4, S5 and S6, and diode is 7, is respectively D1, D2, D3, D4, D5, D6 and D7.

One end of button S1, S2 and S3 is connected to respectively outer input interface IO1, IO2 and IO3 one to one, that is to say that one end of S1 is connected to IO3, and one end of S2 is connected to IO2, and one end of S3 is connected to IO1.

In 3 outer input interfaces, choosing arbitrarily two is one group, altogether chooses 2 groups, and 2 groups of outer input interfaces are incomplete same each other, that is to say that IO1 and IO2 are one group, IO1 and IO3 are one group, and IO1 is connected with the negative pole of D1, and the positive pole of D1 is connected with one end of S4, IO2 is connected with the negative pole of D2, the positive pole of D2 is connected with one end of S4, and IO1 is connected with the negative pole of D3, and the positive pole of D3 is connected with one end of S5, IO3 is connected with the negative pole of D4, and the positive pole of D4 is connected with one end of S5.

It is one group that 3 outer input interfaces are chosen 3, that is to say that IO1, IO2 and IO3 are one group, IO1 is connected with the negative pole of D5, the positive pole of D5 is connected with one end of S6, IO2 is connected with the negative pole of D6, the positive pole of D6 is connected with one end of S6, and IO3 is connected with the negative pole of D7, and the positive pole of D7 is connected with one end of S6.

The other end of described S1, S2, S3, S4, S5 and S6 is all connected to 3V3 power supply.

According to the method described above, 4 outer input interfaces can be extended at most 15 buttons, when 4 outer input interfaces are extended to 15 buttons, wherein 4 each corresponding buttons that directly connect of outer input interface, at this moment expand 4 buttons, then a={2,3,4}

that is to say, during a=2,

at this moment expand 6 buttons, during a=3,

at this moment expand 4 buttons, during a=4,

at this moment expand 1 button, according to the above, the in the situation that of 4 outer input interfaces, can expand at most 15 buttons, also can reduce as required the button of respective numbers.

In like manner, 5 outer input interfaces can be extended at most 31 buttons, can use less outer input interface to expand more button, and software algorithm are simple, processor fast response time by the utility model.

Claims (2)

1. a button expanded circuit, it comprises processor, processor is provided with n outer input interface, wherein n >=2; It is characterized in that:

It also comprises X button, wherein $n<X\&le;C_n^1+C_n^2+...+C_n^{n-1}+C_n^n;$

One end of n button in X button is connected to respectively n outer input interface one to one;

In n outer input interface, choosing arbitrarily a is one group, altogether chooses b group, and b group outer input interface is incomplete same each other, wherein

2≤a≤n, a can choose one or more, wherein a outer input interface in any one group of outer input interface is connected to respectively the negative pole of a diode one to one, the positive pole of a diode is all connected to the one end of removing any one button of selected n button in X button, and the other end of a described X button is all connected to power supply.

2. button expanded circuit according to claim 1, is characterized in that:

Described $X=C_n^1+C_n^2+...+C_n^{n-1}+C_n^n,b=C_n^a,$ a={2，3，.......，n}。

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