CN211265447U - Package body - Google Patents

Package body Download PDF

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Publication number
CN211265447U
CN211265447U CN202020460756.5U CN202020460756U CN211265447U CN 211265447 U CN211265447 U CN 211265447U CN 202020460756 U CN202020460756 U CN 202020460756U CN 211265447 U CN211265447 U CN 211265447U
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China
Prior art keywords
lead frame
chip
layer
package
metal layer
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CN202020460756.5U
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Chinese (zh)
Inventor
阳小芮
董美丹
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Shanghai Kaihong Electronic Co Ltd
Diodes Shanghai Co Ltd
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Diodes Shanghai Co Ltd
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Priority to CN202020460756.5U priority Critical patent/CN211265447U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

The utility model provides a packaging body, includes lead frame and chip, wherein, the lead frame includes base island and pin, the chip set up in the lead frame on the base island. The chip comprises a plurality of bonding pads, each bonding pad corresponds to one pin of the lead frame, and each bonding pad of the chip is directly and electrically connected with the corresponding pin of the lead frame through a conducting layer. The problem that the design of the conductive layer cannot be used at present due to the fact that the conductive layer is too small is solved, and the operation energy efficiency of the packaging body which can only use closely-arranged bonding wires due to the fact that the conductive layer is too small is greatly simplified.

Description

Package body
Technical Field
The utility model relates to a semiconductor encapsulation field, in particular to packaging body.
Background
The packaged product is usually formed by mounting a chip on a lead frame and encapsulating the chip with a molding compound.
Currently, in view of cost, efficiency, electrical parameters, heat dissipation, high frequency parameters, etc., there is a package body that replaces the traditional wire bonding process with a conductive sheet (or conductive layer), especially a copper sheet welding process. Copper sheets are typically formed and cut using a copper sheet die and then attached to the chip and lead frame using additional processes. However, as the functions of the chip are improved, the design of the copper sheets becomes more and more complex, so that the design size of the copper sheets and the space between the copper sheets become smaller and smaller.
However, due to the design and manufacturing limitations of the mold, some small-sized copper sheets or designs with small copper sheet pitches are difficult to manufacture due to the limitations of the mechanical structure, and thus the copper sheets cannot be manufactured.
Therefore, the existing process technology causes that some packages have to use large-area densely-arranged bonding wires to replace the copper sheets because the formation of the copper sheets can not be realized actually, thereby not only reducing the operation energy efficiency, but also influencing the product performance.
Therefore, there is a need to provide a new packaging method and a package obtained by applying the new packaging method to overcome the above-mentioned drawbacks.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a packaging body and packaging method through directly forming patterned conducting layer in packaging process to solve the problem that the small-size conducting layer can't be made because of die design's restriction or conducting layer self mechanical structure's restriction, thereby thoroughly can't use the problem of conducting layer design because of the conducting layer undersize at present, simplified the operation efficiency of the packaging body that can only use closely arranged bonding wire because of the conducting layer undersize greatly.
In order to achieve the above object, according to the utility model discloses an aspect provides a packaging body, including lead frame and chip, wherein, the lead frame includes base island and pin, the chip set up in the lead frame on the base island, the pad of chip through a sheetmetal with the pin electric connection of lead frame.
In an embodiment of the present invention, the metal sheet passes through solder paste and the bonding pad electric connection of the chip.
In an embodiment of the present invention, the metal sheet and the chip are attached to the surface of the base island.
In an embodiment of the present invention, the metal sheet is made of copper.
According to another aspect of the present invention, there is provided a packaging method, including: providing a lead frame, and mounting a chip on the lead frame; packaging the chip for the first time; a step of forming a patterned metal layer; and, a second encapsulation step; in the step of forming the patterned metal layer, a metal sheet is formed to electrically connect the bonding pad of the chip and the lead of the lead frame.
In an embodiment of the present invention, in the step of packaging the chip for the first time, the chip is packaged by the molding compound, and the chip reaches the lead frame, and at least exposes the bonding pad of the chip and the pin of the lead frame.
As can be understood by those skilled in the art, in an embodiment of the present invention, in the step of performing the first packaging on the chip, a plastic package mold is used, so that when the chip and the lead frame are packaged, a bonding pad of the chip and a pin of the lead frame are exposed by a plastic package material; or, in the step of packaging the chip for the first time, a plastic package mold is used, so that when the chip and the lead frame are packaged by the plastic package material, the surface (including the bonding pad) of the chip, which is far away from the base island, and the pins of the lead frame are fully exposed.
In an embodiment of the present invention, in the step of forming the patterned metal layer, a metal layer is first formed, so that the metal layer covers the chip and the lead frame; and then, forming a patterned masking layer on the metal layer, and etching to obtain the patterned metal layer.
As will be appreciated by those skilled in the art, in one embodiment of the present invention, the first and second components may be selected from: and forming a masking layer on the metal layer, and carrying out exposure and development to form the patterned masking layer on the metal layer.
Alternatively, in an embodiment of the present invention, in the step of forming the patterned metal layer, a patterned masking layer is first formed, such that the patterned masking layer covers the chip and the lead region of the lead frame; and then, forming a metal layer to fill the patterned masking layer, and removing the patterned masking layer to obtain the patterned metal layer. It will be appreciated by those skilled in the art that in this step, the patterned masking layer exposes at least the bonding pads of the chip and the leads of the lead frame.
In an embodiment of the present invention, the material of the patterned masking layer is a photosensitive dry film or a photoresist material. It will be understood by those skilled in the art that the photosensitive dry film and the photoresist are commercially available as is conventional in the art.
In an embodiment of the invention, before the step of forming the patterned metal layer, the packaging method further includes: a step of forming a solder paste such that the solder paste covers the exposed pads of the chip and the leads of the lead frame.
In a preferred embodiment of the present invention, there is provided a packaging method, comprising the steps of:
s10: providing a lead frame, and mounting a chip on the lead frame;
s20: packaging for the first time, namely, exposing a bonding pad of the chip and a pin of the lead frame when the chip and the lead frame are packaged by using a plastic package mold;
s30: forming a solder paste so that the solder paste covers the pads of the chip and the leads of the lead frame exposed in step S20;
s41: forming a metal layer covering the chip and the lead frame in the area, i.e., the metal layer covers and contacts the surface of the molding compound formed in the step S20 and the surface of the solder paste formed in the step S30; that is, in this step, the metal layer covers the region where the base island of the lead frame is located and the region where the pin is located;
s42: forming a patterned masking layer on the surface of the metal layer formed in step S41;
s43: etching to obtain a patterned metal layer, wherein the patterned metal layer is electrically connected with the bonding pad of the core and the pin of the lead frame through the solder paste;
s50: and packaging for the second time to package the lead frame, the chip and the patterned metal layer, and cutting and molding to obtain a packaging body.
In a preferred embodiment of the present invention, there is provided a packaging method, comprising the steps of:
s10: providing a lead frame, and mounting a chip on the lead frame;
s20: packaging for the first time, namely, exposing a bonding pad of the chip and a pin of the lead frame by using a plastic package mold when the chip and the lead frame are packaged by using a plastic package material;
s31: vacuum pasting a photosensitive dry film, so that the photosensitive dry film covers the chip and the lead area of the lead frame, that is, the photosensitive dry film covers and contacts the surface of the molding compound formed in the step S20 and the bonding pad of the chip exposed in the step S20;
s32: obtaining a patterned masking layer after exposure and development, so that the patterned masking layer at least exposes the bonding pad of the chip and the pin of the lead frame;
s40: forming a metal layer, filling the patterned masking layer with the metal layer, and removing the patterned masking layer to obtain the patterned metal layer, so that the patterned metal layer is electrically connected with the bonding pad of the core and the pins of the lead frame;
s50: and packaging for the second time to package the lead frame, the chip and the patterned metal layer, and cutting and molding to obtain a packaging body.
In a preferred embodiment of the present invention, there is provided a packaging method, comprising the steps of:
s10: providing a lead frame, and mounting a chip on the lead frame;
s20: packaging for the first time, namely, fully exposing the surface (including a bonding pad) of the chip departing from the base island and pins of the lead frame when the chip and the lead frame are packaged by using a plastic package mold;
s31: forming a metal layer, wherein the metal layer covers the chip and the lead area of the lead frame, namely, the metal layer covers and contacts the surface of the molding compound formed in the step S20, and the exposed surface (including the bonding pad) of the chip, which is far away from the base island, and the lead of the lead frame;
s32: forming a patterned masking layer on the surface of the metal layer formed in step S31;
s33: etching to obtain a patterned metal layer, wherein the patterned metal layer is attached to the surface of the chip, which is far away from the base island, and is electrically connected with the pins of the lead frame;
s40: and packaging for the second time to package the lead frame, the chip and the patterned metal layer, and cutting and molding to obtain a packaging body.
The utility model discloses in, through directly forming patterned conducting layer in the packaging process to avoid the shaping step of extra independent conducting layer, thereby avoided the problem that the small-size conducting layer can't be makeed because of the restriction of die design or conducting layer self mechanical structure's restriction. Packaging body and packaging method can solve the technical problem that can't use the design of conducting layer because of the conducting layer undersize at present, simplified the operation efficiency of the packaging body that can only use the close-packed bonding wire because of the conducting layer undersize greatly.
Drawings
Fig. 1 is a flowchart of a packaging method of a package according to an embodiment of the present invention; fig. 2A to 2H are schematic structural views of the package body corresponding to fig. 1;
fig. 3 is a flowchart of a packaging method of a package according to another embodiment of the present invention; fig. 4A to 4E are schematic structural views of the package body corresponding to fig. 3;
fig. 5 is a flowchart of a packaging method of a package according to another embodiment of the present invention; fig. 6A to 6G are schematic structural views of the package corresponding to fig. 5;
fig. 7A and 7B are schematic views of a part of the step structure of a packaging method of a package according to another embodiment of the present invention
Detailed Description
Hereinafter, the technique of the present invention will be described in detail with reference to the embodiments. It should be understood that the following detailed description is only for assisting the person skilled in the art in understanding the present invention, and is not intended to limit the present invention.
Example one
In the present embodiment, a method for packaging a package and a package obtained by using the method are provided.
The packaging method in this embodiment is described in detail below with reference to fig. 1 and fig. 2A to 2H. In this embodiment, the packaging method includes the following steps:
step S10: as shown in fig. 1 and 2A, a lead frame 1 is provided, and a chip 2 is mounted on the lead frame 1. As shown in fig. 2A, the lead frame 1 includes a base island 11 and a lead 12. It will be understood by those skilled in the art that the lead frame 1 may include a plurality of frame units defined by a package line W, each of which includes the base island 11 and the leads 12. In fig. 2A, only one frame unit defined by the package line W is schematically shown. In this step, as shown in fig. 2A, the chip 2 is mounted on the lead frame 1, particularly on the base island 11 of the lead frame 1. It will be appreciated by those skilled in the art that the chip 2 may be mounted on the lead frame 1 in any manner known in the art, such as, but not limited to, by soldering or adhesive material to the lead frame 1. As shown in fig. 2A, the chip 2 includes a plurality of bonding pads 21, and the bonding pads 21 are electrically connected to the leads 12 of the lead frame 1 through a subsequently formed conductive layer.
Step S20: as shown in fig. 1 and 2B, a first packaging is further performed, and a plastic mold is used to expose the bonding pads 21 of the chip 2 and the leads 12 of the lead frame 1 when the chip 2 and the lead frame 1 are packaged by the plastic mold 3. It will be understood by those skilled in the art that the molding compound 3 may expose the bonding pads 21 of the chip 2 and portions of the chip 2, as well as portions of the leads 12 of the lead frame 1.
Step S30: as shown in fig. 1 and 2C, a solder paste layer 4 is further formed such that the solder paste layer 4 covers the pad 21 of the chip 2 and the portion of the lead 12 of the lead frame 1 exposed in the above step S20;
step S41: as shown in fig. 1 and 2D, a metal layer 5A is further formed, and the metal layer 5A covers the chip 2 and the lead 12 of the lead frame 1, that is, the metal layer 5A covers and contacts the surface of the molding compound 3 formed in the step S20 and the surface of the solder paste layer 4 formed in the step S30. That is, in this step, the metal layer 5A covers the region where the base island 11 and the lead 12 of the lead frame 1 are located, as shown in fig. 2D. It will be understood by those skilled in the art that, in this step, the coverage area of the metal layer 5A is not particularly limited, and at least covers the area where the conductive layer is finally formed. In order to simplify the manufacturing process, in the present embodiment, as shown in fig. 2D, the metal layer 5A covers substantially the entire area of the frame unit defined by the package line W.
Step S42: a patterned masking layer 6 is further formed on the surface of the metal layer 5A formed in the above step S41. As will be understood by those skilled in the art, in this step, as shown in fig. 2E, a masking layer 6A may be first formed on the metal layer 5A, the coverage of the masking layer 6A is the same as that of the metal layer 5A, and the material of the masking layer 6A is a photosensitive dry film or a photoresist material. The masking layer 6A is then patterned by exposure and development steps known in the art to form a patterned masking layer 6 as shown in fig. 2F on the metal layer 5A.
Step S43: after further etching and removing the patterned masking layer 6, the metal layer 5A shown in fig. 2D is patterned to finally obtain a patterned metal layer (i.e. the conductive layer 5), as shown in fig. 2G. Therefore, as shown in fig. 2A and 2G, the step obtains the conductive layers 5 electrically connected to the bonding pads (bonding pads 21 in fig. 2A) of the core 2 and the leads 12 of the lead frame 1 through the solder paste layers 4, respectively, and each bonding pad 21 is directly electrically connected to the corresponding lead 12 of the lead frame 1 through one conductive layer 5. The formed conductive layer 5 is a clip copper sheet which is used in the same traditional packaging body in the field and has heat dissipation performance and replaces wire bonding. It can be seen that, in the packaging method of the present embodiment, there is no need to form a clip copper sheet with an external shape structure as shown in fig. 2G in advance and mount the clip copper sheet in the package, but the clip copper sheet is directly formed in the packaging step of the package through an etching process. This allows the conductive layer 5 to be formed in the desired shape and size without being mechanically and dimensionally constrained by the clip copper sheet forming process. It will be appreciated by those skilled in the art that etching may be performed in this step in an etching method known in the art.
Step S50: and finally, performing secondary packaging to package the lead frame 1, the chip 2 and the conductive layer 5, and cutting and forming to obtain a packaging body. As shown in fig. 2H, in this step, the lead frame 1, the chip 2 and the conductive layer 5 are encapsulated by a molding compound 3, and a package 100 is obtained after cutting and molding.
As shown in fig. 2H, the package 100 manufactured by the packaging method according to the embodiment has a lead frame 1 and a chip 2, the lead frame 1 includes a base island 11 and a lead 12, and the chip 2 is disposed on the base island 11 of the lead frame 1. The chip 2 has a plurality of bonding pads 21 as shown in fig. 2A, each bonding pad 21 corresponds to one lead 12 of the lead frame 1, and each bonding pad 21 of the chip 2 is electrically connected to the corresponding lead 12 of the lead frame 1 through the solder paste layer 4 by one conductive layer 5 as shown in fig. 2H. That is, as shown in fig. 2H, a solder paste layer 4 is disposed between the conductive layer 5 and the corresponding pad 21 shown in fig. 2A, so as to achieve electrical connection.
Example two
In the embodiment, a packaging method of the package and a package obtained by using the packaging method are also provided. Unlike the first embodiment, the step of forming the solder paste layer described in the first embodiment is not included in the packaging method of the present embodiment.
The packaging method in this embodiment is described in detail below with reference to fig. 3 and 4A to 4E. In this embodiment, the packaging method includes the following steps:
step S10: as shown in fig. 3 and fig. 2A, a lead frame 1 is provided, and a chip 2 is mounted on the lead frame 1, as in the first embodiment. As shown in fig. 2A, the lead frame 1 includes a base island 11 and a lead 12. It will be understood by those skilled in the art that the lead frame 1 may include a plurality of frame units defined by a package line W, each of which includes the base island 11 and the leads 12. In fig. 2A, only one frame unit defined by the package line W is schematically shown. In this step, as shown in fig. 2A, the chip 2 is mounted on the lead frame 1, particularly on the base island 11 of the lead frame 1. It will be appreciated by those skilled in the art that the chip 2 may be mounted on the lead frame 1 in any manner known in the art, such as, but not limited to, by soldering or adhesive material to the lead frame 1. As shown in fig. 2A, the chip 2 includes a plurality of bonding pads 21, and the bonding pads 21 are electrically connected to the leads 12 of the lead frame 1 through a subsequently formed conductive layer.
Step S20: as shown in fig. 3 and fig. 2B, as in the first embodiment, a first packaging is further performed, and a plastic mold is used to expose the bonding pads 21 of the chip 2 and the leads 12 of the lead frame 1 when the chip 2 and the lead frame 1 are packaged by the plastic mold 3. It will be understood by those skilled in the art that the molding compound 3 may expose the bonding pads 21 of the chip 2 and portions of the chip 2, as well as portions of the leads 12 of the lead frame 1.
Step S41: as shown in fig. 3 and 4A, a metal layer 5A is further formed, where the metal layer 5A covers the chip 2 and the lead 12 of the lead frame 1, and contacts the pad 21 of the chip 2 and the lead 12 of the lead frame 1 exposed in step S20. That is, the metal layer 5A covers and contacts the surface of the molding compound 3 formed in the above step S20, and all exposed portions in the above step S20. That is, in this step, the metal layer 5A covers the region where the base island 11 and the lead 12 of the lead frame 1 are located, as shown in fig. 2D. It will be understood by those skilled in the art that, in this step, the coverage area of the metal layer 5A is not particularly limited, and at least covers the area where the conductive layer is finally formed. In order to simplify the manufacturing process, in the present embodiment, as shown in fig. 4A, the metal layer 5A covers substantially the entire area of the frame unit defined by the package line W.
Step S42: as in the first embodiment, a patterned masking layer 6 is further formed on the surface of the metal layer 5A formed in step S41. As will be understood by those skilled in the art, in this step, as shown in fig. 4B, a masking layer 6A may be first formed on the metal layer 5A, the coverage of the masking layer 6A is the same as that of the metal layer 5A, and the material of the masking layer 6A is a photosensitive dry film or a photoresist material. The masking layer 6A is then patterned by exposure and development steps known in the art to form a patterned masking layer 6 as shown in fig. 4C on the metal layer 5A.
Step S43: as in the first embodiment, after further etching and removing the patterned masking layer 6, the metal layer 5A shown in fig. 4C is patterned to finally obtain a patterned metal layer (i.e., the conductive layer 5), as shown in fig. 4D. Therefore, as shown in fig. 2A and 4D, the step obtains the conductive layers 5 directly electrically connected to the bonding pads (bonding pads 21 in fig. 2A) of the core 2 and the leads 12 of the lead frame 1, respectively, and each bonding pad 21 is directly electrically connected to the corresponding lead 12 of the lead frame 1 through one conductive layer 5.
Step S50: and finally, performing secondary packaging to package the lead frame 1, the chip 2 and the conductive layer 5, and cutting and forming to obtain a packaging body. As shown in fig. 4E, in this step, the lead frame 1, the chip 2 and the conductive layer 5 are encapsulated by a molding compound 3, and a package 200 is obtained after cutting and molding.
As shown in fig. 4E, the package 200 manufactured by the packaging method according to the embodiment has a lead frame 1 and a chip 2, the lead frame 1 includes a base island 11 and a lead 12, and the chip 2 is disposed on the base island 11 of the lead frame 1. The chip 2 has a plurality of bonding pads 21 as shown in fig. 2A, each bonding pad 21 corresponds to one lead 12 of the lead frame 1. Unlike the first embodiment, in the package 200 of the present embodiment, each pad 21 of the chip 2 is in direct contact with the corresponding lead 12 of the lead frame 1 through the conductive layer 5. That is, as shown in fig. 4E, each conductive layer 5 is in direct contact with the corresponding pad 21 shown in fig. 2A facing the surface of the pad 21; and, each conductive layer 5 faces the surface of the corresponding pin 12 and is in direct contact with the pin 12.
EXAMPLE III
In the embodiment, a packaging method of the package and a package obtained by using the packaging method are also provided. Different from the first embodiment or the second embodiment, in the packaging method of the present embodiment, a manner of obtaining the conductive layer is different.
Further, as shown in fig. 6A to 6F, in the present embodiment, a surface of the lead 12 of the lead frame 1 for contacting the conductive layer 5 (i.e., an upper surface of the lead 12 in fig. 6A to 6F) is higher than a surface of the base island 11 for contacting the chip 2 (i.e., an upper surface of the base island 11 in fig. 6A to 6F).
The packaging method in this embodiment is described in detail below with reference to fig. 5 and 6A to 6F. In this embodiment, the packaging method includes the following steps:
step S10: as shown in fig. 5 and 6A, a lead frame 1 is provided, and a chip 2 is mounted on the lead frame 1. As shown in fig. 6A, the lead frame 1 includes a base island 11 and a lead 12. It will be understood by those skilled in the art that the lead frame 1 may include a plurality of frame units defined by a package line W, each of which includes the base island 11 and the leads 12. In fig. 6A, only one frame unit defined by the packaging line W is schematically shown. In this step, as shown in fig. 6A, the chip 2 is mounted on the lead frame 1, particularly on the base island 11 of the lead frame 1. It will be appreciated by those skilled in the art that the chip 2 may be mounted on the lead frame 1 in any manner known in the art, such as, but not limited to, by soldering or adhesive material to the lead frame 1. As shown in fig. 6A, the chip 2 includes a plurality of bonding pads 21, and the bonding pads 21 are electrically connected to the leads 12 of the lead frame 1 through a subsequently formed conductive layer.
Step S20: as shown in fig. 5 and 6B, a first packaging is further performed, and a plastic mold is used to expose the bonding pads 21 of the chip 2 and the leads 12 of the lead frame 1 when the chip 2 and the lead frame 1 are packaged by the plastic mold 3. It will be understood by those skilled in the art that the molding compound 3 may expose the bonding pads 21 of the chip 2 and portions of the chip 2, as well as portions of the leads 12 of the lead frame 1. Alternatively, as shown in fig. 6B, the molding compound 3 exposes the chip 2.
Step S31: as shown in fig. 5 and 6C, a photosensitive dry film 6A is further attached in vacuum, so that the photosensitive dry film 6A covers the chip 2 and the region where the lead 12 of the lead frame 1 is located, that is, the photosensitive dry film 6A covers and contacts the surface of the molding compound 3 formed in step S20, and the chip 2 and the region where the lead 12 of the lead mine 1 is located, which are exposed in step S20. In order to simplify the manufacturing process, in the present embodiment, as shown in fig. 6C, the photosensitive dry film 6A covers substantially the entire area of the frame unit defined by the packaging line W.
Step S32: as shown in fig. 5 and 6D, a patterned masking layer 6 is obtained after exposure and development, so that the patterned masking layer 6 exposes at least the bonding pad 21 of the chip 2 and the lead 12 of the lead frame 1. It will be appreciated by those skilled in the art that the exposed portion of patterned masking layer 6 is the portion where conductive layer 5 is ultimately formed, as shown in fig. 6D.
Step S40: as shown in fig. 5 and fig. 6E, a metal layer 5A is further formed, and the metal layer 5A fills the patterned masking layer 6. After removing the patterned masking layer 6 by a method conventional in the art, a patterned metal layer as shown in fig. 6F, i.e. the conductive layer 5, can be obtained. Therefore, as shown in fig. 6A and 6F, the step obtains the conductive layers 5 respectively and directly electrically connected to the bonding pads (bonding pads 21 in fig. 6A) of the core 2 and the leads 12 of the lead frame 1, and each bonding pad 21 is directly contacted with the corresponding lead 12 of the lead frame 1 through one conductive layer 5. The formed conductive layer 5 is a clip copper sheet which is used in the same traditional packaging body in the field and has heat dissipation performance and replaces wire bonding. It can be seen that, in the packaging method of the present embodiment, there is no need to form a clip copper sheet with an external shape structure as shown in fig. 6F in advance and mount the clip copper sheet in the package, but the clip copper sheet is directly formed in the packaging step of the package through an etching process. This allows the conductive layer 5 to be formed in the desired shape and size without being mechanically and dimensionally constrained by the clip copper sheet forming process.
Step S50: as shown in fig. 5 and 6G, a second packaging is further performed to package the lead frame 1, the chip 2 and the conductive layer 5, and a package 300 is obtained after cutting and molding. As shown in fig. 6G, in this step, the lead frame 1, the chip 2 and the conductive layer 5 are encapsulated by a molding compound 3, and a package 300 is obtained after cutting and molding.
As shown in fig. 6G, the package 300 manufactured by the packaging method according to the embodiment has a lead frame 1 and a chip 2, the lead frame 1 includes a base island 11 and a lead 12, and the chip 2 is disposed on the base island 11 of the lead frame 1. The chip 2 has a plurality of bonding pads 21 as shown in fig. 6A, each bonding pad 21 corresponding to one lead 12 of the lead frame 1. Each pad 21 of the chip 2 is in direct contact with a corresponding lead 12 of the lead frame 1 through the conductive layer 5. That is, as shown in fig. 6F, each conductive layer 5 is in direct contact with the corresponding pad 21 shown in fig. 6A facing the surface of the pad 21; and, each conductive layer 5 faces the surface of the corresponding pin 12 and is in direct contact with the pin 12.
Example four
In the embodiment, a packaging method of the package and a package obtained by using the packaging method are also provided. Unlike the third embodiment, in the packaging method of the present embodiment, in the step S32 of forming a patterned masking layer 6, as shown in fig. 7A, the patterned masking layer 6 exposes only the bonding pad 21 of the chip 2 and the lead 12 of the lead frame 1. So that when the conductive layer 5 is finally formed, as shown in fig. 7B, a projection 51 is formed on the surface of the conductive layer 5 facing the corresponding pad 21 shown in fig. 7A so that the projection 51 is in direct contact with the pad 21.
In this embodiment, except for the step S32, the packaging method is the same as that of the third embodiment.
The present invention has been described in relation to the above embodiments, which are only examples for implementing the present invention. It must be noted that the disclosed embodiments do not limit the scope of the invention. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Claims (9)

1. The utility model provides a packaging body, includes lead frame and chip, wherein, the lead frame includes base island and pin, the chip set up in the lead frame on the base island, its characterized in that, the chip contains a plurality of pads, and each pad corresponds one the pin of lead frame, each pad of chip through a conducting layer with correspond the direct electric connection of pin of lead frame.
2. The package of claim 1, wherein each conductive layer is in direct contact with the pad facing a surface of the corresponding pad; and each conducting layer faces the surface of the corresponding pin and is in direct contact with the pin.
3. The package of claim 1, wherein each conductive layer has at least one bump disposed on a surface facing the corresponding pad such that the bump is in direct contact with the pad.
4. The package of claim 1, wherein a layer of solder paste is disposed between the conductive layer and the corresponding pad.
5. The package of claim 1, wherein a surface of the pin contacting the conductive layer is higher than a surface of the base island contacting the chip.
6. The package of claim 1, wherein the conductive layer is directly obtained by a step of patterning a metal layer in the packaging step of the package.
7. The package of claim 6, wherein in the step of patterning the metal layer, a metal layer is first formed such that the metal layer covers the chip and the lead frame in the area; and then, forming a patterned masking layer on the metal layer, and etching to obtain the conductive layer.
8. The package of claim 6, wherein in the step of patterning the metal layer, a patterned masking layer is first formed such that the patterned masking layer covers the chip and the lead frame in the area where the leads are located; then, a metal layer is formed to fill the patterned masking layer, and the conductive layer is obtained after the patterned masking layer is removed.
9. The package according to claim 7 or 8, wherein the material of the patterned masking layer is a photosensitive dry film or a photoresist material.
CN202020460756.5U 2020-04-01 2020-04-01 Package body Active CN211265447U (en)

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