CN211264298U

CN211264298U - PLL chip configuration test system based on host computer

Info

Publication number: CN211264298U
Application number: CN201921618981.0U
Authority: CN
Inventors: 周雨石; 李海龙; 钟为金
Original assignee: Dfine Technology Co Ltd
Current assignee: Dfine Technology Co Ltd
Priority date: 2019-09-26
Filing date: 2019-09-26
Publication date: 2020-08-14
Anticipated expiration: 2029-09-26

Abstract

The utility model discloses a PLL chip configuration test system based on host computer, include: the digital processing unit is connected with the upper computer and the frequency integrated circuit module, is used for analyzing the received register parameter command and issuing the register parameter command to the frequency integrated circuit module; the frequency synthesis circuit module outputs corresponding signal waveforms according to the received register configuration information; the frequency spectrograph is configured to receive and display the signal waveform output by the frequency synthesizer circuit module; and the upper computer inputs the register configuration information to the frequency synthesizer circuit module and acquires the waveform index of the output waveform of the frequency spectrograph. The utility model discloses utilize the signal waveform information of host computer receiving frequency spectrograph, judge whether qualified of waveform index to register value is issued manually or automatically, the PLL chip configuration of renewing, in order to reach the required index of PLL chip, there is digital processing personnel to write up host computer and FPGA program earlier stage, later stage test only need radio frequency designer debug can, reduce FPGA compile time, improved efficiency.

Description

PLL chip configuration test system based on host computer

Technical Field

The utility model relates to an electronic communication field especially relates to a PLL chip configuration test system based on host computer.

Background

Phase Locked Loops (PLLs) have been widely used in communication devices such as wireless base stations and wired transmission networks, and in the technical fields of radar, aerospace, precision measurement, computer, infrared, laser, atomic energy, stereo, motor control, imaging, and the like.

The traditional PLL chip configuration is that firstly, radio frequency designers simulate to obtain a required result, the result is provided for digital processors to be programmed and converted into a register value which can be read by a chip, and after the configuration is finished, the radio frequency designers confirm that if the difference or the index is not satisfied with the initial design (the actual difference between the hardware circuit environment and the simulation), the digital processors need to perform programming modification on the register value again or for multiple times according to the test result of the radio frequency designers until the result reaches the required index, the modification amount is large, and more manpower and material resources are occupied.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to the above-mentioned problem, provide a PLL chip configuration test system based on host computer.

The utility model provides a PLL chip configuration test system based on host computer, includes: the digital processing unit is connected with the upper computer and the frequency integrated circuit module, is used for analyzing the received register parameter command and issuing the register parameter command to the frequency integrated circuit module; the frequency synthesis circuit module outputs corresponding signal waveforms according to the received register configuration information; the frequency spectrograph is configured to receive and display the signal waveform output by the frequency synthesizer circuit module; and the upper computer inputs the register configuration information to the frequency synthesizer circuit module and acquires the waveform index of the output waveform of the frequency spectrograph.

Furthermore, a PLL chip configuration test system based on host computer, the frequency synthesis circuit module be PLL chip circuit.

Furthermore, the PLL chip configuration test system based on the upper computer is characterized in that the digital processing unit adopts an FPGA programmable logic device and sends the configured register parameters to the frequency synthesis circuit module according to a preset time sequence.

Furthermore, a PLL chip configuration test system based on host computer, frequency integrated circuit module and frequency spectrograph pass through GPIB line connection.

Furthermore, the PLL chip configuration test system based on the upper computer is a high-performance PC.

Further, a PLL chip configuration test system based on host computer, the communication mode of host computer and frequency integrated circuit module be SPI communication or RS232 communication.

The utility model has the advantages that: the utility model discloses utilize the signal waveform information of host computer receiving frequency spectrograph, judge whether qualified of waveform index to register value is issued manually or automatically, the PLL chip configuration of renewing, in order to reach the required index of PLL chip, there is digital processing personnel to write up host computer and FPGA program earlier stage, later stage test only need radio frequency designer debug can, reduce FPGA compile time, improved efficiency.

Drawings

Fig. 1 is a schematic diagram of the structure and principle of the present invention.

Fig. 2 is a schematic flow chart illustrating the principle of the PLL chip configuration according to the present invention.

Detailed Description

In order to clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will be described with reference to the accompanying drawings.

In this embodiment, as shown in fig. 1, the PLL chip configuration testing system based on the upper computer includes a digital processing unit, a frequency synthesizer module, a frequency spectrograph, and an upper computer.

In the chip configuration process, a radio frequency designer firstly obtains frequency value data required by the radio frequency designer through simulation and calculation, gives a corresponding register value according to data reference PLL chip data, sends the register value to a digital processing unit through an upper computer, sends the register value to the PLL chip according to a fixed time sequence after a series of processing, the PLL chip can output corresponding frequency to be displayed on a frequency spectrograph after successful configuration, and the radio frequency designer judges whether the output frequency meets the design requirement according to the final output (rear-end mixing frequency conversion and the like) so as to change the register value configured by the current PLL chip.

As shown in fig. 2, the utility model discloses PLL chip configuration test flow based on host computer, the value of key register is issued to the host computer (default register value can directly write in the procedure), FPGA among the digital processing unit is responsible for the analytic order, then in calling into each register, because the register has parameterized, the PLL register in the procedure just can be updated to the register value of receiving the host computer and issuing, then issue for the PLL chip, need not to compile, because of the FPGA device, software itself, compile can consume a large amount of time, just this restriction has been eliminated after the parameterization, PLL output corresponding frequency, observe on the spectrometer, the tester can judge whether satisfy the design index according to the frequency spectrum, whether continue to change the register again, if satisfy the requirement, this register value will be solidified in the procedure as optimal data.

The utility model discloses utilize the signal waveform information of host computer receiving frequency spectrograph, judge whether qualified of waveform index to register value is issued manually or automatically, the PLL chip configuration of renewing, in order to reach the required index of PLL chip, there is digital processing personnel to write up host computer and FPGA program earlier stage, later stage test only need radio frequency designer debug can, reduce FPGA compile time, improved efficiency.

The basic principles and the main features of the invention and the advantages of the invention have been shown and described above. It will be understood by those skilled in the art that the present invention is not limited to the above embodiments, and that the foregoing embodiments and descriptions are provided only to illustrate the principles of the present invention without departing from the spirit and scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. The utility model provides a PLL chip configuration test system based on host computer which characterized in that includes:

the digital processing unit is connected with the upper computer and the frequency integrated circuit module, is used for analyzing the received register parameter command and issuing the register parameter command to the frequency integrated circuit module;

the frequency synthesis circuit module outputs corresponding signal waveforms according to the received register configuration information;

the frequency spectrograph is configured to receive and display the signal waveform output by the frequency synthesizer circuit module;

and the upper computer inputs the register configuration information to the frequency synthesizer circuit module and acquires the waveform index of the output waveform of the frequency spectrograph.

2. The upper-computer-based PLL chip configuration test system according to claim 1, wherein said frequency synthesizer circuit module is a PLL chip circuit.

3. The PLL chip configuration test system based on the host computer of claim 1, wherein the digital processing unit adopts an FPGA programmable logic device to send the configured register parameters to the frequency synthesizer circuit module according to a preset time sequence.

4. The upper-computer-based PLL chip configuration test system according to claim 1, wherein said frequency synthesizer module is connected to said frequency spectrometer via a GPIB line.

5. The PLL chip configuration test system based on the upper computer as claimed in claim 1, wherein the upper computer is a high performance PC.

6. The PLL chip configuration test system based on the upper computer of claim 1, wherein the communication mode of the upper computer and the frequency synthesizer circuit module is SPI communication or RS232 communication.