CN112835648A - FPGA-based chip internal register high-reliability configuration method - Google Patents
FPGA-based chip internal register high-reliability configuration method Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
Abstract
The invention provides a high-reliability configuration method for a chip internal register based on an FPGA (field programmable gate array), which solves the problem that the starting failure or partial function abnormality of electronic equipment is caused by the fact that the initialization configuration process is randomly interfered and deviates from an actual expected value due to electromagnetic interference or space single particles. The method comprises the following steps: step one, initializing register list information; step two, starting a register configuration process; step three, register configuration process; 3.1) data acquisition; 3.2) register write operation; 3.3) register read operation; 3.4) judging data; 3.5) register configuration counter update. The method takes the FPGA as a core processor, performs writing, reading and inquiring on all the readable and writable registers of the peripheral chip in the power-on initialization configuration process, and performs state inquiring on the read-only registers so as to solve the possible risk of abnormal configuration when the integrated circuit is initialized and configured in a complex electromagnetic environment.
Description
Technical Field
The invention belongs to the technical field of embedded system development, and particularly relates to a high-reliability configuration method for an internal register of a peripheral circuit chip based on an FPGA.
Background
With the development of semiconductor integrated circuit technology, most of the existing electronic devices are formed by integrating a core processor (CPU, FPGA, DSP, GPU, etc.) with peripheral Integrated Circuits (ICs) with various functions, and since a single integrated circuit has relatively powerful functions, in order to meet the requirements of different customers and different functions, an IC designer usually sets a plurality of registers (many registers even reach thousands of registers) inside the IC to set the functions or parameters of the IC, and configures different registers according to different requirements, which is called initialization configuration. However, in a complex electromagnetic environment or a space environment with strong radiation, the initialization configuration process is randomly disturbed to deviate from the actual expected value due to electromagnetic interference or space single particles, that is, some registers needing to be changed with default values are written with wrong values, or some registers without being changed with default values are tampered, so that the electronic device fails to start or partially functions abnormally.
Disclosure of Invention
The invention aims to solve the problem that the starting failure or partial function abnormality of electronic equipment is caused by the fact that the initialization configuration process is randomly interfered to deviate from an actual expected value due to electromagnetic interference or space single particles, and provides a high-reliability configuration method for an internal register of a chip based on an FPGA. The method takes the FPGA as a core processor, performs writing, reading and inquiring on all the readable and writable registers of the peripheral chip in the power-on initialization configuration process, and performs state inquiring on the read-only registers so as to solve the possible risk of abnormal configuration when the integrated circuit is initialized and configured in a complex electromagnetic environment.
In order to achieve the purpose, the invention adopts the following technical scheme:
a high-reliability configuration method for an internal register of a chip based on an FPGA comprises the following steps:
step one, initializing register list information;
initializing register list information, wherein the register list information comprises readable and writable register information and read-only register information, the readable and writable register information comprises a register address, an initialization configuration value and read-write mark information, and the read-only register information comprises a register address and read-only mark information;
step two, starting a register configuration process;
when the configuration starting signal and/or the reconfiguration signal are/is effective, the FPGA internal state machine jumps out of the standby configuration state and enters the next step;
step three, register configuration process;
3.1) data acquisition;
acquiring the address, the register value and the read-write mark of the current register needing to be written or read only from the initialized register list information according to the register counter, entering different states according to the read-write mark state machine, and executing the step 3.2 if the read-write mark is both written and read; if the read-write mark is read-only, executing the step 3.3);
3.2) register write operation;
the FPGA generates corresponding waveforms according to the write time sequence requirement of the configuration interface of the peripheral chip, and after the write operation is finished, the step 3.3) is executed;
3.3) register read operation;
the FPGA generates corresponding waveforms according to the read time sequence requirement of the configuration interface of the peripheral chip, receives the current address register data sent by the peripheral chip, carries out sorting and/or conversion according to the output time sequence, and executes the step 3.4 after the read operation is finished;
3.4) judging data;
if the read-write flag of the register in the current operation is both writing and reading, judging whether the read data of the current address register is consistent with the write data in the step 3.2), if so, executing the step 3.5), otherwise, executing the step 3.1); the data read by the current address register is the data which is sent by the peripheral chip during the read operation in the step 3.3) and is processed by sorting and/or conversion;
if the read-write mark of the register in the current operation is read-only, judging whether the read data of the current address register is in a normal range, if so, executing the step 3.1), otherwise, executing the step 3.3);
3.5) updating a register configuration counter;
after the current register operation is completed, judging whether all registers are inquired completely, if not, adding 1 to or subtracting 1 from the register configuration counter (according to a counting mode), and repeating the steps 3.1 to 3.5) until all registers are configured or inquired completely; otherwise, returning to the step two.
Further, in the first step, the register list information is pre-stored in the ROM inside the FPGA, and is automatically loaded when being powered on.
Further, in step two, the start configuration signal and/or the reconfiguration signal is a start register configuration signal generated at power-on start, reset or mode switching.
Further, in step 3.2), the configuration interface includes I2C, SPI, JTAG, and UART interfaces.
Compared with the prior art, the invention has the beneficial effects that:
the method adopts a write-read-comparison strategy for the readable and writable register in the FPGA peripheral chip, thereby ensuring that the written data is consistent with a preset value; and judging whether the state value of the read-only register is in a normal value range or not, and preventing the abnormal configuration caused by the influence of a complex electromagnetic environment on the initialization configuration, thereby improving the reliability of the initialization configuration of the electronic equipment.
Drawings
FIG. 1 is a flow chart of a high-reliability configuration method of an internal register of a chip based on an FPGA according to the present invention;
FIG. 2 is a state machine jump diagram for reliable configuration of the chip internal registers provided by the present invention;
FIG. 3 is a timing diagram of an SPI configuration interface of an image sensor according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
The invention provides a high-reliability configuration method for an internal register of a chip based on an FPGA (field programmable gate array). the method takes the FPGA as a core processor to carry out high-reliability initialization configuration on the internal register of a peripheral device of the FPGA, thereby reducing the risk of initialization abnormity caused by interference of a complex electromagnetic environment on the initialization configuration process. The method divides the internal registers of the chip into two types of read-write and read-only, and different types of registers adopt different operation and discrimination methods, thereby improving the reliability of configuration.
The high-reliability configuration method of the chip internal register based on the FPGA specifically comprises the following steps:
step one, initializing register list information;
initializing register list information, wherein the register list information is information of all registers of the device and specifically comprises readable and writable register information and read-only register information, the readable and writable register information comprises a register address, an initialization configuration value and read-write flag information, the read-only register information mainly comprises address information and read-only flag information, and the register value is meaningless; the register list information can be pre-stored in an ROM in the FPGA, and is automatically loaded when being electrified;
step two, starting a register configuration process;
when the configuration starting signal and/or the reconfiguration signal are/is effective, the FPGA internal state machine jumps out of the standby configuration state and enters the next state; the start configuration signal and/or the reconfiguration signal may specifically be a start register configuration signal generated during power-on start, reset, or mode switching;
step three, register configuration process;
3.1) data acquisition;
according to the counter of the configuration register, acquiring the address, the register value and the read-write mark of the current register needing to be written and read or read only from the initialization register list information ROM; and entering different states according to the read-write mark state machine, if the read-write mark is both write and read, the state machine skips to the step 3.2); if the read-write mark is read-only, the state machine jumps to the step 3.3);
3.2) register write operation;
the writing operation is that the FPGA generates corresponding waveforms according to the writing time sequence requirement of a configuration interface of the peripheral chip, and the configuration interface comprises but is not limited to I2C, SPI, JTAG and UART interfaces; after the write operation is finished, the state machine jumps to 3.3);
3.3) register read operation;
the read operation is that the FPGA generates corresponding waveforms according to the read time sequence requirement of the configuration interface of the peripheral chip, receives the current address register data sent by the peripheral chip, and carries out sorting and/or conversion according to the output time sequence; after the reading operation is finished, the state machine jumps to the step 3.4);
3.4) judging data;
data determination is divided into two parts: if the read-write mark of the register in the current operation is both writing and reading, judging whether the read data of the register in the current address is consistent with the written data in the step 3.2), if so, skipping to the step 3.5 by the state machine, otherwise, skipping to the step 3.1 by the state machine);
if the read-write mark of the register in the current operation is read-only, judging whether the read data of the current address register is in a normal range, if so, skipping to the step 3.1 by the state machine, otherwise, skipping to the step 3.3 by the state machine); the data read by the current address register is the data which is sent by the peripheral chip during the read operation in the step 3.3) and is processed by sorting and/or conversion;
3.5) updating a register configuration counter;
the updating of the register configuration counter is to judge whether all registers are inquired after the current register operation is completed, if not, the register configuration counter is increased by 1or decreased by 1, and the state machine jumps to the step 3.1) and repeats the steps 3.1) -3.5) until all registers are configured or inquired; otherwise, the state machine jumps to step two. The increment or the decrement of 1 of the register configuration counter is made according to the increment or the decrement strategy of the whole counting process.
Taking one of the chips (image detectors) on the periphery of the FPGA as an example, a flow diagram of the reliable configuration method is shown in fig. 1, and mainly includes processes of initializing register list information, starting configuration/reconfiguration, writing operation timing, reading operation timing, data determination, counter updating, and the like. The register list information is information of all registers of the device, the readable and writable register information comprises register addresses, initialization configuration values and read-write flag information, the read-only register information mainly comprises address information and read-only flag information, and register values are meaningless. All register list information is pre-stored in an internal ROM of the FPGA, and is automatically loaded when being powered on. The following detailed description of the reliable register configuration method, which is programmed inside the FPGA by means of a state machine, is made with reference to fig. 2. When the start configuration signal and/or the reconfiguration signal is active (cfg _ St 1or refg 1), the state machine jumps out of St1: idle state and enters the register configuration process. The data acquisition (St2: reg _ updata) is to acquire the address, the register value and the read-write mark of the current register needing to be read or written from the initialization register list information ROM according to the configuration register counter; and entering different states according to the read-write mark state machine, and if the read-write mark is both write and read (reg _ wr is 1), the state machine jumps to the state St3: reg _ wr; if the read-write flag is read-only (reg _ wr ═ 0), the state machine jumps to St4: reg _ rd; after the state machine enters St3: reg _ wr, the FPGA generates corresponding waveforms, such as XCE, SDI and SCK signal waveforms shown in FIG. 3, according to the write timing requirement of the configuration interface of the peripheral chip, and at this time, the SDO has no data output (continuous low level); when the write operation (St3: reg wr) is completed (reg wr finish ═ 1), the state machine jumps to St4: reg rd, otherwise the state machine stays at St3: reg wr until the write operation is completed. After the state machine enters St4: reg _ rd, the FPGA generates corresponding waveforms, such as XCE, SDI, SCK and SDO signal waveforms shown in FIG. 3, according to the read timing requirement of the configuration interface of the peripheral chip, receives the current address register data sent by the peripheral chip through the SDO, and performs sorting and/or conversion according to the output timing; when the read operation (St4: reg rd) is completed (reg rd finish ═ 1), the state machine jumps to St5: reg judge, whereas the state machine stays at St4: reg rd until the read operation is completed. In the state St5, reg _ judge, the FPGA compares the data obtained by the read operation with the written data or the normal state value, and if the comparison is successful (reg _ wr _ success is 1), the state machine jumps to St 6: reg _ cnt _ updata; if the comparison is unsuccessful (reg _ wr _ success is 0), the state machine jumps to St2: reg _ updata, and performs a configuration inquiry flow of rewrite operation, read operation and comparison on the current register. In the state St 6: reg _ cnt _ updata, a register configuration counter update is performed, the register configuration counter is incremented by 1or decremented by 1, the increment or decrement operation depends on the whole count increment or decrement strategy, and then the state machine jumps to St 7: the cfg _ finish judges whether the whole initialization configuration process is finished according to the value of the register configuration counter, and if the whole configuration process is finished (cfg _ finish is 1), the state machine jumps to St1: idle state; otherwise, jump to St2: reg _ updata to configure the next register. And the process is circulated until the whole initialization configuration process is completed.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and it will be apparent to those skilled in the art that various modifications, changes, and interface configurations may be applied. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (4)
1. A high-reliability configuration method for an internal register of a chip based on an FPGA is characterized by comprising the following steps:
step one, initializing register list information;
initializing register list information, wherein the register list information comprises readable and writable register information and read-only register information, the readable and writable register information comprises a register address, an initialization configuration value and read-write mark information, and the read-only register information comprises a register address and read-only mark information;
step two, starting a register configuration process;
when the configuration starting signal and/or the reconfiguration signal are/is effective, the FPGA internal state machine jumps out of the standby configuration state and enters the next step;
step three, register configuration process;
3.1) data acquisition;
acquiring the address, the register value and the read-write mark of the current register needing to be written or read only from the initialized register list information according to the register counter, entering different states according to the read-write mark state machine, and executing the step 3.2 if the read-write mark is both written and read; if the read-write mark is read-only, executing the step 3.3);
3.2) register write operation;
the FPGA generates corresponding waveforms according to the write time sequence requirement of the configuration interface of the peripheral chip, and after the write operation is finished, the step 3.3) is executed;
3.3) register read operation;
the FPGA generates corresponding waveforms according to the read time sequence requirement of the configuration interface of the peripheral chip, receives the current address register data sent by the peripheral chip, carries out sorting and/or conversion according to the output time sequence, and executes the step 3.4 after the read operation is finished;
3.4) judging data;
if the read-write flag of the register in the current operation is both writing and reading, judging whether the read data of the current address register is consistent with the write data in the step 3.2), if so, executing the step 3.5), otherwise, executing the step 3.1); the data read by the current address register is the data which is sent by the peripheral chip during the read operation in the step 3.3) and is processed by sorting and/or conversion;
if the read-write mark of the register in the current operation is read-only, judging whether the read data of the current address register is in a normal range, if so, executing the step 3.1), otherwise, executing the step 3.3);
3.5) updating a register configuration counter;
after the current register operation is completed, judging whether all registers are inquired completely, if not, adding 1 to or subtracting 1 from the register configuration counter, and repeating the steps 3.1) to 3.5) until all registers are configured or inquired completely; otherwise, returning to the step two.
2. The FPGA-based chip internal register high-reliability configuration method according to claim 1, characterized in that: in the first step, the register list information is pre-stored in an internal ROM of the FPGA, and is automatically loaded when being electrified.
3. The FPGA-based chip internal register high-reliability configuration method according to claim 2, characterized in that: in step two, the start configuration signal and/or the reconfiguration signal are start register configuration signals generated during power-on start, reset or mode switching.
4. The FPGA-based chip internal register high-reliability configuration method according to claim 1, 2 or 3, characterized in that: in step 3.2), the configuration interface comprises an I2C interface, an SPI interface, a JTAG interface and a UART interface.
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| CN115454918A (en) * | 2022-11-11 | 2022-12-09 | 成都航天通信设备有限责任公司 | CX9261 chip configuration method based on FPGA |
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