CN211208446U

CN211208446U - Anti-fuse memory cell

Info

Publication number: CN211208446U
Application number: CN201921312949.XU
Authority: CN
Inventors: 冯鹏; 李雄
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2019-08-13
Filing date: 2019-08-13
Publication date: 2020-08-07
Anticipated expiration: 2029-08-13

Abstract

The embodiment of the utility model provides an antifuse memory cell is related to, include: a substrate having a select gate structure thereon; the first doped region and the second doped region are respectively positioned in the substrate at two opposite sides of the selective gate structure, and the types of doped ions of the first doped region and the second doped region are the same; the anti-fuse grid dielectric layer is positioned on the first doped region, and the anti-fuse grid is positioned on the anti-fuse grid dielectric layer; and the third doping area is positioned between the second doping area and the selective grid structure, the doping ion type of the third doping area is the same as that of the second doping area, and the doping ion concentration of the third doping area is smaller than that of the second doping area. The utility model discloses can reduce the damage of electric field to the select gate dielectric layer to improve the reliability of select transistor among the antifuse memory cell.

Description

Anti-fuse memory cell

Technical Field

The utility model relates to the field of semiconductor technology, in particular to antifuse memory cell.

Background

Memory devices can be generally classified into volatile memory devices and nonvolatile memory devices. The nonvolatile memory device may be further classified into a Read Only Memory (ROM), a one time programmable memory (OTP memory), and a rewritable memory. Among them, the otp memory can be classified into a fuse type (fuse type) and an antifuse type (anti-fuse type).

In a semiconductor device such as a DRAM (Dynamic Random Access Memory), a defective address is generally repaired by replacing a defective cell that cannot normally operate with a redundant cell. In storing defective addresses, antifuse memory is commonly used to store information.

The smallest unit of an antifuse memory is usually composed of one antifuse transistor and one select transistor. The working principle of the antifuse memory is to store data 1 or 0 according to whether the antifuse gate dielectric layer is broken down, so that the antifuse memory can selectively electrically connect two elements which are originally electrically isolated. In the prior art, in the programming process of an antifuse memory, a source/drain terminal of a selection transistor instantly bears high voltage transmitted by the antifuse transistor, so that a selection gate dielectric layer is damaged, and the reliability of the selection transistor is influenced.

SUMMERY OF THE UTILITY MODEL

An embodiment of the utility model provides an antifuse storage unit solves when antifuse grid dielectric layer takes place dielectric breakdown, and the source/drain bears the problem that high pressure caused the selective grid structural damage in the twinkling of an eye.

In order to solve the above technical problem, an embodiment of the present invention provides an antifuse memory cell, including: the substrate is provided with a selection gate structure; the first doped region and the second doped region are respectively positioned in the substrate at two opposite sides of the selective gate structure, and the doped ion types of the first doped region and the second doped region are the same; the anti-fuse grid dielectric layer is positioned on the first doping region, and the anti-fuse grid is positioned on the anti-fuse grid dielectric layer; and the third doping area is positioned between the second doping area and the selective grid structure, the type of doping ions of the third doping area is the same as that of the doping ions of the second doping area, and the concentration of the doping ions of the third doping area is less than that of the doping ions of the second doping area.

Compared with the prior art, the embodiment of the utility model provides a technical scheme has following advantage:

the embodiment of the utility model provides an anti-fuse memory cell, set up the third doped region between select gate structure and second doped region, the third doped region is the same with the doping ion type in second doped region, do not set up L DD structure between first doped region and select gate structure promptly when anti-fuse gate dielectric layer takes place the dielectric breakdown, instantaneous high voltage is born in first doped region, because L DD structure's existence can increase the overlap region area in the strong electric field district between select gate structure and the first doped region, consequently when not setting up L DD structure between first doped region and the select gate structure, the strong electric field area that the instantaneous high voltage that first doped region bore formed reduces with the overlap region area of select gate structure, reduced the direct damage of strong electric field to the select gate structure.

In addition, because the L DD structure is not arranged between the first doped region and the select gate structure, equivalent to that equivalent resistance is connected in series between the first doped region and the select gate structure, and a voltage division effect can be achieved, which is beneficial to reducing the electric field intensity of the strong electric field region where the select gate structure is located, thereby weakening the damage of the strong electric field region to the select gate structure.

In addition, the material of the anti-fuse grid dielectric layer is the same as that of the selection grid dielectric layer, and the thickness of the anti-fuse grid dielectric layer is smaller than or equal to that of the selection grid dielectric layer, so that the selection grid dielectric layer is not broken down before the anti-fuse grid dielectric layer is broken down, and the electrical performance of the anti-fuse storage unit is improved.

In addition, the concentration of the doping ions in the first doping region is less than or equal to that in the second doping region, so that the situation that the selection gate dielectric layer is not broken down before the anti-fuse gate dielectric layer is broken down is further ensured, and the electrical performance of the anti-fuse memory unit is improved.

In addition, a fourth doping area is arranged between the first doping area and the selective gate structure, the type of doping ions of the fourth doping area is different from that of the doping ions of the first doping area, namely the fourth doping area is an HA L O area.

In addition, the fourth doping region can also reduce the ion diffusion of the first doping region and is used for inhibiting the problems of leakage current and source-drain punch-through caused by the ion diffusion of the first doping region.

In addition, the depth of the fourth doping area in the substrate is larger than that of the first doping area in the substrate, so that the ion diffusion of the first doping area can be further inhibited.

In addition, a fifth doping area is arranged below the third doping area, the fifth doping area is in contact with the second doping area, and the type of doping ions of the fifth doping area is the same as that of the fourth doping area. The fifth doped region is arranged for inhibiting the ion diffusion of the second doped region and is used for inhibiting the problems of leakage current and source-drain punch-through caused by the ion diffusion of the second doped region.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

FIG. 1 is a cross-sectional view of an antifuse memory cell;

FIG. 2 is a schematic cross-sectional view of an antifuse memory cell according to a first embodiment of the present invention;

FIG. 3 is an equivalent circuit of an antifuse memory cell according to a first embodiment of the present invention;

FIG. 4 is a schematic cross-sectional view of an antifuse memory cell according to a second embodiment of the present invention;

fig. 5 to 8 are schematic cross-sectional views illustrating steps of a method for manufacturing an antifuse memory cell according to a first embodiment of the present invention;

fig. 9 is a schematic cross-sectional structure diagram corresponding to an intermediate step of a method for manufacturing an antifuse memory cell according to a second embodiment of the present invention.

Detailed Description

As can be seen from the background art, the select gate dielectric layer in the prior art anti-fuse memory cell is susceptible to damage.

Referring to fig. 1, fig. 1 is a schematic cross-sectional view of an antifuse memory cell. Referring to fig. 1, an antifuse memory cell includes: a substrate 21 having a select gate structure 24 thereon; the first doping region 25 and the second doping region 29, the first doping region 25 and the second doping region 29 are respectively located in the substrate 21 at two opposite sides of the select gate structure 24, and the doping ion types of the first doping region 25 and the second doping region 29 are the same; an anti-fuse gate dielectric layer 232 on the first doped region 25 and an anti-fuse gate 233 on the anti-fuse gate dielectric layer 232; a third doped region 27, the third doped region 27 is located between the second doped region 29 and the select gate structure 24, the type of doped ions of the third doped region 27 is the same as the type of doped ions of the second doped region 29, and the concentration of doped ions of the third doped region 27 is less than the concentration of doped ions of the second doped region 29; and a fourth doped region 20, wherein the fourth doped region 20 is located between the first doped region 25 and the select gate structure 24, the type of the doped ions in the fourth doped region 20 is the same as the type of the doped ions in the first doped region 25, and the concentration of the doped ions in the fourth doped region 20 is less than the concentration of the doped ions in the first doped region 25.

The anti-fuse memory cell described above has a problem in that the select gate dielectric layer 242 is damaged by a strong electric field. The analysis finds that the reasons for the above problems are as follows: when the voltage drop applied across the antifuse gate dielectric layer 232 reaches a certain value, dielectric breakdown of the antifuse gate dielectric layer 232 occurs, so that the antifuse gate dielectric layer 232 is instantly conducted, and the first doped region 25 will bear an instant high voltage. Since the fourth doped region 20 is connected to the first doped region 25 and the fourth doped region 20 is in contact with the selection gate dielectric layer 242, the transient high voltage applied to the first doped region 25 generates a strong electric field between the fourth doped region 20 and the selection gate dielectric layer 242, and the presence of the strong electric field may cause damage to the selection gate dielectric layer 242.

To solve the above problems, embodiments of the present invention provide an anti-fuse memory cell comprising an anti-fuse transistor and a select transistor, the anti-fuse gate dielectric layer and the first Doped region forming the anti-fuse transistor, the anti-fuse transistor having a single-sided source/Drain, the anti-fuse transistor functioning as a capacitor, further, the first Doped region, the second Doped region and the select gate structure forming the select transistor, the select gate structure comprising the select gate and the select gate dielectric layer, wherein the first Doped region and the second Doped region respectively serve as the Drain or the source of the select transistor, and the third Doped region is provided as a L DD structure only between the second Doped region and the select gate structure, and no L DD (L g heavy Doped Drain) is provided between the first Doped region and the select gate structure, that is the structure of the single-sided fuse L DD structure, when the anti-fuse gate in the anti-fuse gate transistor is broken down, the first Doped region and the select gate structure are provided with a lightly Doped Drain, that the anti-fuse gate structure of the single-fuse gate structure is protected from the high voltage, thereby improving reliability of the select gate structure, and the select gate structure of the anti-fuse transistor, which is provided by the select gate structure, which is advantageous for example, and which is provided with good stability of the select gate structure, thereby improving reliability of the select gate structure of the select transistor, and the select transistor, which is provided by the select gate structure of the anti-fuse L.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the embodiments of the present invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.

Fig. 2 is a schematic cross-sectional view of an antifuse memory cell according to a first embodiment of the present invention.

Referring to fig. 2, the antifuse memory cell in the present embodiment includes: a substrate 11 having a select gate structure 14 thereon; the first doped region 15 and the second doped region 19 are respectively positioned in the substrate 11 at two opposite sides of the select gate structure 14, and the doping ion types of the first doped region 15 and the second doped region 19 are the same; an anti-fuse gate dielectric layer 132 overlying first doped region 15 and an anti-fuse gate 133 overlying anti-fuse gate dielectric layer 132; a third doped region 17, the third doped region 17 is located between the second doped region 19 and the select gate structure 14, the type of doping ions of the third doped region 17 is the same as the type of doping ions of the second doped region 19, and the concentration of doping ions of the third doped region 17 is less than the concentration of doping ions of the second doped region 19.

The anti-fuse memory cell provided by the embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

In this embodiment, the select gate structure 14 is located on the substrate 11, the select gate structure 14 includes a select gate dielectric layer 142 and a select gate 143 located on the select gate dielectric layer 142, and the sidewall surfaces of two opposite sides of the select gate structure 14 have first sidewalls 141.

The material of the select gate 143 may be polysilicon or metal, the material of the select gate dielectric layer 142 is usually oxide, the first sidewall 141 may be one of silicon oxide, silicon nitride and silicon oxynitride, or a combination thereof, and the first sidewall 141 plays a role in protecting the select gate 143 and the select gate dielectric layer 142.

In this embodiment, the substrate 11 further has an isolation structure 12 therein, and the material of the isolation structure 12 may be silicon oxide or silicon nitride. It should be noted that the depth of the isolation structure 12 in the substrate 11 can be adjusted according to the actual situation.

The substrate 11 has a first doped region 15 and a second doped region 19 therein, the first doped region 15 and the second doped region 19 are respectively located at two opposite sides of the select gate structure 14, and the first doped region 15 and the second doped region 19 have the same doping ion type, which includes N-type ions or P-type ions. The first doped region 15, the select gate structure 14 and the second doped region 19 constitute a select transistor, the first doped region 15 serves as a source or a drain of the select transistor, and the second doped region 19 serves as a drain or a source of the select transistor.

In the present embodiment, the doping ion concentration of the first doping region 15 is greater than that of the second doping region 19. In this manner, first doped region 15 is enabled to provide an effective voltage to the antifuse transistor, thereby ensuring that select gate dielectric layer 142 is not broken down before antifuse gate dielectric layer 132 is broken down, thereby improving the electrical performance of the antifuse memory cell.

When the selection transistor in the anti-fuse memory cell is an NMOS transistor, the doping type of the first doping region 15 and the second doping region 19 is N-type doping; when the selection transistor in the anti-fuse memory cell is a PMOS transistor, the doping type of the first doped region 15 and the second doped region 19 is P-type doping.

In addition, a well region (not shown) is included in the substrate 11, and the doping type of the well region is different from the doping type of the first doping region 15 and the second doping region 19.

In this embodiment, the edge 151 of the first doped region 15 facing the select gate structure 14 is aligned with the sidewall 144 of the select gate 14 facing the first doped region 15. In the subsequent annealing process, the sidewall of the first doped region 15 facing the second doped region 19 slightly moves toward the second doped region 19 from the first doped region 15.

In other embodiments, in the horizontal direction of the first doped region toward the second doped region, a distance between a sidewall of the first doped region toward the select gate structure and a sidewall of the select gate structure toward the first doped region is 0nm to 800 nm. For example, the pitch may be 0nm, 10nm, 50nm, 100nm, 300nm, 500nm, or 800 nm. When the distance is within the range of 0 nm-800 nm, the electric field between the first doping region and the selection grid structure can not damage the selection grid dielectric layer when the first doping region bears instantaneous high voltage, and the first doping region and the second doping region can be normally conducted when the selection grid is under working voltage.

The substrate 11 further has an anti-fuse gate dielectric layer 132 and an anti-fuse gate 133 on the anti-fuse gate dielectric layer, the anti-fuse gate dielectric layer 132 is located on the first doped region 15 and the isolation structure 12, the first doped region 15, the anti-fuse gate dielectric layer 132 and the anti-fuse gate 133 form an anti-fuse transistor with a single-sided source/drain, and the anti-fuse transistor functions as a capacitor. The antifuse transistor and the selection transistor together constitute an antifuse memory cell.

For example, when the voltage drop across the antifuse transistor reaches 6V, the antifuse gate dielectric layer 132 undergoes dielectric breakdown, thereby completing the data storage process of the antifuse memory cell. It should be noted that, in this embodiment, the antifuse gate dielectric layer 132 is partially located on the first doped region 15, so that after the antifuse gate dielectric layer 132 is broken down, the direction of current is a single side, which improves the energy utilization rate and enhances the electrical performance of the antifuse memory cell.

In this embodiment, the material of antifuse gate 133 may be the same as or different from that of select gate 143, and the material of antifuse gate dielectric layer 132 may be the same as or different from that of select gate dielectric layer 142. In the present embodiment, the material of the anti-fuse gate dielectric layer 132 is the same as the material of the select gate dielectric layer 142, and is silicon oxide.

The material of antifuse gate dielectric layer 132 is the same as the material of select gate dielectric layer 142, and the thickness of antifuse gate dielectric layer 132 is less than or equal to the thickness of select gate dielectric layer 142. In this manner, select gate dielectric layer 142 is effectively guaranteed not to be broken down before antifuse gate dielectric layer 132 is broken down, so that antifuse gate 133 can provide an effective voltage to the antifuse transistor, enabling the antifuse transistor to be broken down effectively; if the thickness of the antifuse gate dielectric layer is greater than that of the selection gate dielectric layer, the selection gate dielectric layer is already broken down when the antifuse gate dielectric layer is not broken down, and the breakdown effect of the antifuse transistor is affected.

In addition, the distance 112 between the side wall of antifuse gate 133 facing select gate 143 and the side wall of select gate 143 facing antifuse gate 133 is 400nm to 800 nm. For example, the pitch may be 400nm, 500nm, 600nm, 700nm, or 800 nm. The purpose of setting the range of the spacing 112 is to ensure that the potential difference between the antifuse gate 133 and the select gate 143 cannot break down the dielectric therebetween, prevent the antifuse gate 133 and the select gate 143 from forming an electrical connection, prevent the antifuse memory cell from failing, and make the antifuse memory cell have a smaller size, thereby achieving high integration.

The third doped region 17 is used as an L DD structure between the second doped region 19 and the select gate structure 14, which plays a role of reducing the electric field between the source and the drain, and meanwhile, since the third doped region 17 is located between the first doped region 15 and the second doped region 19, the third doped region 17 shortens the distance between the source and the drain, thereby avoiding the hot electron effect.

Referring to fig. 3, fig. 3 is an equivalent operating circuit of the antifuse memory cell according to the first embodiment of the present invention, referring to fig. 2 and fig. 3, the antifuse gate 133, the antifuse gate dielectric layer 132 and the first doped region 15 constitute an antifuse transistor 41, the antifuse transistor functions as a capacitor, the first doped region 15, the second doped region 19 and the select gate structure 14 constitute a select transistor 43, and since no L DD structure is disposed between the first doped region 15 and the select gate structure 14, in other words, an equivalent resistor 42 is connected in series between the first doped region 15 and the select gate structure 14, the equivalent resistor 42 can achieve a voltage dividing effect, so as to weaken the damage of the electric field to the select gate dielectric layer 142, improve the reliability of the select transistor 43, and improve the electrical performance of the antifuse memory cell.

The utility model discloses the first embodiment does not set up L DD structure between first doped region 15 and select gate structure 14, only remain with second doped region 19 and select gate structure 14 between unilateral L DD structure, third doped region 17. because the existence of L DD structure can increase the overlap region area of the strong electric field region between select gate structure 14 and the first doped region 15, consequently when not setting up L DD structure between first doped region 15 and select gate structure 14, the strong electric field region that the instantaneous high voltage that first doped region 15 bore formed reduces with the overlap region area of select gate structure 14, has reduced the direct damage of strong electric field to antifuse grid dielectric layer 142, in addition, because do not set up L DD structure between first doped region 15 and select gate structure 14, be equivalent to having established ties equivalent resistance and can reach the partial pressure effect between first doped region 15 and select gate structure 14, has weakened the damage of electric field to select gate dielectric layer 142.

The second embodiment of the present invention further provides an antifuse memory cell, which is different from the previous embodiment in that, in the present embodiment, the antifuse memory cell further includes a fourth doped region and a fifth doped region. The fourth doped region is positioned in the substrate and is contacted with the first doped region, the fourth doped region is positioned between the first doped region and the selective grid structure, and the doped ion type of the fourth doped region is different from that of the first doped region; the fifth doping area is positioned in the substrate and is contacted with the second doping area, the fifth doping area is positioned below the third doping area, and the doping ion type of the fifth doping area is the same as that of the fourth doping area. The following detailed description is made with reference to the accompanying drawings, and it should be noted that the same or corresponding features as those of the foregoing embodiments can be referred to the corresponding description of the foregoing embodiments, and will not be described below in detail.

Fig. 4 is a schematic cross-sectional view of an antifuse memory cell according to a second embodiment of the present invention.

Referring to fig. 4, the present embodiment provides an antifuse memory cell including: a substrate 31; a select gate structure 34; a first doped region 35 and a second doped region 39; antifuse gate dielectric layer 332 and antifuse gate 333; a third doped region 37; a fourth doped region 36 located in the substrate 31 and contacting the first doped region 35, the fourth doped region 36 located between the first doped region 35 and the select gate structure 34, and a type of doped ions in the fourth doped region 36 being different from a type of doped ions in the first doped region 35; a fifth doped region 38, the fifth doped region 38 is located in the substrate 31 and contacts the second doped region 39, the fifth doped region 38 is located under the third doped region 37, and the doping ion type of the fifth doped region 38 is the same as that of the fourth doped region 36.

The third doped region 37 is an L DD structure for an antifuse memory cell the fourth doped region 36 and the fifth doped region 38 serve as HA L O (halo) regions for the antifuse memory cell.

The fourth doped region 36 is disposed to facilitate suppressing ion diffusion of the first doped region 35, so as to fix the breakdown region on the edge of the first doped region 35, and since the breakdown voltage perpendicular to the edge direction is higher than the breakdown voltage of the select gate dielectric layer 342 perpendicular to the substrate direction, the arrangement of the fourth doped region 36 can improve the breakdown voltage, thereby achieving the purpose of protecting the select gate structure 34.

In this embodiment, the depth of the fourth doping region 36 in the substrate 31 is greater than the depth of the first doping region 35 in the substrate 31. When the fourth doping region 36 is located at a depth in the substrate 31 that is greater than a depth of the first doping region 35 in the substrate 31, the fourth doping region 36 can inhibit the doping ions in the first doping region 35 from diffusing into the substrate 31 below the first doping region 35, thereby inhibiting the substrate leakage current caused by the ion diffusion.

The fifth doped region 38 is used to suppress the leakage current and source-drain punch-through problem caused by the ion diffusion of the second doped region 39.

In this embodiment, the fourth doping region 36 inhibits ion diffusion of the first doping region 35, and the fifth doping region 38 inhibits ion diffusion of the second doping region 36, that is, the HA L O region including the fourth doping region 36 and the fifth doping region 38 inhibits leakage current and source-drain punch-through caused by ion diffusion of the first doping region 35 and the second doping region 36, in addition, the fourth doping region 36 is beneficial to making up for the problem of resistance increase between the first doping region 35 and the second doping region 39 caused by single-side L DD structure loss, so that saturation current is increased, and the reaction speed of the antifuse memory cell is increased.

In this embodiment, no L DD structure is disposed between the first doped region 35 and the select gate structure 34, the overlapping area between the strong electric field region formed by the transient high voltage borne by the first doped region 35 and the select gate structure 34 is reduced, which reduces the direct damage of the strong electric field to the select gate dielectric layer 342 in the select gate structure 34, and in addition, since no L DD structure is disposed between the first doped region 35 and the select gate structure 34, it is equivalent to serially connecting a resistor between the first doped region 35 and the select gate structure 34 and achieving the voltage dividing effect, thereby reducing the damage of the electric field to the select gate dielectric layer 342.

In addition, the anti-fuse memory cell is provided with a fourth doping region 36 which is in contact with the first doping region 35, a fifth doping region 38 which is in contact with the second doping region 39, and an HA L O region which is formed by the fourth doping region 36 and the fifth doping region 38 plays a role of inhibiting the ion diffusion of the first doping region 35 and the second doping region 39, so that the problems of leakage current and source-drain punch-through caused by the ion diffusion of the first doping region 35 and the second doping region 39 are inhibited.

Correspondingly, the embodiment of the present invention further provides a manufacturing method for manufacturing the antifuse memory cell, including: providing a substrate, wherein a selection gate structure is arranged on the substrate, a first doping region and a second doping region are respectively formed in the substrate on two opposite sides of the selection gate structure, and the doping ion types of the first doping region and the second doping region are the same; and forming a third doping area before forming the second doping area, wherein the third doping area is positioned in the substrate and is contacted with the second doping area, the type of doping ions of the third doping area is the same as that of the second doping area, and the concentration of the doping ions of the third doping area is less than that of the second doping area.

The following describes a method for manufacturing an antifuse memory cell according to an embodiment of the present invention in detail with reference to the accompanying drawings.

Fig. 5 to 8 are schematic cross-sectional structures corresponding to steps of a method for manufacturing an antifuse memory cell according to a first embodiment of the present invention. In this embodiment, in the process step of forming the select gate structure, the anti-fuse gate dielectric layer and the anti-fuse gate are formed at the same time.

Referring to fig. 5, a substrate 11 is provided, and a first doped region 15 is formed in the substrate 11 by an ion implantation process.

The first doped region 15 serves as a source or drain for a subsequent select transistor and also as a single-sided source/drain for an antifuse transistor.

The forming process of the first doped region 15 includes: forming a patterned mask layer 102 on the surface of the substrate 11, wherein the patterned mask layer 102 covers the surfaces of the substrate 11 except the surface of the substrate 11 corresponding to the first doping region 15 in the vertical direction; ion implantation is performed by using the patterned mask layer 102 as a mask to form the first doped region 15.

In this embodiment, forming the first doped region 15 further includes forming a well region (not shown) and forming the isolation structure 12. The doped ion type of the well region can be N-type or P-type, which is opposite to the type of the selection transistor in the anti-fuse memory cell. The material of the isolation structure may be an oxide or a nitride.

Referring to fig. 6 and 7, a select gate structure 14 is formed on a substrate 31, and a first doped region 15 is located in the substrate at one side of the select gate structure 14; in the process step of forming select gate structure 14, an anti-fuse gate dielectric layer 132 and an anti-fuse gate 133 overlying anti-fuse gate dielectric layer 132 are simultaneously formed on first doped region 15. Wherein the antifuse gate dielectric layer 132 is partially located on the first doped region 15.

Select gate structure 14 includes a select gate 143 and a select gate dielectric layer 142. Specifically, in the process step of forming select gate dielectric layer 142, anti-fuse gate dielectric layer 132 is formed at the same time; in the process step of forming select gate 143, anti-fuse gate 133 is simultaneously formed.

In this embodiment, antifuse gate dielectric layer 142 and antifuse gate 143 are formed in the same process step as select gate structure 14. It should be noted that in other embodiments, the anti-fuse gate dielectric layer and the anti-fuse gate and select gate structures may be formed in different process steps.

The process steps for forming antifuse gate dielectric layer 132, antifuse gate 133, and select gate structure 14 include: forming a dielectric layer 140 on the surface of the substrate 11, wherein the dielectric layer 140 covers the first doped region 15, and the dielectric layer 140 provides a process basis for forming the antifuse gate dielectric layer 132 and the select gate dielectric layer 142; forming an anti-fuse gate (not shown) on dielectric layer 140; forming a graphical mask on the anti-fuse grid; and etching the anti-fuse gate and the dielectric layer 140 by using the patterned mask as a mask, thereby forming an adjacent and independent anti-fuse gate structure and a select gate structure 14, wherein the anti-fuse gate structure comprises an anti-fuse gate 133 and an anti-fuse gate dielectric layer 132, and the select gate structure 14 comprises a select gate 143 and a select gate dielectric layer 142.

The dielectric layer 140 may be formed by a conventional vacuum deposition technique, such as furnace thermal oxidation, atomic layer deposition (a L D), Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and furnace thermal oxidation in this embodiment.

In this embodiment, the first doped region 15 is formed before the anti-fuse gate dielectric layer 132 and the anti-fuse gate 133, so as to avoid the ion implantation process for forming the first doped region 15 from damaging the anti-fuse gate 133 and the anti-fuse gate dielectric layer 132, and ensure the good performance of the anti-fuse gate 133 and the anti-fuse gate dielectric layer 132.

It should be noted that, in other embodiments, the anti-fuse gate and the anti-fuse gate dielectric layer, and the select gate structure may be formed sequentially. For example, after the select gate structure and the first doped region are formed, the antifuse gate dielectric layer and the antifuse gate are formed.

Referring to fig. 8, a third doped region 17 is formed in the substrate 31 using an ion implantation process.

The third doped region 17 serves as an L DD structure connecting subsequently formed second doped regions.

The third doped region 17 is located on the opposite side of the select gate structure 14 from the first doped region 15, the type of the doped ions of the third doped region 17 is the same as that of the first doped region 15, and the concentration of the doped ions of the third doped region 17 is lower than that of the first doped region 15.

The forming process of the third doped region comprises the following steps: forming a patterned mask layer 103 on the surface of the substrate 11, wherein the patterned mask layer 103 covers the surfaces of the substrate 11 except the surface of the substrate 11 corresponding to the third doped region 17 in the vertical direction; ion implantation with a certain implantation angle is performed with the patterned mask layer 103 as a mask to form the third doped region 17.

It should be noted that the implantation angle referred to in the present application refers to an angle at which the implantation ion beam is deflected with respect to a direction perpendicular to the surface of the semiconductor substrate, i.e., an angle of an angle between the implantation ion beam and the perpendicular direction.

It should be noted that, in other embodiments, before the ion implantation of the third doped region is performed, an amorphization implantation may also be performed in the substrate on both sides of the select gate structure, so that an amorphous layer is formed on the surface of the substrate. The amorphous layer can avoid the channel effect in the ion implantation process of the third doped region, and can better control the depth of the ion implantation.

In this embodiment, in order to prevent the ion implantation process for forming the third doped region 17 from damaging the select gate structure 14, before forming the third doped region 17, the first sidewalls 141 are formed on the sidewalls of the select gate structure 14 on two opposite sides.

The forming process of the first sidewall spacers 141 includes: firstly, forming a dielectric layer (not shown) on the surface of the substrate 11, wherein the thickness of the dielectric layer is higher than the height of the selection gate structure 14; a back etching process is performed to form first sidewalls 141 on both sides of the select gate structure 14.

The material of the first sidewall 141 may be one of silicon oxide, silicon nitride, and silicon oxynitride, or a combination thereof, and the first sidewall 141 serves to protect the select gate structure 141. The dielectric layer can be formed by chemical vapor deposition or physical vapor deposition.

Referring to fig. 2, a second doped region 19 is formed in the substrate 11 on one side of the select gate structure 14, and the second doped region 19 and the first doped region 15 are respectively located on two opposite sides of the select gate structure 14.

The second doped region 19 is located in the substrate 11 on the opposite side of the select gate structure 14 from the first doped region 15, the distance between the second doped region 19 and the first doped region 15 is greater than the distance between the second doped region 17 and the first doped region 15, and the type of doped ions in the second doped region 19 is the same as that in the first doped region 15.

The forming process of the second doped region 19 includes: forming a patterned mask layer (not shown) on the surface of the substrate 11; and performing ion implantation by using the patterned mask layer as a mask to form a second doped region 19.

The first doped region 15, the select gate structure 14 and the second doped region 19 constitute a select transistor.

The first embodiment of the present invention provides a method for manufacturing an antifuse memory cell, wherein an L DD structure is not disposed between the first doped region 15 and the select gate structure 14, and only a single-side L DD structure between the second doped region 19 and the select gate structure 14, i.e. the third doped region 17, is retained, because the L DD structure increases the area of the overlapping region of the strong electric field region between the select gate structure 14 and the first doped region 15, when the L DD structure is not disposed between the first doped region 15 and the select gate structure 14, the area of the overlapping region between the strong electric field region formed by the instantaneous high voltage borne by the first doped region 15 and the select gate structure 14 is reduced, thereby reducing the direct damage of the strong electric field to the antifuse gate dielectric layer 142, and in addition, because the L DD structure is not disposed between the first doped region 15 and the select gate structure 14, it is equivalent to serially connecting an equivalent resistor between the first doped region 15 and the select gate structure 14, and thus achieving the voltage dividing effect, and reducing the damage of the electric field to the select gate dielectric layer 142.

It should be noted that, the same or corresponding manufacturing steps as those in the first method embodiment may refer to corresponding descriptions of the first method embodiment, and are not described in detail below. The second method embodiment of the present invention is different from the first method embodiment in that: forming the fourth doped region 36 and the fifth doped region 38 before or after forming the third doped region 37; the second doped region 39 is formed.

As shown in fig. 9, in the present embodiment, the fourth doping region 36 and the fifth doping region 39 are formed in the substrate 31 before the third doping region 37 is formed.

The fourth doped region 36 is located in the substrate 31 and contacts the first doped region 35, the fourth doped region 36 is located between the first doped region 35 and the select gate structure 14, and the doping ion type of the fourth doped region 36 is different from the doping ion type of the first doped region 35.

The fifth doped region 38 and the fourth doped region 36 are formed simultaneously, the fifth doped region 38 is located in the substrate 31 and contacts the second doped region 39, the fifth doped region 38 is located below the third doped region 37, and the doped ion type of the fifth doped region 38 is the same as that of the fourth doped region 36.

The process steps for forming the fourth doped region 36 and the fifth doped region 38 include: firstly, forming a patterned mask layer 304 on the surface of the substrate 31, wherein the patterned mask layer 304 covers the surfaces of the rest of the substrate 31 except the surface of the substrate 31 corresponding to the fourth doped region 36 in the vertical direction; ion implantation is performed using the patterned mask layer 304 as a mask to form the fourth doped region 36 and the fifth doped region 38.

In this embodiment, the ion implantation dose of the fourth doped region 36 is 1E12atom/cm 2-5E 13atom/cm2, the implantation energy is 20 KeV-100 KeV, the implantation angle is 0-45 degrees, and the implantation depth is 30 nm-100 nm. It should be noted that the ion implantation process for forming the fourth doped region 36 and the fifth doped region 38 may be performed in one step or in multiple steps, and is determined according to the required dopant ion concentration of the fourth doped region 36 and the fifth doped region 38.

In this embodiment, in order to prevent the ion implantation process for forming the fourth doped region 36 from damaging the antifuse gate 333 and the antifuse gate dielectric layer 332, before the fourth doped region 36 is formed, the second sidewalls 331 are formed on the sidewalls of the antifuse gate 333 and the antifuse gate dielectric layer 332 on two opposite sides. The forming process of the second sidewall 331 is the same as the forming process of the first sidewall 341, and is not described herein again. The material of the second sidewall 331 and the first sidewall 341 may be the same or different.

It should be noted that, in the embodiment of the present invention, after all the ion implantation processes are completed, annealing treatment is performed to activate the doped ions in each doped region and repair implantation damage. In the embodiment of the utility model provides an in, also can be after single ion implantation technology, carry out annealing immediately, through the doping ion in each doping region of annealing process activation many times to repair and pour into the damage. The annealing process includes a rapid thermal annealing or spike annealing process. The temperature of the annealing treatment is 950-1100 ℃ and the time is 10-30 s.

In this embodiment, the antifuse memory cell is further improved by forming the fourth doped region 36 and the fifth doped region 38. The fourth doped region 36 is formed to be beneficial to inhibiting the ion diffusion of the first doped region 35, so that the breakdown region is fixed on the edge of the first doped region 35, and the breakdown voltage in the direction perpendicular to the edge is higher than the breakdown voltage of the select gate dielectric layer in the direction perpendicular to the substrate, so that the breakdown voltage can be improved due to the arrangement of the fourth doped region, and the purpose of protecting the select gate structure is achieved.

In addition, the fourth doped region 36 is disposed to facilitate suppressing ion diffusion of the first doped region 35, and the fifth doped region 38 is formed to facilitate suppressing ion diffusion of the second doped region 36, that is, the HA L O region including the fourth doped region 36 and the fifth doped region 38 suppresses leakage current and source-drain punch-through caused by ion diffusion of the first doped region 35 and the second doped region 36. in addition, the fourth doped region 36 is advantageous to compensate for the problem of resistance increase between the first doped region 35 and the second doped region 39 due to the single-sided L DD structure loss, thereby increasing the reaction speed of the antifuse memory cell.

The embodiment of the utility model provides a manufacturing method of anti-fuse memory cell, set up the third doped region between select gate structure and second doped region, the doping ion type in third doped region and second doped region is the same, do not set up L DD structure between first doped region and select gate structure promptly when anti-fuse gate dielectric layer takes place dielectric breakdown, first doped region bears the high voltage that passes over, because the overlapping area of L DD structure can increase the strong electric field region between select gate structure and the first doped region, consequently, when not setting up L DD structure between first doped region and the select gate structure, the overlapping area of the strong electric field region that the instantaneous high voltage that first doped region bore formed and select gate structure reduces, has reduced the direct damage of strong electric field to select gate structure, in addition, because do not set up L DD structure between first doped region and select gate structure, be equivalent to having established ties resistance and can reach the partial pressure effect between first doped region and select gate structure, has weakened the electric field damage.

It will be understood by those skilled in the art that the foregoing embodiments are specific examples of the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in its practical application. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. An antifuse memory cell, comprising:

a substrate having a select gate structure thereon;

the drain electrode and the source electrode are respectively positioned in the substrate at two opposite sides of the selective gate structure;

the anti-fuse grid dielectric layer is positioned on the drain electrode, and the anti-fuse grid electrode is positioned on the anti-fuse grid dielectric layer;

l DD structure, the L DD structure being of the same type as the source dopant ions and having a dopant ion concentration less than the source is located within the substrate and in contact with the source, the L DD structure is located between the source and the select gate structure.

2. The anti-fuse memory cell of claim 1, wherein the select gate structure comprises a select gate dielectric layer and a select gate on a top surface of the select gate dielectric layer; the selection gate dielectric layer and the anti-fuse gate dielectric layer are both made of silicon oxide; the thickness of the anti-fuse gate dielectric layer is smaller than or equal to that of the gate dielectric layer.

3. The antifuse memory cell of claim 1, further comprising a first HA L O region different from the drain dopant ion type, the first HA L O region being within the substrate and in contact with the drain, the first HA L O region being between the drain and the select gate structure.

4. The antifuse memory cell of claim 3, wherein the first HA L O region is located at a greater depth within the substrate than the drain is located within the substrate.

5. The antifuse memory cell of claim 3, further comprising a second HA L O region doped with the same ion type as the first HA L O region, the second HA L O region being within the substrate and in contact with the source, the second HA L O region being below the L DD structure.

6. The antifuse memory cell of claim 3, wherein the drain is horizontally oriented toward the source with a spacing between the drain and the select gate structure.

7. The antifuse memory cell of claim 6, wherein the spacing between the edge of the drain toward the select gate structure and the sidewall of the select gate structure toward the drain is between 10nm and 800 nm.

8. The antifuse memory cell of claim 1, wherein the antifuse gate is oriented horizontally to the select gate structure, and wherein a spacing between the antifuse gate and the select gate structure is 400nm to 800 nm.

9. The antifuse memory cell of claim 1, wherein the antifuse gate dielectric layer is partially over the drain.