CN211187504U - Electrotomy auxiliary system based on FPGA - Google Patents

Abstract

An FPGA-based electrostomy auxiliary system comprises an endoscope system, a first FPGA image processing module, a first ARM microprocessor, a second FPGA image processing module, a second ARM microprocessor, a second FPGA image processing module and a display; the endoscope system comprises a CCD camera and a video decoding chip which are connected with each other, and the video decoding chip, a first FPGA image processing module, a first ARM microprocessor, a second FPGA image processing module, a second ARM microprocessor, a second FPGA image processing module and a display are connected in sequence. Full play FPGA image processing module is at the parallel data processing ability in the image processing field, and data processing is fast, can realize signal real-time processing, thereby makes the utility model discloses can break away from the computer and realize that the endoscope makes a video recording and video display. The utility model discloses simple structure, it is small, with low costs, easily carry.

Description

Electrotomy auxiliary system based on FPGA

Technical Field

The utility model relates to the technical field of medical equipment, especially, relate to an electrotomy auxiliary system based on FPGA.

Background

Prostatic hyperplasia is a common disease and frequently encountered disease of old male patients. The bipolar resection for prostate hyperplasia is the most popular prostate hyperplasia cutting operation, and at present, the endoscope is mainly used for shooting, the shooting picture is transmitted to the computer for display, and the doctor observes the shooting picture displayed by the computer, and cuts the mucosa at the junction of the middle lobe gland and the bladder neck with a small circular knife in an arc shape to resect the hyperplasia prostate gland. The medical endoscope system is used as an auxiliary imaging tool and is a medical electronic instrument for acquiring and processing endoscope images, and the quality of the imaging quality of the medical endoscope system directly influences clinical diagnosis and treatment.

The endoscope camera system has the working principle that: the endoscope receives reflected light of a mucosal surface in a body cavity, images the reflected light by the lens, transmits the image to the camera device to collect the image and converts the image into an electric signal; then, the video signal is transmitted to a processing center, and the storage and processing of the image are realized in the processing center; and finally, outputting the image to a display through an image interface to realize the real-time display of the color image of the detected target. It follows that the endoscope system is essentially a conventional color camera system for medical imaging.

The camera system mainly has an analog type and a digital type, the technology of the camera system is developed mature, but the camera system is not beneficial to the subsequent processing of images due to the fact that the camera system is an analog video; the latter is relatively flexible in design and is easy to implement various types of processing of images. With the development of technology and the coming of digital information age, the information content of images is getting larger and larger, and digital camera systems have become the main trend of development.

At present, a digital camera system adopted in the prostate hyperplasia surgery mainly adopts a computer to receive image data output by a digital image sensor, and the image processing, storage and display are realized through the computer.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to solve the above-mentioned technical problem to a resecting operation auxiliary system based on FPGA is provided.

The utility model discloses a following technical scheme realizes:

an FPGA-based electrostomy auxiliary system comprises an endoscope system, a first FPGA image processing module, a first ARM microprocessor, a second FPGA image processing module, a second ARM microprocessor, a second FPGA image processing module and a display; the endoscope system comprises a CCD camera and a video decoding chip which are connected with each other, wherein the video decoding chip, a first FPGA image processing module, a first ARM microprocessor, a second FPGA image processing module, a second ARM microprocessor, a second FPGA image processing module and a display are connected in sequence;

the CCD camera collects optical images of the endoscope, outputs analog video signals, converts the analog video signals into digital video signals through decoding of the video decoding chip, and sends the digital video signals to the first FPGA image processing module;

the first FPGA image processing module is used for preprocessing the digital video signal, converting the digital video signal into a matrix form and sending the matrix form to the first ARM microprocessor;

the first ARM microprocessor compresses the matrix video signal and sends the matrix video signal to the second FPGA image processing module;

the second FPGA image processing module performs parallel matrix processing on the compressed matrix video signals and sends corresponding video signals to a second ARM microprocessor;

the second ARM microprocessor amplifies the matrix video signals and sends the amplified matrix video signals to a third FPGA image processing module;

and the third FPGA image processing module performs format conversion on the matrix video signal after the amplification processing.

Furthermore, the models of the first FPGA image processing module, the second FPGA image processing module and the third FPGA image processing module are PYNQ-Z2.

Furthermore, the models of the first ARM microprocessor and the second ARM microprocessor are both ARM Contex-A9.

Further, the model of the CCD camera is DE L ON HD 380B.

Further, the video decoding chip model is ADV 7123.

Compared with the prior art, the utility model discloses main beneficial effect as follows:

(1) the utility model overcomes the technical defects of the prior art, structurally combines a plurality of FPGA image processing modules with a plurality of ARM microprocessors, and the first FPGA image processing module preprocesses the digital video signals, converts the digital video signals into a matrix form and sends the matrix form to the first ARM microprocessors; the first ARM microprocessor compresses the matrix video signal and sends the matrix video signal to the second FPGA image processing module; the second FPGA image processing module performs parallel matrix processing on the compressed matrix video signals and sends corresponding video signals to the second ARM microprocessor; and the second ARM microprocessor converts the video signal after matrix processing into an image format, amplifies the compressed video signal and sends the amplified video signal to a display for displaying. The FPGA image processing module and the ARM microprocessor are reasonably arranged structurally, partial data with small data volume and short consumed time are processed through the ARM microprocessor, and partial data with large data volume and long consumed time are processed through the FPGA image processing module. Full play FPGA image processing module is at the parallel data processing ability in the image processing field, and data processing is fast, can realize signal real-time processing, thereby makes the utility model discloses can break away from the computer and realize that the endoscope makes a video recording and video display.

(2) The utility model discloses simple structure, it is small, with low costs, easily carry, important market value has.

Drawings

FIG. 1 is a schematic view of the structure of the present invention

FIG. 2 is a schematic diagram of the hardware connection between the first FPGA image processing module and the first ARM microprocessor

Detailed Description

The technical solution of the present invention will be further specifically described below with reference to the drawings of the specification.

As shown in fig. 1, an auxiliary system for an electrostomy based on an FPGA comprises an endoscope system, a first FPGA image processing module, a first ARM microprocessor, a second FPGA image processing module, a second ARM microprocessor, a second FPGA image processing module and a display; the endoscope system comprises a CCD camera and a video decoding chip which are connected with each other, wherein the video decoding chip, a first FPGA image processing module, a first ARM microprocessor, a second FPGA image processing module, a second ARM microprocessor, a second FPGA image processing module and a display are connected in sequence;

the CCD camera collects optical images of the endoscope, outputs analog video signals, converts the analog video signals into digital video signals through decoding of the video decoding chip, and sends the digital video signals to the first FPGA image processing module;

the first FPGA image processing module is used for preprocessing the digital video signal, converting the digital video signal into a matrix form and sending the matrix form to the first ARM microprocessor;

the first ARM microprocessor compresses the matrix video signal and sends the matrix video signal to the second FPGA image processing module;

the second FPGA image processing module performs parallel matrix processing on the compressed matrix video signals and sends corresponding video signals to a second ARM microprocessor;

the second ARM microprocessor amplifies the matrix video signals and sends the amplified matrix video signals to a third FPGA image processing module;

and the third FPGA image processing module performs format conversion on the matrix video signal after the amplification processing.

Preferably, the models of the first FPGA image processing module, the second FPGA image processing module and the third FPGA image processing module are PYNQ-Z2.

Specifically, PYNQ-Z2 provides rich hardware peripheral interfaces and rich resources of logic gate circuits, and can process high frame rate video and real-time signals.

Preferably, the first ARM microprocessor and the second ARM microprocessor are both in ARM Contex-A9 models.

Specifically, the first FPGA image processing module comprises a USB interface, and video signals collected by a CCD camera of the endoscope system are sent to the first FPGA image processing module through the USB interface. Because the Video signal collected by the CCD camera is in an AVI (audio Video interleaved) format, and the first FPGA image processing module cannot directly operate the Video signal in the AVI format, the first FPGA image processing module firstly preprocesses the Video signal in the AVI format collected by the CCD camera, converts the color and brightness of pixel points of the Video signal in the AVI format into a matrix form, and sends the matrix form to the first ARM microprocessor.

Because the occupied memory of the video is large, the video transmission speed is possibly slow, a certain time delay exists between an output image and an input image, and the real-time performance of the input video and the output video must be ensured in the operation, so that the input video needs to be compressed, the occupied memory of the video is reduced, the transmission speed is accelerated, and the real-time performance of the video signal is ensured. After the first ARM microprocessor receives the matrix video signals sent by the first FPGA image processing module, the video signals are compressed, the memory occupied by the video is reduced, the video signal processing amount is reduced, and the video signal processing speed is increased.

And the first ARM microprocessor compresses the video signals and then sends the compressed video signals to the second FPGA image processing module, and the second FPGA image processing module performs parallel matrix processing on the compressed matrix video signals. Because the video signal is compressed by the first ARM microprocessor, the second FPGA image processing module can complete parallel matrix processing of the matrix video signal in a short time and send the matrix-processed video signal to the second ARM microprocessor.

Since the matrix video signal has been compressed by the first ARM microprocessor, video sharpness is reduced. Therefore, the video signal needs to be amplified again to improve the video definition and meet the actual requirements of the operation. And after receiving the video signal subjected to matrix processing, the second ARM microprocessor amplifies the matrix video signal and sends the amplified matrix video signal to the third FPGA image processing module.

Since the matrix video signal cannot be directly displayed on the display screen, the matrix video signal needs to be converted into an AVI format or other video formats so that the video can be directly displayed on the display screen. And after receiving the amplified matrix video signal, the third FPGA image processing module converts the video signal into an AVI format or other video formats so as to directly display a corresponding video on a display screen.

Further, the model of the CCD camera is DE L ON HD380B, and the resolution is 1920X 1080.

Further, the video decoding chip model is ADV 7123.

Specifically, as shown in fig. 2, a schematic diagram of a hardware connection between the first FPGA image processing module and the first ARM microprocessor is shown.

Specifically, ADDr1-ADDr9 are address buses, D0-D15 are data buses, nGCS5 are bank chip selects of the first ARM microprocessor, nOE is a read enable signal of the first ARM microprocessor, nWE is a write enable signal of the first ARM microprocessor, and EINT10 is an interrupt signal of the first ARM microprocessor.

Specifically, the hardware connection relationship between the second FPGA image processing module and the first ARM microprocessor, the hardware connection relationship between the second FPGA image processing module and the second ARM microprocessor, and the hardware connection relationship between the third FPGA image processing module and the second ARM microprocessor are the same as those shown in fig. 2.

The video decoding chip converts analog video signals into digital video signals, and FPGA image processing module converts digital video signals into the matrix form to matrix form video signals carries out matrix processing, enlargies and handles, format conversion, and ARM microprocessor compresses, enlargies video signals, is prior art, not the utility model discloses improve and the scope of protection. In specific implementation, the method can be realized by adopting the prior art. The utility model discloses what improve and protect is a structure based on FPGA's electrotomy auxiliary system.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and any modifications and equivalent changes made according to the technical spirit of the present invention should be included in the protection scope of the present invention.

Claims (5)

1. The utility model provides an electrotomy auxiliary system based on FPGA which characterized in that: the endoscope system comprises an endoscope system, a first FPGA image processing module, a first ARM microprocessor, a second FPGA image processing module, a second ARM microprocessor, a second FPGA image processing module and a display; the endoscope system comprises a CCD camera and a video decoding chip which are connected with each other, wherein the video decoding chip, a first FPGA image processing module, a first ARM microprocessor, a second FPGA image processing module, a second ARM microprocessor, a second FPGA image processing module and a display are connected in sequence;

the CCD camera collects optical images of the endoscope, outputs analog video signals, converts the analog video signals into digital video signals through decoding of the video decoding chip, and sends the digital video signals to the first FPGA image processing module; the first FPGA image processing module is used for preprocessing the digital video signal, converting the digital video signal into a matrix form and sending the matrix form to the first ARM microprocessor; the first ARM microprocessor compresses the matrix video signal and sends the matrix video signal to the second FPGA image processing module; the second FPGA image processing module performs parallel matrix processing on the compressed matrix video signals and sends corresponding video signals to a second ARM microprocessor; the second ARM microprocessor amplifies the matrix video signals and sends the amplified matrix video signals to a third FPGA image processing module; and the third FPGA image processing module performs format conversion on the matrix video signal after the amplification processing.

2. The FPGA-based electrostomy assistance system of claim 1, wherein: the models of the first FPGA image processing module, the second FPGA image processing module and the third FPGA image processing module are PYNQ-Z2.

3. The FPGA-based electrostomy assistance system of claim 1, wherein: the models of the first ARM microprocessor and the second ARM microprocessor are both ARM Contex-A9.

4. The FPGA-based electrostomy assistance system of claim 1, wherein the model number of the CCD camera is DE L ON HD 380B.

5. The FPGA-based electrostomy assistance system of claim 1, wherein: the video decoding chip is ADV 7123.

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