CN211151936U - Power switch circuit - Google Patents

Abstract

The utility model discloses a power switch circuit (100), including power (VCC), resistive element, electric capacity component (C32), switch button (SW-PB), first switching element (101), second switching element (102), third switching element (103) and power output end (V-PB)_out). The first switch element (101) is electrically connected to the capacitor element (C32), the switch button (SW-PB), the second switch element (102), and the third switch element (103), respectively. The second switching element (102) is electrically connected to the third switching element (103). The switch circuit (100) controls the on/off of the first switch element (101) by pressing the switch button (SW-PB), thereby controlling the second switch element (102)And further controls the on-off of the third switching element (103) to complete the switching function of the power switching circuit (100). The utility model discloses a field effect transistor of low-power consumption, with low costs and circuit structure is simple easily realizes.

Description

Power switch circuit

Technical Field

The present invention relates generally to power supply. More specifically, the present invention relates to a power switching circuit.

Background

Conventional one-touch switch circuits all require the intervention of a central processing unit ("CPU"). Under extreme conditions such as CPU crash, the situation that the computer cannot be started or shut down may occur. Secondly, in the prior art, a professional power management unit ("PMU") is generally used for power switch control or a professional chip is used for power switch control, but because the PMU or the professional chip has high cost and long purchase period, the prior art cannot realize the reduction of the cost of the bill of material and the improvement of the delivery speed. In addition, some conventional switching circuits, such as triode switching circuits, have large power consumption, and are not suitable for high-frequency and high-speed circuits and scenes requiring large current.

SUMMERY OF THE UTILITY MODEL

For having overcome above-mentioned prior art one or more shortcoming to it is originally to provide a switch circuit that can satisfy the designing requirement, the utility model discloses need not to utilize the CUP to control, but adopt the field effect transistor as switching element to control switching element through the charge-discharge of electric capacity, and then realize switch circuit's power supply and outage function.

In order to solve one or more problems in the above-mentioned background art at least, the utility model discloses a novel power switch circuit, including power, switch button, first switching element, second switching element, third switching element and power output.

A first end of the first switch element is electrically connected with the power supply and a second end of the second switch element respectively, a second end of the first switch element is electrically connected with the switch key, and a third end of the first switch element is grounded; a first end of the second switching element is grounded, and a third end of the second switching element is electrically connected with a second end of the third switching element; the first end of the third switching element is electrically connected with the power supply, and the third end of the third switching element is the power supply output end;

wherein when the switch key is pressed and released in an initial state in which the power supply is turned on, the first switching element is controlled to be turned off to turn on the second switching element electrically connected thereto, the turning on of the second switching element turns on the third switching element electrically connected thereto, and the turning on of the third switching element turns on the power supply output terminal,

when the power output end is in the open state, the switch key is pressed and released, the first switch element is controlled to be conducted, so that the second switch element electrically connected with the first switch element is disconnected, the third switch element electrically connected with the second switch element is disconnected by the disconnection of the second switch element, and the power output end is closed by the disconnection of the third switch element.

In one embodiment, the first switch element is a first NMOS field effect transistor, wherein a first terminal of the first switch element is a drain of the first NMOS field effect transistor, a second terminal is a gate of the first NMOS field effect transistor, and a third terminal is a source of the first NMOS field effect transistor; the second switch element is a second NMOS field effect transistor, wherein a first end of the second switch element is a source electrode of the second NMOS field effect transistor, a second end of the second switch element is a grid electrode of the second NMOS field effect transistor, and a third end of the second switch element is a drain electrode of the second NMOS field effect transistor; the third switching element is a PMOS field effect transistor, wherein the first end of the third switching element is a source electrode of the PMOS field effect transistor, the second end of the third switching element is a grid electrode of the PMOS field effect transistor, and the third end of the third switching element is a drain electrode of the PMOS field effect transistor;

the power switch circuit further comprises a first resistor, a second resistor, a third resistor and a fourth resistor, wherein one end of the first resistor is electrically connected with the power supply, and the other end of the first resistor is electrically connected with the drain electrode of the first NMOS field effect transistor; one end of the second resistor is electrically connected with the drain electrode of the first NMOS field effect transistor, and the other end of the second resistor is electrically connected with the switch key; one end of the third resistor is electrically connected with the drain electrode of the second NMOS field effect transistor, and the other end of the third resistor is electrically connected with the source electrode of the PMOS field effect transistor; one end of the fourth resistor is electrically connected with the grid electrode of the first NMOS field effect transistor, and the other end of the fourth resistor is electrically connected with the resistor and the grid electrode of the PMOS field effect transistor.

In another embodiment, the power switch circuit further includes a capacitive element, one end of the capacitive element is grounded, and the other end of the capacitive element is electrically connected to the second resistor and one end of the switch button, and the capacitive element performs charge and discharge operations through the first resistor and the second resistor, so as to control the on or off of the first NMOS fet.

In yet another embodiment, the drain of the first NMOS field effect transistor is electrically connected to the second resistor and the power supply through the first resistor, respectively, the gate of the first NMOS field effect transistor is electrically connected to the drain of the second NMOS field effect transistor and the gate of the PMOS field effect transistor through the second resistor and the third resistor, respectively, and the source of the first NMOS field effect transistor is grounded.

In another embodiment, the gate of the second NMOS field effect transistor is electrically connected to the drain of the first NMOS field effect transistor, the drain of the second NMOS field effect transistor is electrically connected to the gate of the PMOS field effect transistor and the power supply through the third resistor and the gate of the first NMOS field effect transistor through the fourth resistor, respectively, and the source of the second NMOS field effect transistor is grounded.

In another embodiment, the gate of the PMOS fet is electrically connected to the drain of the second NMOS fet, the source of the PMOS fet is electrically connected to the power supply, and the drain of the PMOS fet is the power supply output terminal of the power switch circuit.

In one embodiment, in an initial state of turning on the power supply, the voltage of the capacitive element is zero, the power supply is pressurized to the gate of the first NMOS fet through the third resistor and the fourth resistor to turn on the first NMOS fet, and the gate voltage of the second NMOS fet is pulled down, so that the second NMOS fet is turned off, thereby turning off the PMOS fet electrically connected thereto, and the turning off of the PMOS fet turns off the power supply output terminal.

In another embodiment, in an initial state of turning on the power supply, when the switch button is pressed and released, the zero voltage of the capacitive element is transferred to the gate of the first NMOS fet to turn from on to off, and simultaneously the capacitive element starts to be charged through the first resistor and the second resistor until the voltage of the capacitive element is greater than the on voltage of the first NMOS fet, the power supply is pressurized to the gate of the second NMOS fet through the first resistor to turn the second NMOS fet from off to on, thereby pulling down the gate voltage of the PMOS fet electrically connected thereto, causing the PMOS fet to turn from off to on, and the PMOS fet to turn on to turn the power supply output terminal from off to on.

In yet another embodiment, when the power output terminal is in the on state, the switch button is pressed and released, the high voltage of the capacitive element is transmitted to the gate of the first NMOS fet to turn it from off to on, and then the gate voltage of the second NMOS fet is pulled down, so that the second NMOS fet turns from on to off, thereby causing the PMOS fet electrically connected thereto to turn from on to off, and the PMOS fet being off to turn the power output terminal from on to off.

In one embodiment, the switch button is a self-resetting switch.

The utility model discloses a switch circuit has realized providing and the function of disconnected power supply to external equipment. The utility model relates to a principle is ingenious, in the switching circuit working process, through the produced voltage variation of electric capacity component's charge-discharge and then control switch circuit switch on and break off to accomplish the power supply and the outage function to external equipment. The utility model discloses a circuit does not have CPU's intervention control, has higher reliability. In addition, the utility model discloses a metal-oxide semiconductor field effect transistor for the circuit is simple, realize easily and low power dissipation, small in noise.

Drawings

The above-described features of the present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by reading the following detailed description with reference to the accompanying drawings. The drawings in the following description are only some embodiments of the invention, and other drawings can be derived by those skilled in the art without inventive effort, wherein:

fig. 1 is a schematic block diagram illustrating a power switching circuit according to the present invention; and

fig. 2 is a detailed circuit diagram showing a power switch circuit according to an embodiment of the present invention.

Detailed Description

The utility model discloses a power switch circuit adopts the three switch element of low-power consumption, through utilizing switch button to control switching on and off of the first switch element to control switching on and off of the second switch element rather than the electricity is connected to through switching on and off of second switch element control rather than the third switch element's of electricity connection switching on and off, with this open or close as the power output end of third switch element one end. Based on such control principle, the utility model discloses a switch circuit realizes supplying power and the function of outage to external equipment.

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It is to be understood that the embodiments described herein are part of the invention and not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by the skilled in the art without creative work belong to the protection scope of the present invention.

Fig. 1 is a schematic block diagram illustrating a power switching circuit 100 according to the present invention. As shown in the drawings, the power switch circuit 100 of the present invention mainly includes a power VCC, a switch button SW-PB, a first switch element 101, a second switch element 102, a third switch element 103, and a power output terminal V, in addition to other specific elements not shown_out. For ease of describing the individual connection ends of the elements, the figures showArabic numerals 1, 2 and 3 denote first, second and third terminals of a switching element, respectively, and the power supply output terminal V_outAnd is electrically connected to an external device (not shown) that requires power to be supplied and removed.

As can be seen from fig. 1, a first terminal of the first switch element 101 is electrically connected to the power source VCC and a second terminal of the second switch element 102, a second terminal of the first switch element 101 is electrically connected to the switch button SW-PB, and a third terminal of the first switch element 101 is grounded. A first terminal of the second switching element 102 is grounded, and a third terminal of the second switching element 102 is electrically connected to a second terminal of the third switching element 103. The first end of the third switch element 103 is electrically connected with a power supply VCC, and the third end of the third switch element 103 is a power supply output end V_out。

The operation of the power switching circuit 100 will be described with reference to fig. 1.

First, in an initial state where the power source VCC is turned on, the switch button SW-PB is in an off state, and at this time, the power source VCC pressurizes the first switching element 101 through an internal circuit, causing it to be turned on, so that the second switching element 102 electrically connected thereto is controlled to be turned off due to receiving a zero voltage. Further, the turning off of the second switching element 102 causes the power supply VCC to act on the third switching element 103 through the internal circuit, causing the third switching element 103 to turn off. And the turning off of the third switching element 103 makes the power supply output terminal V_outClosing, at this time, the power supply output end V_outThe voltage of (c) is zero.

Then, when the external device needs to be powered, the switch button SW-PB is pressed and released in the initial state of turning on the power source VCC. At this time, the first switching element 101 receives the zero voltage transmitted from the internal circuit, causing it to be controlled to turn from on to off, while the power source VCC acts on the second switching element 102 through the internal circuit, causing the second switching element 102 to turn from off to on. Further, the conduction of the second switch element 102 makes the third switch element 103 electrically connected to it turn from off to on, and the conduction of the third switch element 103 makes the power output terminal V_outIs turned on, at the moment, the power output end V_outProviding a voltage to an external device.

Then, when the power of the external device needs to be cut off, the power output end V is connected with the power supply_outIn the on state, switch button SW-PB is pressed again and released. At this time, the first switching element 101 receives a high voltage from the internal circuit, causing its state to transition from off to on, so that the second switching element 102 electrically connected thereto is controlled to transition from on to off as a result of receiving a zero voltage. Further, the turning off of the second switching element 102 causes the power supply VCC to act on the third switching element 103 through an internal circuit, causing the third switching element 103 to turn from on to off. And the turning off of the third switching element 103 makes the power supply output terminal V_outIs changed from on to off, and the power output end V is switched to_outIs zero, and thus stops supplying power to the external device.

The power switching circuit 100 of the present invention is generally described above with reference to fig. 1, and the above-mentioned internal circuit is not described for the sake of brevity. In light of the disclosure and teachings of the present invention, those skilled in the art can construct the above-mentioned internal circuit with various specific circuit configurations and with appropriate components, thereby implementing the present invention to implement the on-off control of the circuit by using three switching elements and keys.

Fig. 2 is a detailed circuit diagram illustrating the power switching circuit 100 according to an embodiment of the present invention. It should be noted that the power switch circuit 100 shown in fig. 2 can be understood as an exemplary specific implementation of the power switch circuit 100 in fig. 1, and therefore, the details of the power switch circuit 100 described in conjunction with fig. 1 also apply to the description of the power switch circuit 100 in fig. 2, that is, the circuit elements and the connection relationships shown in fig. 2 also apply to the power switch circuit 100 in fig. 1. The connection relationship and the operation principle of the power switching circuit 100 will be described in detail below with reference to fig. 2.

In one or more embodiments, the aforementioned switching element of the present invention can be implemented as an N-channel metal-oxide semiconductor field effect transistor ("NMOS field effect transistor") or a P-channel metal-oxide semiconductor field effect transistor ("PMOS field effect transistor"), or can also be other switching elements or modules capable of implementing the switching function of the present invention.

Based on the above, in the power switch circuit 100 shown in fig. 2, the first switch element 101 in fig. 1 may be embodied as a first NMOS fet Q1, wherein the first terminal of the first switch element 101 is the drain of the first NMOS fet Q1, the second terminal is the gate of the first NMOS fet Q1, and the third terminal is the source of the first NMOS fet Q1. Similarly, the second switch element 102 may be embodied as a second NMOS field effect transistor Q2, wherein the first terminal of the second switch element 102 is the source of the second NMOS field effect transistor Q2, the second terminal is the gate of the second NMOS field effect transistor Q2, and the third terminal is the drain of the second NMOS field effect transistor Q2. Similarly, the third switching element 103 may be embodied as a PMOS fet Q3, wherein the first terminal of the third switching element 103 is the source of the PMOS fet Q3, the second terminal is the gate of the PMOS fet Q3, and the third terminal is the drain of the PMOS fet Q3.

As shown in the drawing, the power switching circuit 100 further includes a first resistor R60, a second resistor R61, a third resistor R62, and a fourth resistor R63. One end of the first resistor R60 is electrically connected to a power source VCC, and the other end is electrically connected to the drain of the first NMOS FET Q1. One end of the second resistor R61 is electrically connected with the drain electrode of the first NMOS field effect transistor Q1, and the other end is electrically connected with the switch key SW-PB.

One end of the third resistor R62 is electrically connected with the drain electrode of the second NMOS field-effect transistor Q2, and the other end is electrically connected with the source electrode of the PMOS field-effect transistor Q3; one end of the fourth resistor R63 is electrically connected to the gate of the first NMOS FET Q1, and the other end is electrically connected to the resistor R62 and the gate of the PMOS FET Q3.

As further shown in the figure, the power switch circuit 100 further includes a capacitor C32, one end of which is grounded, and the other end of which is electrically connected to the second resistor R61 and one end of the switch button SW-PB, wherein the capacitor C32 performs charging and discharging operations through the first resistor R60 and the second resistor R61, so as to control the on/off of the first NMOS fet Q1.

In one embodiment, as shown in the figure, the drain of the first NMOS fet Q1 is electrically connected to the second resistor R61 and the power source VCC through the first resistor R60, respectively; the grid electrode of the first NMOS field-effect transistor Q1 is electrically connected with the drain electrode of the second NMOS field-effect transistor Q2 and the grid electrode of the PMOS field-effect transistor Q3 through a second resistor R62 and a third resistor R63 respectively; the source of the first NMOS field effect transistor Q1 is grounded.

In another embodiment, the gate of the second NMOS fet Q2 is electrically connected to the drain of the first NMOS fet Q1; the drain electrode of the second NMOS field-effect transistor Q2 is respectively electrically connected with the grid electrode of the PMOS field-effect transistor Q3, the power supply VCC through a third resistor R62 and the grid electrode of the first NMOS field-effect transistor Q1 through a fourth resistor R63; the source of the second NMOS field effect transistor Q2 is grounded. The grid electrode of the PMOS field effect transistor Q3 is electrically connected with the drain electrode of the second NMOS field effect transistor Q2; the source electrode of the PMOS field effect transistor Q3 is electrically connected with a power supply VCC; the drain of the PMOS field effect transistor Q3 is the power output end V of the power switch circuit 100_out。

The operation of the power switching circuit 100 will be described in detail with reference to fig. 2.

As shown in fig. 2, power switch circuit 100 is in an initial state, in which the voltage of capacitor C32 is zero, and switch button SW-PB is in a pop-up state. The power source VCC is pressurized to the gate of the first NMOS FET Q1 (hereinafter referred to as "Q1") through the third resistor R62 and the fourth resistor R63, and V is connected to ground at this time since the source of Q1 is grounded_gs> turn-on voltage (V)_gsThe gate-source voltage of the fet) so that Q1 is turned on. Since the drain of Q1 is electrically connected to the gate of a second NMOS field effect transistor Q2 (hereinafter referred to as "Q2"), the gate voltage of Q2 is pulled low to zero, and the source of Q2 is grounded, so that V of Q2 is set to zero_gs0, less than the turn-on voltage of Q2, turning off Q2. At this time, the voltage of the power source VCC is applied across the gate and source of the PMOS fet Q3 (hereinafter, abbreviated as "Q3"), and thus V of Q3_gs0, less than the turn-on voltage of Q3, resulting in Q3 turning off. V of Q3 at this time_d＝0(V_dIs the drain voltage of the fet) and, therefore, the power supply output terminal V_outAnd closing.

When power is supplied to other external devices, the switch button SW-PB can be pressed and released. At this time, the switch circuit is in the initial state, and the zero voltage of the capacitor C32 is transmitted to the gate of Q1 through the switch key at the instant when the switch key is pressed to turn on the circuit. V of Q1 at this time since the source of Q1 is grounded_gs0, less than its turn-on voltage, so Q1 transitions from on to off.

Due to the turn-off of Q1, on the one hand, the power supply VCC starts to charge the capacitive element C32 through the first resistor R60 and the second resistor R61 until the voltage on C32 is greater than the turn-on voltage of Q1; on the other hand, the power VCC applies a voltage to the gate of Q2 through the first resistor R60, and since the source of Q2 is grounded, V of Q2 is applied_gsTurn on voltage, turning Q2 from off to on.

The turn-on of Q2 causes the gate voltage of Q3, which is electrically connected to its drain, to be zero, while the source of Q3 is connected to the supply VCC, resulting in V of Q3_gsTurn-on voltage, then Q3 transitions from off to on, at which time V of Q3_d＝V_s(V_sSource voltage of fet), and final power supply output terminal V_outTransitioning from off to on. At this time, the power switching circuit 100 is connected to the power supply output terminal V_outThe external device of (2) supplies power.

When it is not necessary to connect to the power supply output terminal V_outWhen the external device is powered on, the switch key SW-PB is pressed again and released, and the high voltage of the capacitor element C32 is transferred to the gate of the Q1 at the moment when the switch key is pressed to turn on the circuit. V of Q1 at this time since the source of Q1 is grounded_gsTurn on voltage, so Q1 transitions from off to on. Since the drain of Q1 is electrically connected to the gate of Q2, the gate voltage of Q2 is pulled low to zero. At this time, the source of Q2 is grounded, so V of Q2_gsAt 0, this voltage is less than the turn-on voltage of Q2 so that Q2 changes from on to off.

Meanwhile, the voltage of the power supply VCC is loaded on both the gate and the source of the Q3End, then V of Q3_gsAt 0, this voltage is less than the turn-on voltage of Q3, causing Q3 to transition from on to off, thus V of Q3_d0, the drain of Q3 is the power supply output terminal V_outAnd finally the power supply output end V_outTurning from on to off, the power switching circuit 100 stops connecting to the power output terminal V_outThe external equipment supplies power. Meanwhile, since Q1 is turned on, the capacitive element C32 performs a discharging operation along the closed loop formed by the second resistors R61, Q1 and C32 until the voltage thereon is zero, so as to wait for the next key operation.

In one embodiment, the switch buttons SW-PB of the present invention are self-resetting switches. For the self-resetting switch, the circuit is in a connection state only when the key is pressed, and the circuit forms a loop at the moment; when the button is released, the circuit is immediately opened.

Optionally, the power VCC of the present invention may be an internal voltage source or an external power source. When external power is used, corresponding interfaces (e.g., pins 1 and 4 in Head4 shown in fig. 2) need to be reserved in the power switching circuit 100.

It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, description, and drawings of the present invention are used for distinguishing between different objects and not for describing a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the invention. As used in the specification and claims of this application, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of the present invention refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Although the embodiments of the present invention are described above, the descriptions are only examples for facilitating understanding of the present invention, and are not intended to limit the scope and application scenarios of the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A power switch circuit (100) comprising a power supply (VCC) and a switch button (SW-PB), characterized in that the power switch circuit (100) further comprises a first switch element (101), a second switch element (102), a third switch element (103) and a power output terminal (V-PB)_out)；

A first end of the first switch element (101) is electrically connected with the power supply (VCC) and a second end of the second switch element (102), a second end of the first switch element (101) is electrically connected with the switch key (SW-PB), and a third end of the first switch element (101) is grounded;

a first end of the second switching element (102) is grounded, and a third end of the second switching element (102) is electrically connected with a second end of the third switching element (103);

a first end of the third switching element (103) is electrically connected to the power supply (VCC), andthe third end of the third switching element (103) is the power output end (V)_out)；

Wherein, when the switch button (SW-PB) is pressed and released in an initial state where the power supply (VCC) is turned on, the first switching element (101) is controlled to be turned off to turn on the second switching element (102) electrically connected thereto, the turn-on of the second switching element (102) turns on the third switching element (103) electrically connected thereto, and the turn-on of the third switching element (103) turns on the power supply output terminal (V-PB)_out) The air conditioner is opened and then is opened,

at the power supply output terminal (V)_out) When the switch key (SW-PB) is pressed and released in the opened state, the first switch element (101) is controlled to be on, so that the second switch element (102) electrically connected with the first switch element is disconnected, the third switch element (103) electrically connected with the second switch element is disconnected by the disconnection of the second switch element (102), and the power output end (V) is disconnected by the disconnection of the third switch element (103)_out) And closing.

2. The power switching circuit (100) of claim 1, wherein the first switching element (101) is a first NMOS field effect transistor (Q1), wherein the first terminal of the first switching element (101) is a drain of the first NMOS field effect transistor (Q1), the second terminal is a gate of the first NMOS field effect transistor (Q1), and the third terminal is a source of the first NMOS field effect transistor (Q1);

the second switch element (102) is a second NMOS field effect transistor (Q2), wherein a first terminal of the second switch element (102) is a source electrode of the second NMOS field effect transistor (Q2), a second terminal is a gate electrode of the second NMOS field effect transistor (Q2), and a third terminal is a drain electrode of the second NMOS field effect transistor (Q2);

the third switching element (103) is a PMOS field effect transistor (Q3), wherein the first end of the third switching element (103) is the source of the PMOS field effect transistor (Q3), the second end is the gate of the PMOS field effect transistor (Q3), and the third end is the drain of the PMOS field effect transistor (Q3);

the power switching circuit (100) further includes a first resistor (R60), a second resistor (R61), a third resistor (R62), and a fourth resistor (R63), wherein,

one end of the first resistor (R60) is electrically connected with the power supply (VCC), and the other end is electrically connected with the drain electrode of the first NMOS field effect transistor (Q1);

one end of the second resistor (R61) is electrically connected with the drain electrode of the first NMOS field effect transistor (Q1), and the other end of the second resistor (R61) is electrically connected with the switch key (SW-PB);

one end of the third resistor (R62) is electrically connected with the drain electrode of the second NMOS field-effect transistor (Q2), and the other end of the third resistor (R62) is electrically connected with the source electrode of the PMOS field-effect transistor (Q3); and

one end of the fourth resistor (R63) is electrically connected with the grid electrode of the first NMOS field effect transistor (Q1), and the other end is electrically connected with the resistor (R62) and the grid electrode of the PMOS field effect transistor (Q3).

3. The power switch circuit (100) of claim 2, wherein the power switch circuit (100) further comprises a capacitive element (C32), one end of which is grounded and the other end of which is electrically connected to the second resistor (R61) and one end of the switch button (SW-PB), and the capacitive element (C32) performs charging and discharging operations through the first resistor (R60) and the second resistor (R61) to control the on/off of the first NMOS fet (Q1).

4. The power switching circuit (100) of claim 3, wherein the drain of the first NMOS field effect transistor (Q1) is electrically connected to a second resistor (R61) and to a power supply (VCC) through the first resistor (R60), respectively, the gate of the first NMOS field effect transistor (Q1) is electrically connected to the drain of the second NMOS field effect transistor (Q2) and to the gate of the PMOS field effect transistor (Q3) through the third resistor (R62) and the fourth resistor (R63), respectively, and the source of the first NMOS field effect transistor (Q1) is grounded.

5. The power switching circuit (100) of claim 4, wherein the gate of the second NMOS field effect transistor (Q2) is electrically connected to the drain of the first NMOS field effect transistor (Q1), the drain of the second NMOS field effect transistor (Q2) is electrically connected to the gate of the PMOS field effect transistor (Q3) and to the power supply (VCC) through the third resistor (R62) and to the gate of the first NMOS field effect transistor (Q1) through the fourth resistor (R63), respectively, and the source of the second NMOS field effect transistor (Q2) is grounded.

6. The power switching circuit (100) of claim 5, wherein the gate of the PMOS FET (Q3) is electrically connected to the drain of the second NMOS FET (Q2), the source of the PMOS FET (Q3) is electrically connected to the power supply (VCC), and the drain of the PMOS FET (Q3) is the power output (V) of the power switching circuit (100)_out)。

7. The power switching circuit (100) of claim 6, wherein in an initial state of turning on the power supply (VCC), the voltage of the capacitive element (C32) is zero, the power supply (VCC) is pressurized to the gate of the first NMOS FET (Q1) through the third resistor (R62) and the fourth resistor (R63) to turn on, thereby pulling down the gate voltage of the second NMOS FET (Q2) such that the second NMOS FET (Q2) is turned off, thereby causing the PMOS FET (Q3) electrically connected thereto to be turned off, and the turning off of the PMOS FET (Q3) causes the power output (V) to be turned off_out) And closing.

8. The power switch circuit (100) of claim 7, wherein when the switch button (SW-PB) is pressed and released in an initial state of turning on the power supply (VCC), a zero voltage of the capacitive element (C32) is transferred to the gate of the first NMOS FET (Q1) to turn it from on to off, and simultaneously the capacitive element (C32) starts to charge through the first resistor (R60) and the second resistor (R61) until its voltage is greater than the turn-on voltage of the first NMOS FET (Q1), and the power supply (VCC) is added through the first resistor (R60) and the power supply (VCC)Pressing on the gate of the second NMOS FET (Q2) to turn the second NMOS FET (Q2) from OFF to ON, thereby pulling down the gate voltage of the PMOS FET (Q3) electrically connected thereto, causing the PMOS FET (Q3) to turn from OFF to ON, and turning on the PMOS FET (Q3) to turn the power output terminal (V)_out) Transitioning from off to on.

9. The power switching circuit (100) of claim 8 wherein said power supply output terminal (V) is connected to a power supply voltage (V)_out) When the switch button (SW-PB) is pressed and released in the opened state, the high voltage of the capacitor element (C32) is transmitted to the grid electrode of the first NMOS field effect transistor (Q1) to change the grid electrode from off to on, and then the grid electrode voltage of the second NMOS field effect transistor (Q2) is pulled down to change the second NMOS field effect transistor (Q2) from on to off, so that the PMOS field effect transistor (Q3) electrically connected with the PMOS field effect transistor is changed from on to off, and the off of the PMOS field effect transistor (Q3) causes the power supply output end (V) to be switched to the off state_out) The state changes from on to off.

10. The power switch circuit (100) of any of claims 1-9, wherein the switch button (SW-PB) is a self-healing switch.

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