CN211089595U

CN211089595U - Bias protection circuit and TR (transmitter-receiver) assembly of power amplifier

Info

Publication number: CN211089595U
Application number: CN202020135877.2U
Authority: CN
Inventors: 李赛; 刘张胜; 寸怀诚
Original assignee: Hunan Eastone Washon Technology Co ltd
Current assignee: Zhejiang Yitong Huasheng Technology Co ltd
Priority date: 2020-01-21
Filing date: 2020-01-21
Publication date: 2020-07-24
Anticipated expiration: 2030-01-21

Abstract

The utility model discloses a power amplifier's bias protection circuit and TR subassembly, bias protection circuit passes through control module and provides control logic (0/3.3V's TT L signal) for grid switch module, switching on and cutting off of NMOS among the control grid switch module, thereby control power amplifier's ending and switching on, grid switch module's output signal is regarded as drain switch module's input signal again, switching on and cutting off of PMOS and NMOS among the control drain switch module, thereby whether normal power supply work of control power amplifier's drain electrode, with the protection of realization to power amplifier, the too big quiescent current has been avoided damaging GaN/GaAs power amplifier.

Description

Bias protection circuit and TR (transmitter-receiver) assembly of power amplifier

Technical Field

The utility model belongs to the technical field of the radar, especially, relate to a power amplifier's bias protection circuit and TR subassembly.

Background

The radar generally works in a half-duplex time-sharing mode, namely, a period of time in one period is a transmitting time, and a period of time is a receiving time. The TR module is widely used in active phased array radars as a transceiver module, and is mainly used to amplify a transmission signal, amplify a reception signal, and control the amplitude and phase of a radio frequency signal, and thus, the TR module of the radar operates based on a pulse period.

With the increase of application frequency and the increase of output power, wide bandgap pinch-off type high-power amplifiers such as GaN/GaAs and the like are more and more appeared in a TR component. The GaN/GaAs power amplifier supplies power to the grid electrode and the drain electrode, the GaN/GaAs power amplifier has the obvious characteristics that the grid electrode voltage is negative voltage, the drain electrode voltage is positive voltage, the grid electrode negative voltage-VGG is started firstly, when the grid electrode negative voltage-VGG exceeds a certain threshold, the drain electrode voltage VDD is added, the power amplifier has static current and can normally work, if the power supply for the grid electrode negative voltage-VGG fails, the output is 0, the static current of the power amplifier can far exceed the normal value, and the power amplifier is easy to burn. Therefore, it is very important to design a circuit applied to a GaN/GaAs power amplifier, which has a power-on sequence protection function for a high-power rf switch operating voltage.

The GaN/GaAs power amplifier can also have different bias working states: class a, class B, class AB, class C, etc., which are mainly different in bias current, i.e., the static bias current needs to be adjusted; in addition, after the static bias current is set, the static current may change with temperature change, device aging and the like, and may need to be adjusted. Designing additional circuitry to adjust the quiescent current not only increases design complexity and cost, but also consumes a significant amount of time in the adjustment.

SUMMERY OF THE UTILITY MODEL

Not enough to prior art, the utility model provides a power amplifier's biasing protection circuit and TR subassembly avoids quiescent current too big damage that causes gaN GaAs power amplifier, realizes quiescent current's automatic adjustment.

The utility model discloses a solve above-mentioned technical problem through following technical scheme: a bias protection circuit for a power amplifier, comprising: the device comprises a drain switch module, a grid switch module, a current detection module, a voltage adjustment module and a control module;

the voltage adjusting module is respectively connected with the control module and the grid switch module; the current detection module is respectively connected with the control module and the drain switch module; the grid switch module is connected with the drain switch module; the control module is also connected with the grid switch module and the drain switch module respectively;

the output end of the drain switch module is connected with the drain of the power amplifier, and the output end of the grid switch module is connected with the grid of the power amplifier.

The utility model discloses power amplifier's bias protection circuit, provide control logic (0/3.3V's TT L signal) for grid switch module through control module, switching on and cutting off of NMOS among the control grid switch module, thereby control power amplifier's cutting off and switching on, grid switch module's output signal is as drain switch module's input signal again, PMOS and NMOS's switching on and cutting off in the control drain switch module, thereby whether control power amplifier's drain electrode normally supplies power work, in order to realize power amplifier's protection, avoided too big quiescent current to damage gaN/GaAs power amplifier, this bias protection circuit directly gets grid switch module's output signal as drain switch's condition, can provide more direct protection.

Further, the gate switch module comprises a level conversion circuit, a first NMOS and an operational amplifier; the input end of the level conversion circuit is connected with the output end of the control module, the output end of the level conversion circuit is connected with the grid electrode of the first NMOS, the source electrode of the first NMOS is connected with a-5V power supply, the drain electrode of the first NMOS is connected with the output end of the voltage adjusting module through a resistor R8, the drain electrode of the first NMOS is further connected with the positive input end of the operational amplifier, the negative input end of the operational amplifier is connected with the output end of the operational amplifier through a resistor R17, and the output end of the operational amplifier is further connected with the input end of the drain switch module.

The output end of the operational amplifier is connected with the grid electrode of the power amplifier, a control logic (TT L signal of 0/3.3V) provided by the control module outputs 0V/-5V after level conversion and an inverter circuit, when the input voltage is 0V, the first NMOS is conducted, the output of the grid switch module is-5V, at this time, the power amplifier is turned off no matter whether the drain voltage of the power amplifier is high level, when the input voltage is 3.3V, the first NMOS is turned off, the output of the grid switch module is the output voltage of the voltage adjusting module, and if the drain voltage of the power amplifier is high level, the power amplifier is turned on.

Furthermore, the source of the first NMOS is also connected to the output terminal of the level shift circuit through a resistor R9, so as to prevent the first NMOS from being triggered by mistake during power-up.

Further, the drain switch module comprises a comparator, an and gate, an isolation gate driver, a first CMOS inverter, a second CMOS inverter, a PMOS, and a second NMOS; the positive input end and the negative input end of the comparator are respectively connected with a +5V power supply through a resistor R6 and a resistor R4, the positive input end of the comparator is also grounded through a resistor R7, and the negative input end of the comparator is also connected with the output end of the grid switch module through a resistor R5; the output end of the comparator is connected with one input end of the AND gate, and the other input end of the AND gate is connected with the output end of the control module; the output end of the AND gate is respectively connected with an INA pin and an INB pin of the isolation gate driver, a VDDA pin of the isolation gate driver is respectively connected with a power supply end of the first CMOS phase inverter and an input end of the current detection module, an OUTA pin of the isolation gate driver is connected with an input end of the first CMOS phase inverter, a VSSA pin of the isolation gate driver is connected with a grounding end of the first CMOS phase inverter, and the VSSA pin of the isolation gate driver is also respectively connected with a VSP power supply and the VDDA pin of the isolation gate driver through a resistor R10 and a parallel circuit consisting of a voltage regulator tube D2 and a capacitor C1; the VDDB pin of the isolation grid driver is respectively connected with the power supply end and the VDN power supply of the second CMOS inverter, the OUTB pin of the isolation grid driver is connected with the input end of the second CMOS inverter, and the VSSB pin of the isolation grid driver and the grounding end of the second CMOS inverter are both grounded; the output end of the first CMOS inverter is connected with the grid electrode of the PMOS through a parallel circuit formed by a resistor R13 and a resistor R14, the source electrode of the PMOS is connected with the input end of the current detection module, and the drain electrode of the PMOS is connected with the drain electrode of the second NMOS; the grid electrode of the second NMOS is connected with the output end of the second CMOS inverter through a parallel circuit formed by a resistor R15 and a resistor R16, and the source electrode of the second NMOS is grounded; the gate of the second NMOS is also connected to the drain of the power amplifier through a resistor R11, and the gate of the second NMOS is also connected to ground through a resistor R12.

Further, the input end of the and gate connected with the output end of the control module is also grounded through a resistor R3 to prevent the and gate from being triggered by mistake.

Further, the negative input terminal of the comparator is also connected to ground through a diode D1.

Further, the current detection module is a current detection circuit mainly comprising a current detection amplifier with the model number of AD8418, the AD8418 is a high-voltage and high-resolution current detection amplifier, the initial gain is set to be 20V/V, and the maximum gain error in the whole temperature range is+0.15%, its buffered output voltage can be directly connected to any typical converter, while AD8418 has excellent input common mode rejection performance, enabling bidirectional current measurement on the sampling resistor.

Further, the voltage adjusting module is a voltage adjusting circuit mainly based on a digital potentiometer with the model number AD5263, and the AD5263 is a four-channel 256-bit digital potentiometer with an optional digital interface, which can realize the same electronic adjusting function as a mechanical potentiometer or a variable resistor and has enhanced resolution, solid state reliability and excellent low temperature coefficient performance.

Further, the control module is a control circuit which is mainly an FPGA with the model number of XC6S L X16-2CPG 196I.

The utility model provides a TR subassembly, include like the embodiment of the utility model provides an arbitrary power amplifier's bias protection circuit.

Advantageous effects

Compared with the prior art, the utility model provides a pair of power amplifier's bias protection circuit, provide control logic (0/3.3V's TT L signal) through control module for grid switch module, control switching on and off of NMOS among the grid switch module, thereby control power amplifier's cutting off and switching on, grid switch module's output signal is as drain switch module's input signal again, control switching on and cutting off of PMOS and NMOS among the drain switch module, thereby whether control power amplifier's drain electrode normally supplies power and works, in order to realize the protection to power amplifier, avoided too big quiescent current to damage GaN/GaAs power amplifier, this bias protection circuit directly gets grid switch module's output signal as drain switch's condition, can provide more direct protection.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only one embodiment of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a block diagram of a bias protection circuit of a power amplifier according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a power module according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of a gate switch module according to an embodiment of the present invention;

fig. 4 is a schematic circuit diagram of a drain switch module according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a current detection module according to an embodiment of the present invention;

fig. 6 is a schematic diagram of a digital potentiometer according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a control module according to an embodiment of the present invention.

Detailed Description

The technical solution of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

As shown in fig. 1, the present invention provides a bias protection circuit for a power amplifier, including: the device comprises a drain switch module, a grid switch module, a current detection module, a voltage adjustment module and a control module; the voltage adjusting module is respectively connected with the control module and the grid switch module; the current detection module is respectively connected with the control module and the drain switch module; the grid switch module is connected with the drain switch module; the control module is also connected with the grid switch module and the drain switch module respectively; the output end of the drain switch module is connected with the drain of the power amplifier, and the output end of the grid switch module is connected with the grid of the power amplifier.

The utility model discloses power amplifier's bias protection circuit, provide 0/3.3V's TT L signal for grid switch module through control module, switching on and cutting off of NMOS in the control grid switch module, thereby control power amplifier's cutting off and switching on, grid switch module's output signal is as drain switch module's input signal again, PMOS and NMOS's switching on and cutting off in the control drain switch module, thereby whether control power amplifier's drain electrode normally supplies power work, in order to realize the protection to power amplifier, avoided too big quiescent current to damage GaN/GaAs power amplifier, this bias protection circuit directly gets grid switch module's output signal as drain switch's condition, can provide more direct protection.

In this embodiment, a VSP power supply, a VDN power supply, a-5V power supply, a +3.3V power supply, and the like are used as inputs of the bias protection circuit, and these power supplies may be taken from a TR component circuit board (VDN is generally 10V, VSP is generally VDSS-10V), or may be obtained through another power supply module (as shown in fig. 1 and fig. 2).

As shown in fig. 1 and 2, the bias protection circuit further includes a power module, the power module includes a first power circuit and a second power circuit, the first power circuit and the second power circuit are respectively composed of two different types of DC/DC conversion chips, an input terminal of the first power circuit is connected to VDD, an output terminal of the first power circuit outputs VSP, VDN, and FPGA-P, and the VSP, VDN, and FPGA-P respectively provide required power for a VSSA pin, a VDDB pin, and FPGA of the isolated gate driver; the input end of the second power supply circuit is connected with a +5V power supply, and the output ends of the second power supply circuit output-5V, FPGA-5V, -3.3V, -5V, FPGA-5V and 3.3V respectively provide required power supplies for the source electrode of the first NMOS, the digital potentiometer and the FPGA. The input VDD and +5V of the first power supply circuit and the second power supply circuit may be provided by a power supply in a system (e.g. a radar system) to which the bias protection circuit is applied, or may be converted into the required VDD and +5V by another power supply circuit, and it is a prior art to obtain the required VDD and +5V by the power supply circuit.

As shown in fig. 3, the gate switch module includes a level shift circuit, a first NMOS (Q3), and an operational amplifier; the input end of the level conversion circuit is connected with the output end of the control module, the output end of the level conversion circuit is connected with the grid electrode of the first NMOS, the source electrode of the first NMOS is connected with a-5V power supply, the drain electrode of the first NMOS is connected with the output end (VG) of the digital potentiometer through a resistor R8, the drain electrode of the first NMOS is further connected with the positive input end of the operational amplifier, the negative input end of the operational amplifier is connected with the output end of the operational amplifier through a resistor R17, and the output end of the operational amplifier is further connected with the negative input end of the comparator through a resistor R5. In order to prevent the first NMOS (Q3) from being triggered by mistake during power-up, the source of the first NMOS is also connected to the output terminal of the level shift circuit through a pull-down resistor R9.

The output end of the operational amplifier is connected with the grid of the power amplifier, the control logic (TT L signal of 0/3.3V) provided by the FPGA outputs 0V/-5V after passing through a level conversion and inversion circuit, when TT L-G is 0V, the first NMOS is conducted, the output VG _ PA of the operational amplifier is-5V, at the moment, the power amplifier is turned off no matter whether the drain voltage of the power amplifier is high level, when the input is 3.3V, the first NMOS is turned off, the output VG _ PA of the operational amplifier is the output voltage VG of a digital potentiometer, if the drain voltage of the power amplifier is high level (for example, 48V), the power amplifier is conducted, the output VG _ PA of the operational amplifier is used as an input signal of the negative input end of a comparator, the PMOS (Q1) and the second NMOS (Q2) are controlled to be conducted and cut off, the drain of the power amplifier is controlled to normally supply power to work, so as to realize the protection of the power amplifier, in order to increase the grid driving current of the first NMOS, the speed of the switch is increased, the first NMOS is connected to the drain of the power amplifier, the first NMOS is connected to the operational amplifier, the operational amplifier is connected to the drain of the MOS 774, the amplifier, the operational amplifier is connected to the CMOS transistor, the CMOS transistor is connected to the low-resistance circuit, the CMOS transistor is connected to the CMOS transistor, the CMOS.

As shown IN FIG. 4, the drain switch module comprises a comparator, an AND gate, an isolation gate driver, a first CMOS inverter, a second CMOS inverter, a PMOS and a second NMOS, wherein a positive input end and a negative input end of the comparator are respectively connected with +5V through a resistor R6 and a resistor R4, a positive input end of the comparator is further grounded through a resistor R7, a negative input end of the comparator is further connected with an output end VG _ PA of the operational amplifier through a resistor R5, an output end of the comparator is connected with one input end of the AND gate, the other input end of the AND gate is connected with an output end TT L-D of the FPGA, an output end of the AND gate is respectively connected with an INA pin and an INB pin of the isolation gate driver, a VDDA pin of the isolation gate driver is respectively connected with a power supply terminal of the first CMOS inverter and an input terminal-IN (VDD _ SW) of the current detection module, a pin of the isolation gate driver is connected with an input end of the first CMOS inverter, a VSSA pin of the isolation gate driver is connected with a ground terminal of the first CMOS inverter, a drain switch module is further connected with a drain terminal VSSA pin of the PMOS through a resistor R10, a resistor R2, a drain resistor R638, a drain resistor R468, a drain resistor Q resistor R is connected with a drain resistor W, a drain resistor W is connected with an output terminal of the PMOS transistor Q resistor W, a drain resistor W is connected with an output terminal of the drain resistor W-D resistor W-SW resistor W-D, a drain resistor W-D resistor W-D resistor W-D resistor W-D resistor W-D resistor W.

The first CMOS inverter is composed of a PMOS (Q4) and an NMOS (Q5), the gates of Q4 and Q5 are connected to form the input end of the first CMOS inverter, the source of Q4 is the power supply end of the first CMOS inverter, the source of Q5 is the grounding end of the first CMOS inverter, and the drains of Q4 and Q5 are connected to form the output end of the first CMOS inverter. The second CMOS inverter is composed of a PMOS (Q6) and an NMOS (Q7), the gates of Q6 and Q7 are connected to form the input end of the second CMOS inverter, the source of Q6 is the power supply end of the second CMOS inverter, the source of Q7 is the grounding end of the second CMOS inverter, and the drains of Q6 and Q7 are connected to form the output end of the second CMOS inverter.

In this embodiment, the isolated gate driver is of a model of UCC21225A, the isolated gate driver has a function of UV L O, and when the input power supply VCCI is abnormally powered down, the isolated gate driver forces OUTA and OUTB to be pulled to respective low levels, at this time, due to the presence of two pairs of CMOS inverters Q4 and Q5, Q6 and Q7, Q1 is turned off, Q2 conducts the drain of the power amplifier and discharges to 0V, thereby protecting the power amplifier, the input and output of the isolated gate driver are isolated, the input level is TT L signal, the high and low levels of the output are the supply voltages VDDA/VSSA and VDDB/VSSB of the two isolated outputs OUTA/OUTB, and since the maximum allowed source voltage of a general power MOS transistor does not exceed 20V, for example, and the voltage values of the input gate driver and vddvdd _ SW are connected, and have +48V, a suitable supply voltage is required to the VSSA, in this embodiment, VSP is +38V, and the external power supply n of vsb is 10V, and VSSB is grounded.

The comparator is model ADCMP608, which is a fast comparator manufactured using the proprietary XFCB2 process of ADI corporation, which has an extremely rich variety of functional characteristics and is easy to use. The model of the AND gate is 74AHC1G08 DBV.

The negative input end of the comparator is grounded through a diode D1, a diode D1 is used for protecting the comparator, because the input level of the comparator is not allowed to be lower than-0.5V for example, if a +5V power supply is abnormal and is 0V for example, when the level of the negative input end of the D1 conduction limiting comparator is higher than-0.5V, +5V power supply is divided by resistors R6 and R7 and then input into the positive input end of the comparator, the +5V power supply and VG _ PA are divided by resistors R4 and R5 and input into the negative input end of the comparator, the input end of an AND gate connected with the FPGA output end TT L-D is grounded through a resistor R3 to prevent the AND gate from being triggered by mistake, a voltage regulator D2 in the drain switch module is used for protecting the Q1, when the VSP is 0V due to abnormal conditions, the low level of the OUTA output of the isolated gate driver is 0V, and the turn-on voltage V of the Q1 is enabled_GSBurning when the temperature exceeds the maximum limit value; however, if D2 exists, when VSP is floating, the low level output by OUTA is the voltage value such as VDD _ SW, and Q1 cannot be turned on; if VSP is shorted to ground, V of Q1 is reduced_GSOnly the regulated voltage value of D2, R10 partial voltage or blow, reach and protect other circuit components and partsThe purpose of (1). Purpose of resistors R11 and R12: when the power amplifier is abnormally powered off and the isolated gate driver or a logic circuit in front of the power amplifier cannot work normally, and the charge of the drain (VDD _ PA) of the power amplifier is not discharged, the voltage is divided by the resistors R11 and R12 to enable the Q2 to keep a conducting state, so that the charge can be discharged quickly, and the power amplifier is protected.

When the absolute value of VG _ PA is not less than the lower limit of the absolute value of the gate voltage, the comparator outputs a high level, if TT L-D is high, the AND gate outputs a high level, the isolation gate driver drives Q1 to be turned on, Q2 to be turned off, and the drain of the power amplifier normally works, otherwise, TT L-D is low, Q1 is turned off, Q2 is turned on, and the drain of the power amplifier is turned off and does not work, when the absolute value of VG _ PA is less than the lower limit of the absolute value of the gate voltage, the comparator outputs a low level, and when the input of TT L-D is high or low, the output of the AND gate is low, Q1 is turned off, Q2 is turned on, the drain of the power amplifier is turned off, the purpose of protecting the power amplifier is achieved, when VDD is abnormally powered off, VDD is powered down before-5V, the gate voltage is immediately turned off as long as VG _ PA is lower than the lower limit of the absolute value of the gate voltage, Q1 is immediately turned off, the lower limit of the absolute value of the gate voltage is set according to the recommended lower limit of the absolute value of the power amplifier, and the absolute value of the power amplifier is set according to the instruction of the power amplifier, such as 0.7.

The bias protection circuit can selectively control the drain or the grid to switch the switch or simultaneously switch the grid and the drain according to the characteristics of the power amplifier, so that the purpose of protecting the power amplifier is achieved.

As shown in FIG. 5, the current detection module is a current detection circuit mainly composed of a current detection amplifier with model number AD8418, the AD8418 is a high-voltage and high-resolution current detection amplifier, the initial gain is set to be 20V/V, and the maximum gain error in the whole temperature range is+0.15%, its buffered output voltage can be directly connected to any typical converter, while the AD8418 has a voltage outputThe input common mode rejection performance of the color can be measured on the sampling resistor through bidirectional current. An IN pin of the AD8418 is connected with a VDD power supply, and an-IN pin of the AD8418 is respectively connected with a source electrode of Q4 and a source electrode of Q1 and used for detecting drain quiescent current; the OUT pin of the AD8418 is directly connected with an ADC port of the FPGA, the FPGA carries OUT AD conversion on a signal detected by the AD8418 to obtain static current, the static current is compared with a set value, if the static current is different from the set value, the effective resistance value of the voltage adjusting module is adjusted, the adjustment of the input voltage VG of the grid switch module is realized, and therefore the automatic adjustment of the static current is realized.

The current detection module and the FPGA realize the static current detection program, which is the prior art, can refer to an invention patent with an authorization publication number of CN106712642B and named as an alternating current servo control system; the program for adjusting the output voltage of the voltage adjustment module by adjusting the voltage adjustment module (the digital potentiometer in this embodiment) through the control module (the FPGA in this embodiment) is the prior art, and can refer to the utility model patent with the authorization publication number of CN209496269U, which is named as a programmable constant current source circuit suitable for laser driving self-adaptation, and can also refer to the invention patent with the authorization publication number of CN106569249B, which is named as an automatic adjusting method for the reverse bias voltage of the satellite-borne Si-APD detector. The current detection module, the control module and the control program of the digital potentiometer are the prior art, and reference is also made to an invention patent with an authorization publication number of CN106569053B and named as a simulation system and method for external characteristics of a vehicle-mounted battery of a pure electric vehicle.

As shown in fig. 6, the voltage adjusting module is a voltage adjusting circuit mainly based on a digital potentiometer with model number AD5263, and AD5263 is a four-channel, 256-bit digital potentiometer with an optional digital interface, which can realize the same electronic adjusting function as a mechanical potentiometer or a variable resistor, and has enhanced resolution, solid-state reliability and excellent low temperature coefficient performance. A pin-through resistor R1 of the AD5263 is connected with a-5V power supply, a pin-through resistor R2 of the AD5263 is grounded, a pin W is connected with the drain electrode of a first NMOS (Q3) through a resistor R8, the AD5263 is also connected with the FPGA through an I2C/SPI, the effective resistor of the AD5263 is adjusted by the FPGA, and the output voltage VG of the AD5263 is adjusted, so that the automatic adjustment of drain quiescent current is realized.

As shown in FIG. 7, the control module is a control circuit mainly based on an FPGA of model XC6S L X16-2CPG196I, and the XC6S L X16 series FPGA has higher efficiency and lower power consumption.

The above disclosure is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or modifications within the technical scope of the present invention, and all should be covered by the scope of the present invention.

Claims

1. A bias protection circuit for a power amplifier, comprising: the device comprises a drain switch module, a grid switch module, a current detection module, a voltage adjustment module and a control module;

2. The bias protection circuit of claim 1, wherein the gate switch module comprises a level shifter, a first NMOS, and an operational amplifier; the input end of the level conversion circuit is connected with the output end of the control module, the output end of the level conversion circuit is connected with the grid electrode of the first NMOS, the source electrode of the first NMOS is connected with a-5V power supply, the drain electrode of the first NMOS is connected with the output end of the voltage adjusting module through a resistor R8, the drain electrode of the first NMOS is further connected with the positive input end of the operational amplifier, the negative input end of the operational amplifier is connected with the output end of the operational amplifier through a resistor R17, and the output end of the operational amplifier is further connected with the input end of the drain switch module.

3. The bias protection circuit of claim 2, wherein the source of the first NMOS is further connected to the output of the level shifter through a resistor R9.

4. The bias protection circuit of any one of claims 1-3, wherein the drain switch module comprises a comparator, an AND gate, an isolated gate driver, a first CMOS inverter, a second CMOS inverter, a PMOS, and a second NMOS; the positive input end and the negative input end of the comparator are respectively connected with a +5V power supply through a resistor R6 and a resistor R4, the positive input end of the comparator is also grounded through a resistor R7, and the negative input end of the comparator is also connected with the output end of the grid switch module through a resistor R5; the output end of the comparator is connected with one input end of the AND gate, and the other input end of the AND gate is connected with the output end of the control module; the output end of the AND gate is respectively connected with an INA pin and an INB pin of the isolation gate driver, a VDDA pin of the isolation gate driver is respectively connected with a power supply end of the first CMOS phase inverter and an input end of the current detection module, an OUTA pin of the isolation gate driver is connected with an input end of the first CMOS phase inverter, a VSSA pin of the isolation gate driver is connected with a grounding end of the first CMOS phase inverter, and the VSSA pin of the isolation gate driver is also respectively connected with a VSP power supply and the VDDA pin of the isolation gate driver through a resistor R10 and a parallel circuit consisting of a voltage regulator tube D2 and a capacitor C1; the VDDB pin of the isolation grid driver is respectively connected with the power supply end and the VDN power supply of the second CMOS inverter, the OUTB pin of the isolation grid driver is connected with the input end of the second CMOS inverter, and the VSSB pin of the isolation grid driver and the grounding end of the second CMOS inverter are both grounded; the output end of the first CMOS inverter is connected with the grid electrode of the PMOS through a parallel circuit formed by a resistor R13 and a resistor R14, the source electrode of the PMOS is connected with the input end of the current detection module, and the drain electrode of the PMOS is connected with the drain electrode of the second NMOS; the grid electrode of the second NMOS is connected with the output end of the second CMOS inverter through a parallel circuit formed by a resistor R15 and a resistor R16, and the source electrode of the second NMOS is grounded; the gate of the second NMOS is also connected to the drain of the power amplifier through a resistor R11, and the gate of the second NMOS is also connected to ground through a resistor R12.

5. The bias protection circuit of claim 4, wherein the input of the AND gate connected to the output of the control module is further connected to ground through a resistor R3.

6. The bias protection circuit for a power amplifier as claimed in claim 4, wherein the negative input terminal of said comparator is further connected to ground through a diode D1.

7. The bias protection circuit of the power amplifier as claimed in any one of claims 1-3, wherein the current detection module is a current detection circuit based on a current detection amplifier model AD 8418.

8. A bias protection circuit for a power amplifier as claimed in any one of claims 1 to 3, wherein said voltage regulation module is a voltage regulation circuit based on a digital potentiometer of type AD 5263.

9. The bias protection circuit of a power amplifier as claimed in any one of claims 1-3, wherein the control module is a FPGA-based control circuit of model XC6S L X16-2CPG 196I.

10. A TR assembly, comprising: a bias protection circuit comprising a power amplifier as claimed in any one of claims 1 to 9.