CN211014537U - Operational amplifier test circuit and system - Google Patents
Operational amplifier test circuit and system Download PDFInfo
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- CN211014537U CN211014537U CN201921329854.9U CN201921329854U CN211014537U CN 211014537 U CN211014537 U CN 211014537U CN 201921329854 U CN201921329854 U CN 201921329854U CN 211014537 U CN211014537 U CN 211014537U
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Abstract
The utility model relates to a test circuit and system are put to fortune. The operational amplifier test circuit comprises a first voltage current source, a second voltage current source, a first input unit, a second input unit and an operational amplifier to be tested. The first voltage current source and the second voltage current source respectively provide a pulse edge voltage signal and a common mode/differential mode voltage to a signal source node P, the first input unit outputs the common mode/differential mode voltage or a low level voltage signal to a negative input end of the operational amplifier to be tested, and the second input unit outputs the program-controlled jump voltage or the low level voltage signal to a positive input end of the operational amplifier to be tested, wherein the program-controlled jump voltage is formed by combining the common mode/differential mode voltage and the pulse edge voltage signal, so that the second voltage current source is multiplexed in the testing process, the number of voltage and current sources of the operational amplifier testing circuit is reduced, and the testing cost is further reduced.
Description
Technical Field
The utility model relates to a semiconductor integrated circuit tests technical field, especially relates to a test circuit and system are put to fortune.
Background
At present, before an operational amplifier is put into an application process of an integrated circuit, multi-parameter testing needs to be carried out on the operational amplifier generally, and in the process of testing each parameter, a testing circuit needs to be provided, so that a plurality of testing circuits are needed, the testing circuit needs to be replaced frequently by the operational amplifier, the testing personnel is troublesome, and meanwhile, the operational amplifier can be damaged due to frequent replacement of the testing circuit of the operational amplifier, and the testing efficiency is low.
In order to improve the testing efficiency, in the mass production test of the operational amplifier, the test of all electrical parameters of the operational amplifier needs to be completed by means of an auxiliary operational amplifier loop and a certain number of voltage current sources, but the increase of the number of the voltage current sources leads to the increase of the testing cost.
SUMMERY OF THE UTILITY MODEL
Therefore, it is necessary to provide an operational amplifier test circuit and system for solving the problem of a large number of voltage current sources in the operational amplifier test circuit.
The utility model provides a test circuit is put to fortune, include:
a first voltage current source; providing a pulse edge voltage signal to a signal source node;
a second voltage current source providing a common mode/differential mode voltage to the signal source node;
a first input unit, a first input end of which is electrically connected to the signal source node, a second input end of which is grounded, and an output end of which is electrically connected to a negative input end of the operational amplifier to be tested, and is configured to receive the common mode/differential mode voltage and the low level voltage signal and output the common mode/differential mode voltage or the low level voltage signal; and
a second input unit, a first input end of which is electrically connected to the signal source node, and a second input end and a third input end of which are both grounded, and configured to receive the common mode/differential mode voltage, the low-level voltage signal, and a program-controlled transition voltage formed by combining the common mode/differential mode voltage and the pulse edge voltage signal, and output the common mode/differential mode voltage, the program-controlled transition voltage, or the low-level voltage signal; and
the positive input end of the operational amplifier to be tested is electrically connected with the output end of the second input unit, the negative input end of the operational amplifier to be tested is electrically connected with the output end of the first input unit, the output end of the operational amplifier to be tested is electrically connected with a third voltage current source, and the third voltage current source is used for obtaining a test result according to a voltage signal output by the operational amplifier to be tested after receiving the common mode/differential mode voltage, the program control jump voltage or the low level voltage signal.
In one embodiment, the first voltage current source comprises:
the direct current signal source is used for providing direct current voltage;
the pulse generation branch circuit, the control end and the time sequence signal input end electricity of pulse generation branch circuit are connected, the pulse generation direct current power input end with direct current signal source electricity is connected, the pulse generation branch circuit the output with the first input electricity of signal modulation circuit is connected, receives direct current voltage with time sequence signal to and when the pressure slew rate is surveyed to needs, according to direct current voltage with time sequence signal generates pulse edge voltage, and provide the signal source node.
In one embodiment, the pulse generation branch comprises a clock driving chip.
In one embodiment, the first input unit includes:
a first fixed contact of the first switch is electrically connected with the signal source node, and a second fixed contact of the second switch is grounded;
a first resistor, a first end of the first resistor being electrically connected to the blade of the first switch; and
and the first end of the second resistor is electrically connected with the second end of the first resistor, and the second end of the second resistor is electrically connected with the negative input end of the operational amplifier to be tested.
In one embodiment, the second input unit includes:
a first fixed contact of the second switch is electrically connected with the signal source node, and a second fixed contact of the second switch is grounded;
a first end of the third resistor is electrically connected with the blade of the second switch; and
and the first end of the fourth resistor is electrically connected with the second end of the third resistor, and the second end of the fourth resistor is electrically connected with the positive input end of the operational amplifier to be tested.
In one embodiment, when the first switch and the second switch are connected to the signal source node, the second voltage current source provides the common mode/differential mode voltage for the operational amplifier to be tested.
In one embodiment, the first input unit further comprises a third switch connected in parallel to two ends of the second resistor for changing the resistance of the first input unit;
the second input unit further comprises a fourth switch, and the fourth switch is connected in parallel to two ends of the fourth resistor and used for changing the resistance of the second input unit.
In one embodiment, the op-amp test circuit further includes:
the positive input end of the auxiliary operational amplifier is electrically connected with the output end of the operational amplifier to be tested, the negative input end of the auxiliary operational amplifier is electrically connected with the fourth voltage current source, the output end of the auxiliary operational amplifier is electrically connected with the fifth voltage current source, and the output signal of the auxiliary operational amplifier is tested through the fifth voltage current source to obtain a test signal;
a fifth switch, wherein the first end of the second switch is electrically connected with the output end of the operational amplifier to be tested;
a fifth resistor, a first end of which is electrically connected to the second end of the second switch, and a second end of which is electrically connected to the positive input end of the auxiliary operational amplifier; and
and a first end of the sixth resistor is electrically connected with a second end of the fifth resistor and the positive input end of the auxiliary operational amplifier, and a second end of the sixth resistor is grounded.
In one embodiment, the op-amp test circuit further includes: and a first input end of the feedback unit is electrically connected with the output end of the operational amplifier to be tested, a second input end of the feedback unit is electrically connected with the output end of the auxiliary operational amplifier, and the output end of the feedback unit is electrically connected with the negative input end of the operational amplifier to be tested.
In one embodiment, the feedback unit includes:
a sixth switch, a first end of the sixth switch being electrically connected to the output end of the auxiliary operational amplifier;
a first end of the seventh switch is electrically connected with the output end of the operational amplifier to be tested;
a first end of the seventh resistor is electrically connected with the second end of the first resistor and the first end of the second resistor, and a second end of the seventh resistor is electrically connected with the second end of the sixth switch and the second end of the seventh switch; and
and the first capacitor is connected in parallel with two ends of the seventh resistor.
In one embodiment, the output end of the operational amplifier to be tested is connected with at least one load, and an eighth switch is arranged between the load and the output end of the operational amplifier to be tested.
In one embodiment, a ninth switch is arranged in series between the third power supply and the output end of the operational amplifier to be tested;
a tenth switch is arranged between the fifth voltage current source and the output end of the auxiliary operational amplifier.
Based on the same inventive concept, the utility model also provides an operational amplifier test system, operational amplifier test system includes a plurality of operational amplifier test circuit as described in any one of the above embodiments.
To sum up, the utility model provides a test circuit and system are put to fortune. The utility model discloses in, utilize test circuit is put to fortune can accomplish the test of all electrical parameters of operational amplifier that await measuring, and through multiplexing second voltage current source, constitutes the pulse of common mode/differential mode voltage and first voltage current source output along voltage signal and generates programme-controlled jump voltage, and the quantity of test circuit voltage current source is put to reducible fortune, reduction test cost.
Drawings
Fig. 1 is a schematic diagram of a circuit structure for testing an operational amplifier according to an embodiment of the present invention;
fig. 2 is an electrical schematic diagram of a first voltage current source according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an equivalent test circuit of the common mode voltage rejection ratio provided by the present invention;
fig. 4 is a schematic diagram of an equivalent test circuit of the rising edge slew rate provided by the present invention;
fig. 5 is a schematic diagram of an equivalent test circuit of the falling edge slew rate provided by the present invention;
fig. 6 is a schematic diagram of an equivalent test circuit of the current flowing into the operational amplifier to be tested according to the present invention;
fig. 7 is a schematic circuit structure diagram of a dual operational amplifier test system according to an embodiment of the present invention;
fig. 8 is a schematic circuit structure diagram of a four-operational amplifier testing system according to an embodiment of the present invention.
Detailed Description
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention can be embodied in many different forms other than those specifically described herein, and it will be apparent to those skilled in the art that similar modifications can be made without departing from the spirit and scope of the invention, and it is therefore not to be limited to the specific embodiments disclosed below.
Referring to fig. 1, an embodiment of the present invention provides an operational amplifier test circuit, which includes a first voltage current source VI _1, a second voltage current source VI _2, a first input unit 100, a second input unit 200, and an operational amplifier DUT to be tested.
The first voltage current source VI _1 provides a pulse edge voltage signal to a signal source node P;
the second voltage current source VI _2 provides a common mode/differential mode voltage to the signal source node P;
a first input end of the first input unit 100 is electrically connected to the signal source node P, a second input end of the first input unit 100 is grounded, and an output end of the first input unit 100 is electrically connected to a negative input end of the operational amplifier under test DUT, and is configured to receive the common mode/differential mode voltage and the low level voltage signal and output the common mode/differential mode voltage or the low level voltage signal.
The first input end of the second input unit 200 is electrically connected to the signal source node P, and the second input end and the third input end of the second input unit 200 are both grounded, and are configured to receive the common mode/differential mode voltage, the low-level voltage signal, and a program-controlled transition voltage formed after the common mode/differential mode voltage and the pulse edge voltage signal are combined, and output the common mode/differential mode voltage, the program-controlled transition voltage, or the low-level voltage signal.
The positive input end of the operational amplifier to be tested DUT is electrically connected to the output end of the second input unit 200, the negative input end of the operational amplifier to be tested DUT is electrically connected to the output end of the first input unit 100, the output end of the operational amplifier to be tested DUT is electrically connected to a third voltage current source VI _3, and the third voltage current source VI _3 is utilized to obtain a test result for a voltage signal output by the operational amplifier to be tested DUT after receiving the common mode/differential mode voltage, the program control jump voltage, or the low level voltage signal.
In this embodiment, the operational amplifier test circuit is utilized to complete the test of all electrical parameters of the operational amplifier DUT to be tested, and the common mode/differential mode voltage and the pulse edge voltage signal output by the first voltage current source VI _1 are combined to generate the program-controlled jump voltage by multiplexing the second voltage current source VI _2, so that the number of voltage and current sources of the operational amplifier test circuit can be reduced, and the test cost can be reduced.
In one embodiment, the first voltage current source VI _1 includes a dc signal source 310 and a pulse generating branch 320.
The dc signal source 310 is configured to provide a dc voltage.
The control end of the pulse generation branch 320 is electrically connected with the time sequence signal input end, the power input end of the pulse generation direct current is electrically connected with the direct current signal source 310, the output end of the pulse generation branch 320 is electrically connected with the first input end of the signal modulation circuit, receives the direct current voltage and the time sequence signal, and when the pressure testing slew rate needs to be tested, the direct current voltage and the time sequence signal are generated to be the pulse edge voltage and provided to the signal source node P.
In one embodiment, the pulse generation branch 320 includes a clock driver chip.
Referring to fig. 2, the clock driving chip is a chip of model E L7156, the dc signal source 310 is connected to the high level pin of the chip E L7156, the low level pin of the chip E L7156 is grounded, the power pin "VS +" of the chip E L7156 is connected to 15V, the power pin "VS-" of the chip E L7156 is grounded, and the input pin of the chip E L7156 is connected to the timing signal, after the chip E L7156 is enabled, the output pin of the chip E L7156 is connected to the high level pin or the low level pin according to the state of the timing input pin, thereby generating a pulse edge signal.
In one embodiment, the first input unit 100 includes a first switch K1, a first resistor R1, and a second resistor R2.
A first fixed contact of the first switch K1 is electrically connected to the signal source node P, and a second fixed contact of the second switch K2 is grounded.
A first end of the first resistor R1 is electrically connected with the blade of the first switch K1.
The first end of the second resistor R2 is electrically connected with the second end of the first resistor R1, and the second end of the second resistor R2 is electrically connected with the negative input end of the operational amplifier DUT to be tested.
In this embodiment, the second resistor R2 is an adjustable resistor, and is used to change the resistance of the negative input terminal of the operational amplifier DUT to be tested.
In one embodiment, the second input unit 200 includes a second switch K2, a third resistor R3, and a fourth resistor R4.
A first fixed contact of the second switch K2 is electrically connected to the signal source node P, and a second fixed contact of the second switch K2 is grounded.
The first end of the third resistor R3 is electrically connected with the blade of the second switch K2.
The first end of the fourth resistor R4 is electrically connected with the second end of the third resistor R3, and the second end of the fourth resistor R4 is electrically connected with the positive input end of the operational amplifier DUT to be tested.
In this embodiment, the resistances of the first resistor R1 and the third resistor R3 are equal, and the fourth resistor R4 is an adjustable resistor, and is used to change the resistance of the positive input terminal of the operational amplifier DUT to be tested.
In one embodiment, when the first switch K1 and the second switch K2 are connected to the signal source node P, the second voltage current source VI _2 provides the common mode/differential mode voltage for the operational amplifier DUT to be tested.
In one embodiment, the first input unit 100 further includes a third switch K3, the third switch K3 is connected in parallel across the second resistor R2 for changing the resistance of the first input unit 100; the second input unit 200 further comprises a fourth switch connected in parallel across the fourth resistor R4 for changing the resistance of the second input unit 200. In this embodiment, the offset current test can be realized by controlling the third switch K3 and the fourth switch.
In one embodiment, the operational amplifier test circuit further includes an auxiliary operational amplifier AMP, a fifth switch K5, a fifth resistor R5, and a sixth resistor R6.
The positive input end of the auxiliary operational amplifier AMP is electrically connected with the output end of the operational amplifier to be tested DUT, the negative input end of the auxiliary operational amplifier AMP is electrically connected with a fourth voltage current source VI _4, the output end of the auxiliary operational amplifier AMP is electrically connected with a fifth voltage current source VI _5, and the output signal of the auxiliary operational amplifier AMP is tested through the fifth voltage current source VI _5 to obtain a test signal.
The first end of the second switch K2 is electrically connected with the output end of the operational amplifier DUT to be tested.
A first terminal of the fifth resistor R5 is electrically connected to the second terminal of the second switch K2, and a second terminal of the fifth resistor R5 is electrically connected to the positive input terminal of the auxiliary operational amplifier AMP.
A first end of the sixth resistor R6 is electrically connected to the second end of the fifth resistor R5 and the positive input terminal of the auxiliary operational amplifier AMP, and a second end of the sixth resistor R6 is grounded.
In this embodiment, the auxiliary operational amplifier AMP, the fifth switch K5, the fifth resistor R5, and the sixth resistor R6 form an auxiliary operational amplifier loop, and each parameter of the operational amplifier DUT to be tested is determined by combining the output signal of the auxiliary operational amplifier AMP and the output signal of the operational amplifier DUT to be tested.
In one embodiment, the operational amplifier test circuit further includes a feedback unit 400, a first input terminal of the feedback unit 400 is electrically connected to the output terminal of the operational amplifier under test DUT, a second input terminal of the feedback unit 400 is electrically connected to the output terminal of the auxiliary operational amplifier AMP, and an output terminal of the feedback unit 400 is electrically connected to the negative input terminal of the operational amplifier under test DUT.
In one embodiment, the feedback unit 400 includes a sixth switch K6, a seventh resistor R7, and a first capacitor C:
a first terminal of the sixth switch K6 is electrically connected to the output terminal of the auxiliary operational amplifier AMP.
And the first end of the seventh switch is electrically connected with the output end of the operational amplifier to be tested DUT.
A first end of the seventh resistor R7 is electrically connected to the second end of the first resistor R1 and the first end of the second resistor R2, and a second end of the seventh resistor R7 is electrically connected to the second end of the sixth switch K6 and the second end of the seventh switch.
The first capacitor C is connected in parallel to two ends of the seventh resistor R7.
In one embodiment, at least one load is connected to the output end of the operational amplifier under test DUT, and the load RLAnd an eighth switch K8 is arranged between the output end of the operational amplifier DUT to be tested, and a driving voltage is provided for the load through an eighth voltage current source VI _ 8.
In one embodiment, a ninth switch K9 is arranged in series between the third power supply and the output end of the operational amplifier under test DUT;
a tenth switch K10 is disposed between the fifth voltage current source VI _5 and the output terminal of the auxiliary operational amplifier AMP.
In addition, the operational amplifier test circuit further comprises a sixth voltage current source VI _6 and a seventh voltage current source VI _7 for supplying power to the operational amplifier DUT to be tested, and an eighth voltage current source for supplying power to the load. That is, the present embodiment can complete the test of all the electrical parameters of the operational amplifier only by using 8 voltage current sources, and when the operational amplifier test circuit is used for testing, the operational amplifier test circuit not only has the advantages of easy operation, high efficiency and the like, but also can reduce the test cost.
In order to better explain the present solution, in the following embodiments, a plurality of specific test circuits are specifically listed, and the connection relationship between the above devices and the connection function are described in detail.
Example one
Referring to fig. 3, the present embodiment mainly performs the detection of the common mode rejection ratio of the operational amplifier under test DUT, i.e. the ratio of the differential mode voltage gain to the common mode voltage gain of the operational amplifier under test DUT within the specified range of the power supply voltage and the output voltage. In this embodiment, the first resistor and the third resistor are RIResistance value of the fifth resistor 3RREFThe resistance value of the sixth resistor is RREFThe sixth switch K6 and the tenth switch K10 are closed, introducing feedback to the output of the auxiliary operational amplifier AMP; simultaneously, the third switch K3 and the fourth switch are closed. And simultaneously changing the voltages of the sixth voltage current source VI _6 and the seventh voltage current source VI _7, so that the input end of the operational amplifier DUT to be tested is equivalent to obtain a common-mode voltage Vi. If the voltage of the output end of the operational amplifier DUT to be tested can be adjusted to the set value by setting the voltage of the fourth voltage current source VI _4, the output voltage Vm0 of the output end of the auxiliary operational amplifier AMP is tested by the fifth voltage current source VI _ 5. Then, the voltages of the sixth voltage current source VI _6 and the seventh voltage current source VI _7 are adjusted and changed to obtain the equivalent common-mode voltage Vi of the input end of the new operational amplifier DUT to be tested’And repeating the step of setting the voltage of the fourth voltage current source VI _4 to make the voltage at the output end of the operational amplifier DUT to be tested be a set value, and then testing the output voltage Vm1 at the output end of the auxiliary operational amplifier AMP by the fifth voltage current source VI _ 5. The common-mode rejection ratio CMRR is obtained as (Vi' -Vi)/((Vm 1-Vm 0)/(RF/RI)), where the unit of CMRR is V/V.
Example two
Referring to fig. 4, the present embodiment mainly detects the rising edge slew rate Sr + of the operational amplifier DUT to be tested, i.e. the maximum change rate of the rising edge of the output voltage with time when the input terminal applies the specified large-signal step pulse voltage. In this embodiment, the seventh switch and the ninth switch K9 are closed, and the output end of the operational amplifier DUT to be tested is fed back; meanwhile, the blade of the first switch K1 is grounded, and the second switch K2 is electrically connected with the voltage current source node and receives the program-controlled jump voltage. At this time, the rising edge amplitude change Δ V1 and the corresponding change time Δ t1 of the output voltage of the output end of the operational amplifier DUT to be tested are detected, and the rising edge slew rate Sr + ═ Δ V1/Δ t1 is obtained according to the calculation formula.
EXAMPLE III
Referring to fig. 5, the present embodiment mainly detects the falling edge slew rate Sr-of the operational amplifier DUT to be tested, i.e. the maximum change rate of the falling edge of the output voltage with time when the input terminal applies the specified large-signal step pulse voltage. In this embodiment, the seventh switch and the ninth switch K9 are closed, and the output end of the operational amplifier DUT to be tested is fed back; meanwhile, the blade of the first switch K1 is grounded, and the second switch K2 is electrically connected with the voltage current source node and receives the program-controlled jump voltage. At this time, the amplitude change Δ V2 of the falling edge of the output voltage of the output end of the operational amplifier DUT to be tested and the corresponding change time Δ t2 are detected, and the falling edge slew rate Sr + ═ Δ V2/Δ t2 is obtained according to the calculation formula.
Example four
Referring to fig. 6, the embodiment mainly tests the current flowing into the power source terminal of the operational amplifier under test DUT. In this embodiment, the first switch K1 and the second switch K2 are grounded, and the third switch K3 and the fourth switch are closed, so as to input a common-mode voltage to the operational amplifier DUT to be tested. The sixth switch K6 IS closed, the output terminal of the auxiliary operational amplifier AMP IS brought into feedback to the negative input terminal of the operational amplifier DUT to be tested, the prescribed power supply voltages V + and V "are applied to the operational amplifier DUT to be tested by the sixth voltage current source VI _6 and the seventh voltage current source VI _7, and the current flowing into the positive power supply terminal of the operational amplifier DUT to be tested IS + detected by the sixth voltage current source VI _6 and IS detected by the seventh voltage current source VI _7 as IS + and IS detected by the seventh voltage current source VI _7 as IS-.
Based on the same inventive concept, the embodiment of the utility model provides a fortune is put test system still provides, fortune is put test system and is put test circuit including a plurality of fortune in any above-mentioned embodiment. Referring to fig. 7 and 8, fig. 7 shows a dual op-amp test system, and fig. 8 shows a four op-amp test system. As can be seen from fig. 7 and 8, each test circuit shares one set of voltage current source, and after the test is started, the sixth voltage current source VI _6 and the seventh voltage current source VI _7 supply power to each operational amplifier DUT to be tested, which is beneficial to saving the start time of each operational amplifier DUT to be tested and improving the test efficiency compared with a single operational amplifier test circuit.
To sum up, the utility model discloses in, utilize test circuit is put to fortune can accomplish the test of all electrical parameters of operational amplifier DUT that await measuring, and through multiplexing second voltage current source VI _2, with the pulse of common mode/differential mode voltage and first voltage current source VI _1 output along voltage signal generation programme-controlled jump voltage, for the operational amplifier DUT that awaits measuring provides the required pulse of test slew rate parameter along the level, reduced the quantity of test circuit voltage current source is put to fortune, reduce test cost.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (13)
1. An operational amplifier test circuit, comprising:
a first voltage current source; providing a pulse edge voltage signal to a signal source node;
a second voltage current source providing a common mode/differential mode voltage to the signal source node;
a first input unit, a first input end of which is electrically connected to the signal source node, and a second input end of which is grounded, and is configured to receive the common mode/differential mode voltage and the low level voltage signal and output the common mode/differential mode voltage or the low level voltage signal; and
a second input unit, a first input end of which is electrically connected to the signal source node, and a second input end and a third input end of which are both grounded, and configured to receive the common mode/differential mode voltage, the low-level voltage signal, and a program-controlled transition voltage formed by combining the common mode/differential mode voltage and the pulse edge voltage signal, and output the common mode/differential mode voltage, the program-controlled transition voltage, or the low-level voltage signal; and
the positive input end of the operational amplifier to be tested is electrically connected with the output end of the second input unit, the negative input end of the operational amplifier to be tested is electrically connected with the output end of the first input unit, the output end of the operational amplifier to be tested is electrically connected with a third voltage current source, and the third voltage current source is used for obtaining a test result according to a voltage signal output by the operational amplifier to be tested after receiving the common mode/differential mode voltage, the program control jump voltage or the low level voltage signal.
2. The op-amp test circuit of claim 1, wherein the first voltage current source comprises:
the direct current signal source is used for providing direct current voltage;
the pulse generation branch circuit is characterized in that a control end of the pulse generation branch circuit is electrically connected with a time sequence signal input end, a power supply input end of pulse generation direct current is electrically connected with the direct current signal source, receives the direct current voltage and the time sequence signal, and when the pressure test slew rate needs to be tested, the pulse generation branch circuit generates the pulse edge voltage according to the direct current voltage and the time sequence signal and provides the pulse edge voltage for the signal source node.
3. The op-amp test circuit of claim 2, wherein the pulse generation branch comprises a clock driver chip.
4. The op-amp test circuit of claim 1, wherein the first input cell comprises:
a first fixed contact of the first switch is electrically connected with the signal source node, and a second fixed contact of the first switch is grounded;
a first resistor, a first end of the first resistor being electrically connected to the blade of the first switch; and
and the first end of the second resistor is electrically connected with the second end of the first resistor, and the second end of the second resistor is electrically connected with the negative input end of the operational amplifier to be tested.
5. The operational amplifier test circuit as claimed in claim 4, wherein the second input unit comprises:
a first fixed contact of the second switch is electrically connected with the signal source node, and a second fixed contact of the second switch is grounded;
a first end of the third resistor is electrically connected with the blade of the second switch; and
and the first end of the fourth resistor is electrically connected with the second end of the third resistor, and the second end of the fourth resistor is electrically connected with the positive input end of the operational amplifier to be tested.
6. The operational amplifier test circuit as claimed in claim 5, wherein the second voltage current source provides the common mode/differential mode voltage for the operational amplifier under test when the first switch and the second switch are connected to the signal source node.
7. The operational amplifier test circuit as claimed in claim 5, wherein the first input unit further comprises a third switch connected in parallel across the second resistor for changing the resistance of the first input unit;
the second input unit further comprises a fourth switch, and the fourth switch is connected in parallel to two ends of the fourth resistor and used for changing the resistance of the second input unit.
8. The op-amp test circuit of claim 5, further comprising:
the positive input end of the auxiliary operational amplifier is electrically connected with the output end of the operational amplifier to be tested, the negative input end of the auxiliary operational amplifier is electrically connected with the fourth voltage current source, the output end of the auxiliary operational amplifier is electrically connected with the fifth voltage current source, and the output signal of the auxiliary operational amplifier is tested through the fifth voltage current source to obtain a test signal;
a fifth switch, wherein the first end of the second switch is electrically connected with the output end of the operational amplifier to be tested;
a fifth resistor, a first end of which is electrically connected to the second end of the second switch, and a second end of which is electrically connected to the positive input end of the auxiliary operational amplifier; and
and a first end of the sixth resistor is electrically connected with a second end of the fifth resistor and the positive input end of the auxiliary operational amplifier, and a second end of the sixth resistor is grounded.
9. The operational amplifier test circuit as claimed in claim 8, further comprising a feedback unit, wherein a first input terminal of the feedback unit is electrically connected to the output terminal of the operational amplifier under test, a second input terminal of the feedback unit is electrically connected to the output terminal of the auxiliary operational amplifier, and an output terminal of the feedback unit is electrically connected to the negative input terminal of the operational amplifier under test.
10. The op-amp test circuit of claim 9, wherein the feedback unit comprises:
a sixth switch, a first end of the sixth switch being electrically connected to the output end of the auxiliary operational amplifier;
a first end of the seventh switch is electrically connected with the output end of the operational amplifier to be tested;
a first end of the seventh resistor is electrically connected with the second end of the first resistor and the first end of the second resistor, and a second end of the seventh resistor is electrically connected with the second end of the sixth switch and the second end of the seventh switch; and
and the first capacitor is connected in parallel with two ends of the seventh resistor.
11. The operational amplifier test circuit as claimed in claim 1, wherein at least one load is connected to the output terminal of the operational amplifier under test, and an eighth switch is disposed between the load and the output terminal of the operational amplifier under test.
12. The operational amplifier test circuit as claimed in claim 8, further comprising a third power supply, wherein a ninth switch is connected in series between the third power supply and the output terminal of the operational amplifier to be tested;
a tenth switch is arranged between the fifth voltage current source and the output end of the auxiliary operational amplifier.
13. An operational amplifier test system comprising a plurality of operational amplifier test circuits according to any one of claims 1 to 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921329854.9U CN211014537U (en) | 2019-08-16 | 2019-08-16 | Operational amplifier test circuit and system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921329854.9U CN211014537U (en) | 2019-08-16 | 2019-08-16 | Operational amplifier test circuit and system |
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| CN211014537U true CN211014537U (en) | 2020-07-14 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110596568A (en) * | 2019-08-16 | 2019-12-20 | 北京华峰测控技术股份有限公司 | Operational amplifier test circuit and system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110596568A (en) * | 2019-08-16 | 2019-12-20 | 北京华峰测控技术股份有限公司 | Operational amplifier test circuit and system |
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