JP3599256B2

JP3599256B2 - Voltage applied current measurement circuit

Info

Publication number: JP3599256B2
Application number: JP4343596A
Authority: JP
Inventors: 憲治伊澤; 好弘橋本
Original assignee: Advantest Corp
Current assignee: Advantest Corp
Priority date: 1996-02-29
Filing date: 1996-02-29
Publication date: 2004-12-08
Anticipated expiration: 2016-02-29
Also published as: JPH09236637A

Description

【０００１】
【発明の属する技術分野】
この発明は例えばＣＭＯＳ型ＩＣのように能動素子が反転動作するときだけ大きな負荷電流を消費し、定常状態では微小電流しか消費しないＩＣの、特に電源電圧供給端子に定常時の電圧を与えた状態で流れる微小電流を測定する電圧印加電流測定回路に関する。
【０００２】
【従来の技術】
図５に従来から用いられている電圧印加電流測定回路の概略の構成を示す。この電圧印加電流測定回路は概略、電圧供給回路１０と電流測定手段２０とによって構成される。電圧供給回路１０は非反転入力端子に一定電圧Ｖ_ｉｎが与えられた演算増幅器１１と、この演算増幅器１１から出力される電圧Ｖ_０を出力し、この出力電圧Ｖ_０を負荷２５に供給する電圧出力端子ＴＯと、電圧出力端子ＴＯに出力される電圧Ｖ_０を演算増幅器１１の反転入力端子に負帰還させる負帰還回路１２と、演算増幅器１１の出力端子と電圧出力端子ＴＯとの間に直列に接続された電流測定用抵抗器１３と、この電流測定用抵抗器１３と並列に接続されたダイオードの逆並列回路１４と、電流測定用抵抗器１３及び逆並列接続されたダイオードとの並列接続回路に更に並列接続した位相補償コンデンサ１５と、電圧出力端子ＴＯと共通電位点に接続されたバイパスコンデンサ１６とによって構成される。
【０００３】
電流測定手段２０は電流測定用抵抗器１３に発生する電圧を取出す差動増幅器２１と、この差動増幅器２１で検出した電圧値をＡＤ変換して取出すＡＤ変換器２２とによって構成することができる。尚、演算増幅器１１の非反転入力端子に一定電圧Ｖ_ｉｎを供給する電圧源１８は一般にＤＡ変換器が用いられ、ＤＡ変換器に与えるディジタル値によって演算増幅器１１の非反転入力端子に与える電圧値Ｖ_ｉｎを任意の電圧に設定できるように構成される。
【０００４】
電圧出力端子ＴＯと共通電位間に負荷２５が接続される。負荷２５はここではＣＭＯＳ型ＩＣであるものとし、そのＣＭＯＳ型ＩＣの定常状態における消費電流値を測定する。
つまり、負荷２５がＣＭＯＳ型ＩＣである場合、ＣＭＯＳ型ＩＣ内の能動素子（ＦＥＴ）が反転動作する毎に、図６Ａに示すような動作電流ＩＰが流れ、反転動作が終了すると、電流消費量は極端に少なくなり、定常電流ΔＩが流れる。動作電流ＩＰと定常電流ΔＩとの比は例えば１０００：１程度の大きな比率を持つ。よって定常電流ΔＩを正確に測定するには動作電流ＩＰが流れた後、定常電流ΔＩに切替わった時点から充分に時間が経過し、電圧出力端子ＴＯの電圧Ｖ_０が安定した時点（以下この電圧Ｖ_０が安定するまでの時間をセットリングタイムと称す）で電流測定手段２０でＡＤ変換動作を実行すればよい。
【０００５】
負荷２５となる被試験ＩＣの動作速度が遅く、動作電流ＩＰが流れる周期が充分長ければセットリングタイムが長くても定常電流ΔＩを正確に測定することはできる。然し乍ら、ＩＣには高速化が要求されており、動作電流ＩＰが流れる周期は年々短かくなる傾向にある。従って従来より、この種の電圧印加電流測定回路ではセットリングタイムを短かくする工夫を種々施している。
【０００６】
その１つとしては電圧出力端子ＴＯにバイパスコンデンサ１６を接続し、このバイパスコンデンサ１６に常時定常電圧Ｖ_０を充電しておき、動作電流ＩＰが負荷２５に流れるとき、負荷２５に流れる動作電流ＩＰの大部分をこのバイパスコンデンサ１６から放出させ、負荷２５で必要とする動作電流ＩＰを過不足なく供給できるようにしている。
【０００７】
更に、電流測定用抵抗器１３に対してダイオードの逆並列回路１４を接続し、動作電流ＩＰが流れている最中に、電流測定用抵抗器１３に大きな電圧降下を発生させない工夫をしている。
動作電流ＩＰが流れた際に、電圧出力端子ＴＯの電圧変動を小さくするためには、バイパスコンデンサ１６の容量値を大きく設定するとよい。バイパスコンデンサ１６の容量値を大きく設定すると、演算増幅器１１から成る負帰還回路の動作が不安定（発振現象が見られる）になる。この現象を除去するために位相補償コンデンサ１５の容量値を大きく設定し、不安定現象を除去している。
【０００８】
【発明が解決しようとする課題】
ところで、位相補償コンデンサ１５の容量値を大きく採ると、電流測定用抵抗器１３の抵抗値も大きいことから、電流測定用抵抗器１３と位相補償コンデンサ１５の時定数が大きくなり、この時定数に従って電圧出力端子ＴＯの電圧が元の定常電圧に復帰するから、時定数が大きい分だけセットリングタイムが長くなり高速動作型のＩＣの定常電流を測定できないことになる。
【０００９】
以下にセットリングタイムの一例を数値を掲げて説明する。高速の負荷変動特性を得るためには演算増幅器１１を含む回路全体の周波数特性を高くすることが要求される。また、微小の定常電流ΔＩを測定するためには電流測定用抵抗器１３の抵抗値Ｒ_ｍを大きなものが必要となる。
ＣＭＯＳ型ＩＣの動作時に流れる動作電流ＩＰはその流れている時間は通常数ｎｓ〜数１０ｎｓであり、演算増幅器１１を用いた負帰還型の電圧供給回路１０では動作電流ＩＰが流れている期間内は負荷変動を補償できない。従って従来よりバイパスコンデンサ１６を設け、動作電流ＩＰが流れている期間はこのバイパスコンデンサ１６から負荷２５に電流を供給し、動作電流ＩＰの終了後、演算増幅器１１側から消費した電荷をバイパスコンデンサ１６に供給している。
【００１０】
動作電流ＩＰが流れている時間ＴＰが短かく、動作電流ＩＰが定電流であるものとすると、バイパスコンデンサ１６に蓄えられる電荷Ｑは一般にＱ＝Ｃ※Ｖ＝Ｉ※Ｔであるから、電圧出力端子ＴＯの電圧変動ΔＶ_０はΔＶ_０≒ＩＰ※ＴＰ／Ｃ_１６となり、バイパスコンデンサ１６に必要な容量値Ｃ_１６はＣ_１６≒ＩＰ※ＴＰ／ΔＶ_０となる。
【００１１】
一般的な例としてＩＰ＝５００ｍＡ，ＴＰ＝１００ｎｓ，ΔＶ_０＝２００ｍＶとすると、
Ｃ_１６≒ＩＰ※ＴＰ／ΔＶ＝５００ｍＡ※ １００ｎｓ／２００ｍＶ＝０．２５μＦ
となる。
電圧出力端子ＴＯを流れる電流が定常状態になったときの電流測定分解能を１００ｎＡ、電流測定手段２０に設けた差動増幅器２１の利得を１０倍、Ａ／Ｄ変換器２２の測定分解能を１ｍＶとすると、電流測定用抵抗器１３の抵抗値Ｒ_ｍは、
Ｒ_ｍ＝１ｍＶ／（１００ｎＡ※１０）＝１ＫΩ
となる。
【００１２】
演算増幅器１１の周波数応答特性を図７に示す。図中曲線Ａはオクターブ当り−６ｄＢの減衰特性、曲線Ｂはオクターブ当り−１２ｄＢの減衰特性を示す。図示する周波数ｆ１〜ｆ２の間はオクターブ当り−１２ｄＢの減衰特性を呈し、このオクターブ−１２ｄＢの減衰特性のまま０ｄＢに達すると周知のように系は不安定な動作となる。この周波数応答特性において、周波数ｆ１は、
ｆ１≒１／（２π※Ｒ_ｍ※Ｃ_１６）＝６３６Ｈｚ
ｆ_ｎを１００ＭＨｚとして回路を安定に動作させるための周波数ｆ２を１００ＫＨｚに採ると、この周波数ｆ２を与える位相補償コンデンサ１５の容量値Ｃ_ｍは、
ｆ２＝１／（２π※Ｒ_ｍ※Ｃ_ｍ）
から、
Ｃ_ｍ＝１／（２π※Ｒ_ｍ※ｆ２）
＝１６００ＰＦ
となる。
【００１３】
電流測定時のセットリングタイムは電流測定用抵抗器１３の抵抗値Ｒ_ｍと位相補償コンデンサ１５の容量値Ｃ_ｍの時定数で決まる。
動作電流ＩＰが流れている期間に電流測定用抵抗器１３の両端に発生する電圧はダイオードの逆並列回路１４の順方向電圧にクランプされる。動作電流ＩＰが流れている期間の電流測定用抵抗器１３に発生する電圧を７００ｍＶとすると、時定数τ＝Ｒ_ｍ※Ｃ_ｍで決まる電流測定用抵抗器１３の両端電圧が１ｍＶに回復するまでの放電時間ＴＳ（セットリングタイム）は、
ｌｏｇｅ（１ｍＶ／７００ｍＶ）＝−６．５５
から、

となる。
【００１４】
結局、図６Ｂに示した電圧出力端子ＴＯの電圧変動ΔＶ_ｏが定常値Ｖ_０＝Ｖ_ｉｎに復帰するまでに約１０．４μｓのセットリングタイムＴＳを要し、このセットリングタイムＴＳを経過した時点でなければ電流測定手段２０は電流測定しても誤差値の大きい電流値を測定してしまう不都合が生じる。セットリングタイムＴＳが１０．４μｓであるとすると、１／１０．４μｓ≒０．１×１０^６＝１００ＫＨｚとなり、動作電流ＩＰの繰返し周波数が１００ＫＨｚより低い周波数のＩＣしか定常電流ΔＩを測定することができないことになる。
【００１５】
この発明の目的は、セットリングタイムＴＳを短かくし、高速動作型のＩＣの定常電流ΔＩを正確に測定することができる電圧印加電流測定回路を提供しようとするものである。
【００１６】
【課題を解決するための手段】
この発明では非反転入力端子に一定電圧が与えられた演算増幅器及びこの演算増幅器の出力電圧が与えられ、周期的に定常時の電流より尖頭値が大きい動作電流を消費する負荷にその出力電圧を供給する電圧出力端子、この電圧出力端子の電圧を上記演算増幅器の反転入力端子に帰還する帰還回路によって構成した電圧供給回路と、この電圧供給回路を構成する演算増幅器の出力端子と電圧出力端子との間に接続した電流測定用抵抗器と、上記電圧出力端子と上記演算増幅器の反転入力端子との間を接続した帰還回路と、上記電圧出力端子と共通電位点との間に接続したバイパスコンデンサと、上記電流測定用抵抗器に並列接続したダイオードの逆並列接続回路と、上記電流測定用抵抗器に並列接続した位相補償コンデンサと、上記電流測定用抵抗器に発生する電圧を測定し、上記演算増幅器から電圧出力端子に出力される電流値を測定する電流測定手段とを具備して構成される電圧印加電流測定回路において、
電圧出力端子にこの電圧出力端子の電圧が規定値より低下したことを検出して電圧出力端子に電流を流し込む電流供給回路と、電圧供給端子の電圧が定常値より高くなったことを検出して電圧供給端子より電流を吸引する電流吸引回路とを付加した電圧印加電流測定回路を提供する。
【００１７】
この出願の請求項２では請求項１で提案した電圧印加電流測定回路において、周期的に流れる動作電流が断になった時点から所定時間経過後に電流供給回路及び電流吸引回路を電圧供給端子から切離す切替回路を付加した電圧印加電流測定回路を提供する。
この出願の請求項３では請求項１で提案した電圧印加電流測定回路において、電流供給回路は電圧供給端子に出力される定常時の電圧値よりわずかに低い電圧を出力する電圧源と、この電圧源の電圧がアノードに与えられ、カソードが電圧供給端子に接続されたダイオードと、このダイオードのアノードに電流出力端子を接続した電流源とによって構成した電圧印加電流測定回路を提供する。
【００１８】
この出願の請求項４では、請求項１で提案した電圧印加電流測定回路において、電流吸引回路は電圧出力端子の定常時の電圧よりわずかに高い電圧を出力する電圧源と、この電圧源の電圧がカソードに与えられ、アノードが電圧出力端子に接続されたダイオードと、このダイオードのカソードと電圧源との接続点に接続され、電圧供給端子の電圧が電圧源の電圧より高くなった時点でダイオードを通じて電圧供給端子から電流を吸引する電流源とによって構成した電圧印加電流測定回路を提供する。
【００１９】
【作用】
この出願の請求項１で提案した電圧印加電流測定回路によれば、負荷となる被試験ＩＣに尖頭値が大きい動作電流ＩＰが流れたために、電圧出力端子の電圧が低下方向に変動すると、その電圧の低下を負帰還ループで構成される電圧供給回路とは別に設けた電流供給回路が検出し、電圧出力端子に電流を供給する。この電流の供給により、従来は電圧供給回路だけから供給されていた電流が、この発明では電流供給回路からも供給されて補足するから、電圧出力端子の電圧変動幅を小さく抑えることができる。
【００２０】
電圧出力回路の電圧変動幅を小さくできることから、バイパスコンデンサの容量値を小さい値に設定することが可能となり、これがために電圧供給回路の電圧が定常時の電圧に復帰するまでの時間（セットリングタイム）を短かくすることができる。
この発明では更に電圧供給回路の電圧出力端子に、この電圧出力端子の電圧が上昇した場合には、その電圧の上昇を検知して電流を吸引する電流吸引回路を設けた構成を提案する。この電流吸引回路を設けたことにより、負荷に動作電流が流れ、その動作電流が断になって定常電流に戻るとき、電圧出力端子の電圧にオーバーシュートが発生したとすると、そのオーバーシュートを検出して電流を吸引する。この電流の吸引によりオーバーシュートを制限する。この電圧制限動作により電圧出力端子の電圧は早期に定常電圧に復帰し、オーバーシュートが発生してもセットリングタイムを短かくすることができる。
【００２１】
請求項２で提案した電圧印加電流測定回路によれば動作電流が断になった時点から所定の時間が経過した時点で電流供給回路及び電流吸引回路を電圧出力端子から切離す切替回路を設けた構成を提案したから、電流供給回路及び電流吸引回路を流れる電流によって電流測定値に誤差が発生しない電圧印加電流測定回路を提供することができる。
【００２２】
【発明の実施の形態】
図１にこの発明による電圧印加電流測定回路の一実施例を示す。
図１において、図５と対応する部分には同一符号を付けて示す。つまり、１０は電圧供給回路、ＴＯは電圧出力端子、２５は被試験ＩＣで構成される負荷、３０はこの発明で付加する電流供給回路、４０は電流吸引回路を示す。
【００２３】
電圧供給回路１０の構成及びその動作は図５で説明したと同じであるからここではその重複説明は省略する。この発明の特徴とする構成は、電圧出力端子ＴＯに電流供給回路３０と電流吸引回路４０も合わせて接続した点である。
電流供給回路３０は電圧出力端子ＴＯの定常状態における電圧Ｖ_０＝Ｖ_ｉｎに安定した状態の電圧によりわずかに低い電圧ＶＬを発生する電圧源３１と、この電圧源３１の電圧がアノードに印加され、カソードが電圧出力端子ＴＯに接続され、更にアノードに電流源３２の電流出力端子が接続されたダイオード３３と、このダイオード３３のアノードと電圧源３１との間に接続したダイオード３４とによって構成することができる。
【００２４】
電流吸引回路４０は定常時の電圧出力端子ＴＯの出力電圧Ｖ_０＝Ｖ_ｉｎよりわずかに高い電圧ＶＨを出力する電圧源４１と、この電圧源４１の電圧ＶＨがカソードに与えられアノードが電圧出力端子ＴＯに接続され、更にカソードに吸引電流源４２が接続されたダイオード４３と、このダイオード４３のカソードと電圧源４１との間に接続したダイオード４４とによって構成することができる。
【００２５】
電圧出力端子ＴＯの電圧がＶ_０＝Ｖ_ｉｎの状態にある定常状態では電流供給回路３０のダイオード３４と電流吸引回路４０のダイオード４４は図２ＣとＤに示すようにオンの状態に保持され、ダイオード３３と４３はオフの状態に維持される。従って電流源３２から供給される電流Ｉ１はダイオード３４と電圧源３１を通じて共通電位点ＣＯＭに流れる。また電流源４２で吸引する電流Ｉ２は共通電位点ＣＯＭから電圧源４１とダイオード４４を通じて電流源４２に吸引される。
【００２６】
この状態で負荷２５に動作電流ＩＰ（図２Ａ）が流れ、この動作電流ＩＰが流れたことにより、電圧出力端子ＴＯの電圧Ｖ_０が図２Ｂに示すように低下し、その電圧Ｖ_０が電圧源３１の電圧ＶＬより低くなるとダイオード３４はオフに制御され、代わってダイオード３３がオンになるため、電流源３２から供給される電流Ｉ１は電圧出力端子ＴＯに注入される。
【００２７】
電流供給回路３０から電圧出力端子ＴＯに電流が注入されることにより、バイパスコンデンサ１６はこの電流Ｉ１により充電され、電圧変動ΔＶ_０は電圧ＶＬ以下には低下しないようにクランプされる。この結果、電圧出力端子ＴＯの電圧変動ΔＶ_０の変動幅は電圧源３１の電圧ＶＬによって決まる小さい変動幅に抑制される。電圧変動幅が小さい値に抑制されるために、電圧出力端子ＴＯの電圧は動作電流ＩＰが断になった時点から極く短かい時間内に定常値Ｖ_０＝Ｖ_ｉｎに復帰することができる。
【００２８】
ここで電圧出力端子ＴＯの電圧変動ΔＶ_０の変動幅が小さくできることから、バイパスコンデンサ１６の容量値Ｃ_１６を小さくできる利点が得られる。バイパスコンデンサ１６の容量値Ｃ_１６は、
電流供給回路３０のスイッチング時間（動作電流ＩＰが流れる時間）を２ｎＳとすると、

となる。
【００２９】
電流測定用抵抗器１３の抵抗値Ｒ_ｍは変化がなく１ＫΩである。
バイパスコンデンサ１６の容量値Ｃ_１６が決まることにより図７に示した周波数特性の周波数ｆ１は、
ｆ１≒１／（２π※Ｒ_ｍ※Ｃ_１６）＝３１．８ｋＨｚ
ｆ_ｎを１００ＭＨｚとして回路を安定に動作させるための周波数ｆ２を１ＭＨｚとすると、位相補償コンデンサ１５の容量値Ｃ_ｍは
Ｃ_ｍ＝１／（２π※Ｒ_ｍ※ｆ２）＝１６０ＰＦ
となる。
【００３０】
このように、位相補償コンデンサ１５の容量値Ｃ_ｍが従来の約１／１０になるため、電流測定用抵抗器１３の抵抗値Ｒ_ｍと位相補償コンデンサ１５の容量値Ｃ_ｍによって決まる放電時間ＴＳ（セットリングタイム）は
ＴＳ＝６．５５τ＝６．５５※１ＫΩ※１６０ＰＦ＝１．０４μｓ
となり、セットリングタイムＴＳを１／１０に短縮することができる。
【００３１】
一方、この発明では動作電流ＩＰが断になった時点で電流供給回路３０からの電流の注入量が大きいと、電圧出力端子ＴＯの電圧が図２Ｂに実線で示すように過渡的に上昇するいわゆるオーバーシュートが発生することが考えられる。このオーバーシュートが発生し、オーバーシュートの電圧が電圧源４１の電圧ＶＨを越えると電流吸引回路４０に設けたダイオード４３がオンとなり、電圧出力端子ＴＯから電流源４２が電流Ｉ２を吸引する。この電流の吸引によってオーバーシュートの電圧は電圧源４１の電圧ＶＨにクランプされ、電圧ＶＨ以上に上昇することを抑制する。この結果、オーバーシュートの量は制限されるため、オーバーシュートが発生してもセットリングタイムを短かくすることができる。
【００３２】
図３はこの出願の請求項２で提案する切替回路５０と６０を付加した実施例を示す。図３では電圧供給回路１０を省略して示している。この実施例では負荷２５に動作電流ＩＰが流れている時点では切替回路５０と６０のダイオード５２と６２は、電圧源５１と６１が出力する正電圧Ｖ_ｓｗｐと負電圧Ｖ_ｓｗｎによってオンの状態に制御され、電流源３２と４２を電流供給回路３０と電流吸引回路４０に接続した状態に保持される。従って電流供給回路３０と電流吸引回路４０は図１で説明したと同様に電流の供給と、吸引動作を実行する。動作電流ＩＰが断になった時点から所定の時間ＴＭ（図４Ｂ参照）経過した時点で電圧源５１と６１から発生している電圧Ｖ_ｓｗｐとＶ_ｓｗｎを０（ゼロ）に戻し、ダイオード５２と６２をオフに制御する。この結果電流源３２と４２は電流供給回路３０と電流吸引回路４０から切離され、電流源３２と４２の電流が電圧出力端子ＴＯに漏れることを阻止する。よって電流源３２と４２が回路から切離された後に電流測定手段２０で電流を測定することにより、電流源３２と４２の電流の影響を受けることなく、電流を測定することができる。
【００３３】
【発明の効果】
以上説明したように、この発明によれば負帰還回路で構成される電圧供給回路１０の電流供給機能を電流供給回路３０で補足し、尖頭値の大きい動作電流ＩＰが流れても、電圧出力端子ＴＯの電圧変動量を低減させる構成としたから、電圧供給回路１０の電流供給容量を軽減させることができる。つまりバイパスコンデンサ１６の容量値Ｃ_１６を小さい値に設定することができる。バイパスコンデンサ１６の容量値Ｃ_１６を小さい値に設定することができることから、位相補償コンデンサ１５の容量値Ｃ_ｍも小さい値に設定することができ、電流測定用抵抗器１３との時定数Ｒ_ｍ※Ｃ_ｍを小さくすることができる。これによって尖頭値の大きい動作電流ＩＰが流れて直後の電圧出力端子ＴＯの電圧が定常時の電圧に復帰するまでのセットリングタイムを短かくすることができ、この結果として動作電流ＩＰの繰返し周期が高速繰返し周期でも定常時の電流ΔＩを正確に測定することができることになる。
【００３４】
また、請求項２で提案した電圧印加電流測定回路によれば電流測定時点では電流補足用の電流供給回路３０及びオーバーシュート除去用の電流吸引回路４０を構成する各電流源３１と４１を回路から切離す構成としたから、スイッチ用のダイオード３３及び４３の漏れ電流による影響を受けることがない。従って、電流供給回路３０と電流吸引回路４０を設けたことにより電流測定値の信頼性が損なわれることはない。
【００３５】
更に、電流供給回路３０及び電流吸引回路４０は動作電流ＩＰが流れている期間が終了し、定常状態での微小電流測定時ではダイオード３３及び４３がオフの状態に制御され、電圧出力端子ＴＯ側に電流を出力することがない。この結果、電流源３２，４２及び電圧源３１，４１には高速応答性のみが要求され、低ノイズ特性、高精度の出力電圧安定度は要求されないため、装置を簡単に作成することができる。
【００３６】
また、バイパスコンデンサ１６の容量値Ｃ_１６を小さい値に設定することができることから、ノイズによる不確定電流の影響を小さくすることができる。つまり、電圧供給回路１０の出力にノイズが存在すると、バイパスコンデンサ１６にノイズ電流が流れ、このノイズ電流が微小電流測定時の不確定電流となる。
因みに１００ＫＨｚで１０μＶのノイズが発生していると、ノイズ電流は、
従来、Ｃ_１６＝０．２５０μＦ
Ｚ_Ｃ＝１／（２π※ｆ※０．２５０μＦ）＝６．３Ω
ノイズ電流＝１０μＶ／６．３Ω＝１．５８μＡ
本発明、Ｃ_１６＝０．００５μＦ
Ｚ_Ｃ＝１／（２π※ｆ※０．００５μＦ）＝３１８Ω
ノイズ電流＝１０μＶ／３１８Ω＝０．０３μＡ
となり、電圧供給回路１０に要求されるノイズ特性も大幅に緩和させることができる。
【図面の簡単な説明】
【図１】この発明の一実施例を説明するための接続図。
【図２】図１の動作を説明するための波形図。
【図３】この発明の請求項２で提案する要部の回路構成を説明するための接続図。
【図４】図３の動作を説明するための波形図。
【図５】従来の技術を説明するための接続図。
【図６】図５の動作を説明するための波形図。
【図７】図５の動作を説明するための周波数特性曲線図。
【符号の説明】
１０電圧供給回路
１１演算増幅器
１２負帰還回路
１３電流測定用抵抗器
１４ダイオードの逆並列回路
１５位相補償コンデンサ
１６バイパスコンデンサ
ＴＯ電圧出力端子
１８電圧源
２０電流測定手段
２５負荷
３０電流供給回路
４０電流吸引回路
５０，６０切替回路[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an IC, such as a CMOS IC, which consumes a large load current only when an active element performs an inverting operation and consumes only a small current in a steady state, particularly a state in which a steady state voltage is applied to a power supply voltage supply terminal. The present invention relates to a voltage application current measurement circuit for measuring a minute current flowing through the circuit.
[0002]
[Prior art]
FIG. 5 shows a schematic configuration of a conventional voltage application current measurement circuit. This voltage application current measurement circuit is generally constituted by a voltage supply circuit 10 and a current measurement unit 20. An operational amplifier 11 which has a constant voltage V _in the voltage supply circuit 10 to the non-inverting input terminal is given, and outputs the voltage V ₀ which is output from the operational amplifier 11, a voltage and supplies the output voltage V ₀ to the load 25 an output terminal tO, a negative feedback circuit 12 for negative feedback to the inverting input terminal of the voltage output terminal calculates voltage V ₀ to be output to the tO amplifier 11, series between the output terminal and the voltage output terminal tO of the operational amplifier 11 , A current measuring resistor 13, an anti-parallel circuit 14 of a diode connected in parallel with the current measuring resistor 13, and a parallel connection of the current measuring resistor 13 and a diode connected in anti-parallel. The circuit comprises a phase compensation capacitor 15 connected in parallel with the circuit, and a bypass capacitor 16 connected to the voltage output terminal TO and a common potential point.
[0003]
The current measuring means 20 can be constituted by a differential amplifier 21 for extracting a voltage generated in the current measuring resistor 13 and an AD converter 22 for AD-converting and extracting a voltage value detected by the differential amplifier 21. . The voltage source 18 supplies a constant voltage V _in to the non-inverting input terminal of the operational amplifier 11 generally to the DA converter is used, the voltage value applied by the digital value applied to the DA converter to the non-inverting input terminal of the operational amplifier 11 composed of a V _in so that it can be set to any voltage.
[0004]
The load 25 is connected between the voltage output terminal TO and the common potential. Here, it is assumed that the load 25 is a CMOS IC, and a current consumption value of the CMOS IC in a steady state is measured.
That is, when the load 25 is a CMOS IC, an operating current IP as shown in FIG. 6A flows each time an active element (FET) in the CMOS IC performs an inversion operation. Becomes extremely small, and a steady current ΔI flows. The ratio between the operating current IP and the steady-state current ΔI has a large ratio of, for example, about 1000: 1. Therefore, in order to accurately measure the steady-state current ΔI, a sufficient time has elapsed since the operation current IP was switched to the steady-state current ΔI, and the time when the voltage V ₀ of the voltage output terminal TO became stable (hereinafter, this time). The time required for the voltage V ₀ to stabilize is referred to as a settling time.
[0005]
If the operating speed of the IC under test as the load 25 is slow and the cycle of the operating current IP is sufficiently long, the steady current ΔI can be accurately measured even if the settling time is long. However, ICs are required to operate at higher speeds, and the cycle at which the operating current IP flows tends to become shorter year by year. Therefore, conventionally, in this type of voltage applied current measuring circuit, various measures have been taken to shorten the settling time.
[0006]
As one of them, a bypass capacitor 16 is connected to the voltage output terminal TO, and the bypass capacitor 16 is always charged with a steady voltage V _{0. When} the operating current IP flows through the load 25, the operating current IP flowing through the load 25 is changed. Is discharged from the bypass capacitor 16 so that the operating current IP required by the load 25 can be supplied without excess or deficiency.
[0007]
Further, an anti-parallel circuit 14 of a diode is connected to the current measuring resistor 13 so that a large voltage drop does not occur in the current measuring resistor 13 while the operating current IP is flowing . .
In order to reduce the voltage fluctuation of the voltage output terminal TO when the operating current IP flows, the capacitance value of the bypass capacitor 16 may be set to be large. If the capacitance value of the bypass capacitor 16 is set large, the operation of the negative feedback circuit including the operational amplifier 11 becomes unstable (oscillation phenomenon is observed). In order to eliminate this phenomenon, the capacitance value of the phase compensation capacitor 15 is set to a large value to eliminate the unstable phenomenon.
[0008]
[Problems to be solved by the invention]
When the capacitance value of the phase compensation capacitor 15 is large, the time constant of the current measurement resistor 13 and the phase compensation capacitor 15 increases because the resistance value of the current measurement resistor 13 is large. Since the voltage at the voltage output terminal TO returns to the original steady voltage, the settling time is lengthened by the larger time constant, and the steady current of the high-speed operation type IC cannot be measured.
[0009]
An example of the settling time will be described below with numerical values. In order to obtain high-speed load fluctuation characteristics, it is necessary to improve the frequency characteristics of the entire circuit including the operational amplifier 11. Also, large is needed the resistance value R _m of the current measuring resistor 13 to measure the steady-state current ΔI of the minute.
The operating current IP flowing during the operation of the CMOS type IC normally flows for several ns to several tens of ns. In the negative feedback type voltage supply circuit 10 using the operational amplifier 11, the operating current IP Cannot compensate for load fluctuations. Therefore, a bypass capacitor 16 is conventionally provided, and a current is supplied from the bypass capacitor 16 to the load 25 during a period when the operating current IP is flowing. To supply.
[0010]
Assuming that the time TP during which the operating current IP flows is short and the operating current IP is a constant current, the charge Q stored in the bypass capacitor 16 is generally Q = C * V = I * T. The voltage fluctuation ΔV _{0 at the} terminal TO is ΔV ₀ ≒ IP * TP / C ₁₆ , and the capacitance value C ₁₆ required for the bypass capacitor ₁₆ is C ₁₆ ≒ IP * TP / ΔV ₀ .
[0011]
As a general example, if IP = 500 mA, TP = 100 ns, and ΔV ₀ = 200 mV,
C ₁₆ @ IP * TP / ΔV = 500 mA * 100 ns / 200 mV = 0.25 μF
It becomes.
The current measurement resolution when the current flowing through the voltage output terminal TO is in a steady state is 100 nA, the gain of the differential amplifier 21 provided in the current measurement means 20 is 10 times, and the measurement resolution of the A / D converter 22 is 1 mV. Then, the resistance value _{R m} of the current measuring resistor 13,
R _m = 1mV / (100nA * 10) = 1KΩ
It becomes.
[0012]
FIG. 7 shows the frequency response characteristics of the operational amplifier 11. In the figure, a curve A indicates an attenuation characteristic of -6 dB per octave, and a curve B indicates an attenuation characteristic of -12 dB per octave. Between the frequencies f1 and f2 shown in the figure, the attenuation characteristic of -12 dB per octave is exhibited, and when the attenuation characteristic reaches 0 dB with the attenuation characteristic of octave -12 dB, the system becomes unstable as is well known. In this frequency response characteristic, the frequency f1 is
f1 ≒ 1 / (2π * R _m * C ₁₆ ) = 636 Hz
Taking f _n the frequency f2 to operate stably circuit as 100MHz to 100 KHz, the capacitance value _{C m} of the phase compensation capacitor 15 to provide the frequency f2 is
f2 = 1 / (2π * R _m * C _m )
From
C _m = 1 / (2π * R _m * f2)
= 1600PF
It becomes.
[0013]
Settling time when the current measurement is determined by the time constant of the capacitance value C _m of the resistance value R _m and the phase compensation capacitor 15 of the current measuring resistor 13.
The voltage generated across the current measuring resistor 13 during the period when the operating current IP is flowing is clamped to the forward voltage of the anti-parallel circuit 14 of the diode. When the voltage generated in the current measuring resistor 13 periods operating current IP is flowing and 700 mV, the voltage across the time constant τ = R _m ※ current measuring resistor 13 determined by C _m until restored to 1mV Is the discharge time TS (settling time) of
log (1 mV / 700 mV) = − 6.55
From

It becomes.
[0014]
After all, it takes a set ring time TS of about 10.4μs on until the voltage fluctuation ΔV _o of the voltage output terminal TO shown in FIG. 6B is restored to the steady-state value _{_V} 0 ₌ _V _in, it has passed the set ring time TS If it is not the time, even if the current measurement unit 20 measures the current, there is a problem that a current value having a large error value is measured. Assuming that the settling time TS is 10.4 μs, 1 / 10.4 μs ≒ 0.1 × 10 ⁶ = 100 KHz, and only the IC having a repetition frequency of the operating current IP lower than 100 KHz measures the steady-state current ΔI. Can not do.
[0015]
SUMMARY OF THE INVENTION An object of the present invention is to provide a voltage application current measurement circuit capable of shortening the settling time TS and accurately measuring the steady-state current ΔI of a high-speed operation type IC.
[0016]
[Means for Solving the Problems]
According to the present invention, an operational amplifier in which a constant voltage is applied to a non-inverting input terminal and an output voltage of the operational amplifier are applied to a load which periodically consumes an operating current having a peak value larger than a steady state current. A voltage output circuit for supplying a voltage output terminal for supplying the voltage of the voltage output terminal to the inverting input terminal of the operational amplifier; and a voltage output terminal and a voltage output terminal of the operational amplifier included in the voltage supply circuit. A feedback circuit connected between the voltage output terminal and the inverting input terminal of the operational amplifier; and a bypass connected between the voltage output terminal and a common potential point. A capacitor, an anti-parallel connection circuit of a diode connected in parallel to the current measuring resistor, a phase compensation capacitor connected in parallel to the current measuring resistor, The voltage generated in the resistor is measured, the voltage source current measurement circuit configured to include a current measuring means for measuring a current value output from the operational amplifier to the voltage output terminal,
The voltage output terminal detects that the voltage of the voltage output terminal has fallen below a specified value, and supplies a current to the voltage output terminal, and detects that the voltage of the voltage supply terminal has become higher than the steady value. Provided is a voltage applied current measuring circuit to which a current attracting circuit for attracting a current from a voltage supply terminal is added.
[0017]
According to a second aspect of the present invention, in the voltage application current measurement circuit proposed in the first aspect, the current supply circuit and the current attraction circuit are disconnected from the voltage supply terminal after a lapse of a predetermined time from the time when the periodically flowing operating current is interrupted. Provided is a voltage application current measurement circuit to which a separation switching circuit is added.
According to a third aspect of the present invention, in the voltage application current measurement circuit proposed in the first aspect, the current supply circuit outputs a voltage slightly lower than a steady state voltage value output to the voltage supply terminal; A voltage applied current measuring circuit is provided which includes a diode having a source supplied to an anode, a cathode connected to a voltage supply terminal, and a current source having a current output terminal connected to the anode of the diode.
[0018]
According to a fourth aspect of the present invention, in the voltage application current measurement circuit proposed in the first aspect, the current suction circuit outputs a voltage slightly higher than a steady state voltage of the voltage output terminal, and a voltage of the voltage source. Is applied to the cathode, the anode is connected to the diode connected to the voltage output terminal, and the diode is connected to the connection point between the cathode of this diode and the voltage source. When the voltage of the voltage supply terminal becomes higher than the voltage of the voltage source, And a current source for drawing a current from a voltage supply terminal through the voltage supply current measuring circuit.
[0019]
[Action]
According to the voltage applied current measuring circuit proposed in claim 1 of the present application, when the operating current IP having a large peak value flows through the IC under test as a load, and the voltage of the voltage output terminal fluctuates in a decreasing direction, The decrease in the voltage is detected by a current supply circuit provided separately from a voltage supply circuit constituted by a negative feedback loop, and a current is supplied to a voltage output terminal. By supplying this current, the current that has been conventionally supplied only from the voltage supply circuit is also supplied from the current supply circuit and supplemented in the present invention, so that the voltage fluctuation width of the voltage output terminal can be reduced.
[0020]
Since the voltage fluctuation range of the voltage output circuit can be reduced, it is possible to set the capacitance value of the bypass capacitor to a small value, and as a result, the time until the voltage of the voltage supply circuit returns to the steady state voltage (settling time) Time) can be shortened.
The present invention further proposes a configuration in which, when the voltage of this voltage output terminal rises, a current attraction circuit is provided at the voltage output terminal of the voltage supply circuit to detect the rise in voltage and to attract the current. By providing this current attraction circuit, when the operating current flows to the load and the operating current is interrupted and returns to the steady current, if an overshoot occurs in the voltage of the voltage output terminal, the overshoot is detected. To draw current. The attraction of this current limits overshoot. Due to this voltage limiting operation, the voltage of the voltage output terminal returns to the steady state voltage early, and the settling time can be shortened even if an overshoot occurs.
[0021]
According to the voltage application current measurement circuit proposed in claim 2, a switching circuit is provided which disconnects the current supply circuit and the current attraction circuit from the voltage output terminal when a predetermined time has elapsed from the time when the operating current is cut off. Since the configuration has been proposed, it is possible to provide a voltage application current measurement circuit in which an error does not occur in the current measurement value due to the current flowing through the current supply circuit and the current suction circuit.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows an embodiment of a voltage applied current measuring circuit according to the present invention.
In FIG. 1, portions corresponding to those in FIG. 5 are denoted by the same reference numerals. That is, 10 is a voltage supply circuit, TO is a voltage output terminal, 25 is a load constituted by the IC under test, 30 is a current supply circuit added in the present invention, and 40 is a current suction circuit.
[0023]
The configuration and operation of the voltage supply circuit 10 are the same as those described with reference to FIG. The feature of the present invention is that the current supply circuit 30 and the current attraction circuit 40 are also connected to the voltage output terminal TO.
The current supply circuit 30 includes a voltage source 31 that generates a slightly lower voltage VL by a voltage _in a steady state at a voltage V ₀ = Vin _in a steady state of the voltage output terminal TO, and the voltage of the voltage source 31 is applied to the anode. A diode 33 having a cathode connected to the voltage output terminal TO, an anode connected to the current output terminal of the current source 32, and a diode 34 connected between the anode of the diode 33 and the voltage source 31. be able to.
[0024]
Current absorbing circuit 40 is a voltage source 41 that outputs a slightly higher voltage VH than the output voltage V _{0 =} V _in the voltage output terminal TO of the steady state, the anode voltage VH of the voltage source 41 is applied to the cathode voltage output The diode 43 is connected to the terminal TO, and further has a cathode connected to an attraction current source 42, and a diode 44 connected between the cathode of the diode 43 and the voltage source 41.
[0025]
In a steady state in which the voltage of the voltage output terminal TO is _in the state of V ₀ = V _in , the diode 34 of the current supply circuit 30 and the diode 44 of the current attraction circuit 40 are kept on as shown in FIGS.

Diodes

33 and 43 are kept off. Therefore, the current I1 supplied from the current source 32 flows to the common potential point COM through the diode 34 and the voltage source 31. The current I2 drawn by the current source 42 is drawn from the common potential point COM to the current source 42 through the voltage source 41 and the diode 44.
[0026]
In this state, the operating current IP (FIG. 2A) flows through the load 25, and as the operating current IP flows, the voltage V ₀ of the voltage output terminal TO decreases as shown in FIG. 2B, and the voltage V ₀ becomes the voltage. When the voltage becomes lower than the voltage VL of the source 31, the diode 34 is controlled to be turned off, and the diode 33 is turned on instead. Therefore, the current I1 supplied from the current source 32 is injected into the voltage output terminal TO.
[0027]
By current from the current supply circuit 30 to the voltage output terminal TO is injected, the bypass capacitor 16 is charged by the current I1, voltage variation [Delta] V ₀ is below the voltage VL is clamped so as not to decrease. As a result, the fluctuation width of the voltage fluctuation ΔV _{0 at} the voltage output terminal TO is suppressed to a small fluctuation width determined by the voltage VL of the voltage source 31. For the voltage fluctuation width is suppressed to a small value, the voltage of the voltage output terminal TO may be operating current IP returns to the steady value V _{0 =} V _in the very short a paddle time after they become cross .
[0028]
Here, since the fluctuation range of the voltage fluctuation ΔV ₀ of the voltage output terminal TO can be reduced, there is obtained an advantage that the capacitance value C ₁₆ of the bypass capacitor 16 can be reduced. The capacitance value C ₁₆ of the bypass capacitor 16 is
Assuming that the switching time of the current supply circuit 30 (the time during which the operating current IP flows) is 2 ns,

It becomes.
[0029]
The resistance value R _m of the current measuring resistor 13 is 1KΩ no change.
Frequency f1 of the frequency characteristics shown in FIG. 7 by the capacitance value C ₁₆ in the bypass capacitor 16 is determined, the
f1 ≒ 1 / (2π * R _m * C ₁₆ ) = 31.8 kHz
When the f _n and 1MHz frequency f2 to operate stably circuit as 100 MHz, the capacitance _{C m} of the phase compensation capacitor _{15 C m = 1 / (2π} ※ R m ※ f2) = 160PF
It becomes.
[0030]
As described above, since the capacitance value C _m of the phase compensation capacitor 15 is about 1/10 of the conventional value, the discharge time TS determined by the resistance value R _{m of the} current measuring resistor 13 and the capacitance value C _m of the phase compensation capacitor 15 is obtained. (Settling time) TS = 6.55τ = 6.55 * 1KΩ * 160PF = 1.04μs
And the settling time TS can be reduced to 1/10.
[0031]
On the other hand, in the present invention, when the amount of current injected from the current supply circuit 30 is large at the time when the operating current IP is cut off, the voltage at the voltage output terminal TO transitionally increases as shown by a solid line in FIG. 2B. It is possible that overshoot occurs. When this overshoot occurs and the overshoot voltage exceeds the voltage VH of the voltage source 41, the diode 43 provided in the current attraction circuit 40 is turned on, and the current source 42 attracts the current I2 from the voltage output terminal TO. The voltage of the overshoot is clamped to the voltage VH of the voltage source 41 due to the attraction of the current, and is suppressed from rising to the voltage VH or more. As a result, the amount of overshoot is limited, so that the settling time can be shortened even if overshoot occurs.
[0032]
FIG. 3 shows an embodiment to which switching circuits 50 and 60 proposed in claim 2 of this application are added. In FIG. 3, the voltage supply circuit 10 is omitted. In this embodiment, when the operating current IP flows through the load 25, the

diodes

52 and 62 of the switching circuits 50 and 60 are turned on by the positive voltage V _swp and the negative voltage V _swn output by the voltage sources 51 and 61. The

current sources

32 and 42 are controlled so as to be connected to the current supply circuit 30 and the current suction circuit 40. Accordingly, the current supply circuit 30 and the current attraction circuit 40 perform the current supply and the attraction operation as described with reference to FIG. The voltages V _swp and V _swn generated from the voltage sources 51 and 61 are returned to 0 (zero) when a predetermined time TM (see FIG. 4B) has elapsed from the time when the operating current IP is cut off, and the diode 52 62 is turned off. As a result, the

current sources

32 and 42 are disconnected from the current supply circuit 30 and the current suction circuit 40, and prevent the current of the

current sources

32 and 42 from leaking to the voltage output terminal TO. Therefore, by measuring the current with the current measuring means 20 after the

current sources

32 and 42 are disconnected from the circuit, the current can be measured without being affected by the currents of the

current sources

32 and 42.
[0033]
【The invention's effect】
As described above, according to the present invention, the current supply function of the voltage supply circuit 10 constituted by the negative feedback circuit is supplemented by the current supply circuit 30 so that the voltage output is maintained even when the operating current IP having a large peak value flows. Since the amount of voltage fluctuation at the terminal TO is reduced, the current supply capacity of the voltage supply circuit 10 can be reduced. That it is possible to set the capacitance value C ₁₆ in the bypass capacitor 16 to a small value. Since it is possible to set the capacitance value C ₁₆ in the bypass capacitor 16 to a small value, capacitance value C _m of the phase compensation capacitor 15 can also be set to a small value, the constant R _m when the current measuring resistor 13 ※ can be reduced C _m. As a result, the settling time until the voltage at the voltage output terminal TO immediately after the operation current IP having a large peak value flows and the voltage at the voltage output terminal TO returns to the steady state voltage can be shortened. As a result, the repetition of the operation current IP Even when the cycle is a high-speed repetition cycle, the steady-state current ΔI can be accurately measured.
[0034]
According to the voltage application current measurement circuit proposed in claim 2, at the time of current measurement, each of the

current sources

31 and 41 constituting the current supply circuit 30 for supplementing the current and the current suction circuit 40 for removing the overshoot are removed from the circuit. Since the switching

diodes

33 and 43 are separated from each other, the switching

diodes

33 and 43 are not affected by leakage current. Therefore, the reliability of the measured current value is not impaired by providing the current supply circuit 30 and the current attraction circuit 40.
[0035]
Further, in the current supply circuit 30 and the current attraction circuit 40, the period during which the operating current IP is flowing ends, and the

diodes

33 and 43 are controlled to be in an off state when measuring a small current in a steady state, and the voltage output terminal TO side No current is output. As a result, only high-speed response is required for the

current sources

32 and 42 and the

voltage sources

31 and 41, and low noise characteristics and high-precision output voltage stability are not required. Therefore, the device can be easily manufactured.
[0036]
Further, since it is possible to set the capacitance value C ₁₆ in the bypass capacitor 16 to a small value, it is possible to reduce the influence of the uncertainty current due to noise. That is, if noise is present in the output of the voltage supply circuit 10, a noise current flows through the bypass capacitor 16, and this noise current becomes an uncertain current when measuring a minute current.
By the way, if noise of 10 μV is generated at 100 kHz, the noise current becomes
Conventionally, C ₁₆ = 0.250 μF
Z _C = 1 / (2π * f * 0.250 μF) = 6.3Ω
Noise current = 10 μV / 6.3Ω = 1.58 μA
The present invention, C ₁₆ = 0.005 μF
Z _C = 1 / (2π * f * 0.005 μF) = 318Ω
Noise current = 10 μV / 318Ω = 0.03 μA
Thus, the noise characteristics required for the voltage supply circuit 10 can be greatly reduced.
[Brief description of the drawings]
FIG. 1 is a connection diagram for explaining an embodiment of the present invention.
FIG. 2 is a waveform chart for explaining the operation of FIG.
FIG. 3 is a connection diagram for explaining a circuit configuration of a main part proposed in claim 2 of the present invention.
FIG. 4 is a waveform chart for explaining the operation of FIG. 3;
FIG. 5 is a connection diagram for explaining a conventional technique.
FIG. 6 is a waveform chart for explaining the operation of FIG. 5;
FIG. 7 is a frequency characteristic curve diagram for explaining the operation of FIG. 5;
[Explanation of symbols]
REFERENCE SIGNS LIST 10 voltage supply circuit 11 operational amplifier 12 negative feedback circuit 13 current measuring resistor 14 antiparallel circuit of diode 15 phase compensation capacitor 16 bypass capacitor TO voltage output terminal 18 voltage source 20 current measuring means 25 load 30 current supply circuit 40 current suction Circuit 50, 60 switching circuit

Claims

An operational amplifier whose input terminal is given a constant voltage, and a voltage that is supplied with the output voltage of the operational amplifier and supplies the output voltage to a load that periodically consumes an operating current whose peak value is larger than a steady-state current between the output terminal, a voltage supply circuit constituted by a feedback circuit for feeding back the voltage of the voltage output terminal to the inverting input terminal of the operational amplifier, the output terminal and the voltage output terminal of the operational amplifier constituting the voltage supply circuit a current measuring resistor connected to a bypass capacitor connected between the common potential point and the voltage output terminal, and a phase compensation capacitor connected in parallel to the upper Symbol current measuring resistor, said current measuring resistor And a current measuring means for measuring a current value output from the operational amplifier to a voltage output terminal.
A current supply circuit for detecting that the voltage of the voltage output terminal is slightly lower than the voltage at the time of steady state at the voltage output terminal, and supplying a current to the potential supply terminal ; A voltage application current measurement circuit, further comprising: a current suction circuit for detecting that the voltage has become slightly higher than the voltage and sucking a current from the voltage supply terminal.

2. The voltage application current measurement circuit according to claim 1, further comprising: a switching circuit for disconnecting the current supply circuit and the current attraction circuit from the voltage supply terminal after a predetermined time has elapsed from a point in time when the operation current flowing periodically is interrupted. A voltage applied current measuring circuit, characterized in that:

2. The voltage application current measurement circuit according to claim 1, wherein the current supply circuit outputs a voltage slightly lower than a steady state voltage value output to the voltage supply terminal, and the voltage of the voltage source is connected to an anode. A voltage applied current measuring circuit, comprising: a diode having a cathode connected to a voltage output terminal of the voltage supply circuit; and a current source having a current output terminal connected to an anode of the diode.

2. The voltage applying current measuring circuit according to claim 1, wherein the current attracting circuit outputs a voltage slightly higher than a steady state voltage of the voltage output terminal; Is connected to a connection point between the diode connected to the voltage output terminal and the cathode of the diode and the voltage source, and when the voltage of the voltage supply terminal becomes higher than the voltage of the voltage source, the diode is connected through the diode. A voltage application current measurement circuit, comprising: a current source that draws a current from a voltage output terminal.