CN210985645U

CN210985645U - Integrated circuit for preventing positive and negative electrodes from being reversely connected and buffering electrification

Info

Publication number: CN210985645U
Application number: CN201921923990.0U
Authority: CN
Inventors: 蒋山; 刘鑫; 陈静; 陈茂才; 张家玉; 于华栋; 羊左成; 陈培杰
Original assignee: 704th Research Institute of CSIC
Current assignee: 704th Research Institute of CSIC
Priority date: 2019-11-06
Filing date: 2019-11-06
Publication date: 2020-07-10
Anticipated expiration: 2029-11-06

Abstract

The utility model relates to a prevent positive negative pole reversal and buffering integrated circuit of going up, buffer resistance R1 with prevent the reversal diode D1 back of establishing ties, constitute the main circuit with parallel connection's forward thyristor T2 and reverse thyristor T1 are parallelly connected again, the main circuit concatenates and constitutes protection circuit at the anodal front end of power conversion equipment input direct current side, the drive circuit of forward thyristor T2 and reverse thyristor T1 gate pole connects before the main circuit, DC power source inserts power conversion equipment, drive circuit is through discerning DC power source nature, automatic judgement switches on the main circuit. The power conversion device has the function of buffering power-on, reduces impact on the power conversion device at the moment of power-on, and can judge the positive and negative polarities of the input voltage to prevent the power conversion device from being damaged due to reverse polarity connection. The power supply and the power conversion device are protected to a great extent. Meanwhile, compared with other devices with the functions, the design circuit greatly reduces the size and saves the space.

Description

Integrated circuit for preventing positive and negative electrodes from being reversely connected and buffering electrification

Technical Field

The utility model relates to a protection circuit, in particular to integrated circuit who goes up in positive negative pole transposition and buffering of preventing.

Background

For devices such as a direct-current input frequency converter, an inverter power supply and the like, the positive and negative polarities of the input power supply are very important, if the input power supply is reversely connected, an immeasurable effect can be caused, and the reverse connection prevention circuit can identify the polarity of the input power supply and play a role in protection. At the moment of power-on, the impact of the bus capacitor is large, and the buffer circuit can play a role in reducing the impact of the bus capacitor. Although the circuit for preventing the reverse connection of the power supply, which is disclosed in the chinese patent No. 201710885164.0, can realize functions, the circuit is long in time consumption and complex in control, and a buffering power-on circuit needs to be designed separately; the buffering power-on circuit disclosed in chinese patent No. 201711067384.9 has a complex circuit topology structure, and cannot effectively determine the polarity of an input power source. Both of the above two circuit structures fail to sufficiently achieve high-speed and high-efficiency performance and save space.

Disclosure of Invention

The utility model discloses a to going up the problem that the electricity damages anti-relative power conversion equipment of positive negative pole in the twinkling of an eye to bus capacitor's impact and positive negative pole, provided an integrated circuit who prevents positive negative pole transposition and buffering and go up, effectively judged direct current source positive and negative polarity to the circuit structure of going up electricity to bus capacitor buffering, to a great extent plays the guard action to the device.

The technical scheme of the utility model is that: an integrated circuit for preventing the reverse connection of positive and negative electrodes and buffering electrification is characterized in that a buffer resistor R1 and a reverse connection prevention diode D1 are connected in series and then are connected in parallel with a forward thyristor T2 and a reverse thyristor T1 which are connected in parallel to form a main circuit, the main circuit is connected in series at the front end of the positive electrode on the input direct current side of a power conversion device to form a protection circuit, a direct current power supply is connected into the power conversion device, an output signal of the direct current power supply passes through a driving circuit for identifying the polarity of the direct current power supply, and the driving circuit outputs gate signals of the forward thyristor T2 and the reverse thyristor T1 to.

The drive circuit comprises an identification circuit, a delay circuit and a trigger circuit in sequence,

an identification circuit: three same-direction anti-reverse-connection diodes D2, D3 and D4 and a current-limiting resistor R4 are connected in series between a positive end point A and a negative end point B of a direct-current power supply input by the power conversion device, an anti-reverse-connection diode D5 is connected in parallel to an anti-reverse-connection diode D3 in the middle of the three same-direction serially-connected anti-reverse-connection diodes, the negative electrode and the positive electrode of an anti-reverse-connection diode D5 are respectively connected with the positive electrode and the negative electrode of an input end of a signal processing optocoupler chip P1, the output end of the signal processing optocoupler chip P1 is connected between a circuit power supply VCC and a VCC _ GND ground in series connection with a pull-down resistor R5, and the output end of the signal processing optoco;

the time delay circuit: the serial point of the output end of the signal processing optocoupler chip P1 AND the pull-down resistor R5 is respectively connected with No. 2 input pins of two logic AND gates AND1 AND AND2, the No. 1 input pins of the input ends of the two logic AND gates AND1 AND AND2 are connected with a delay control signal T _ Drive, AND when the T _ Drive reaches the high level V of the two logic AND gates AND1 AND AND2_highWhen the voltage is applied, the level of the pin No. 2 of the logic AND gate is judged to determine the high level AND the low level of the output level, AND the two logic AND gates AND1 AND AND2 output contact circuits;

a trigger circuit:

the output end of the logic AND gate AND1 is connected to the input anode of the thyristor-driven optocoupler chip P2, a current-limiting resistor R2 is connected between the output end of the logic AND gate AND1 in series, AND the output end of the thyristor-driven optocoupler chip P2 is connected with the output end of the thyristor-driven optocoupler chip P2A current limiting resistor R6 connected in series with the power supply V_DD1And the gate g1 of the inverse thyristor T1,

the output end of the logic AND gate AND2 is connected to the input anode of the thyristor-driven optocoupler chip P3, AND a current-limiting resistor R3 is connected in series between the output end of the thyristor-driven optocoupler chip P3 AND the current-limiting resistor R7, the output end of the thyristor-driven optocoupler chip P3 is connected in series between a power supply VDD1 AND a gate g2 of a forward thyristor T2,

the cathode S1 of the reverse thyristor T1 is grounded to VDD1_ GND, the cathode S2 of the forward thyristor T2 is grounded to VDD2_ GND, and VDD1_ GND and VDD2_ GND must be isolated from each other.

The beneficial effects of the utility model reside in that: the utility model discloses prevent positive negative pole transposition and buffering and go up the integrated circuit of electricity, not only have the buffering and go up the electric function, reduce to go up the impact to power conversion device in the twinkling of an eye, can also judge the positive and negative polarity of input voltage, prevent to cause the damage to power conversion device because of polarity transposition. The power supply and the power conversion device are protected to a great extent. Meanwhile, compared with other devices with the functions, the design circuit greatly reduces the size and saves the space.

Drawings

FIG. 1 is a main circuit diagram of the integrated circuit for preventing the reverse connection of the positive electrode and the negative electrode and buffering the electrification of the battery of the present invention;

fig. 2 is a circuit diagram of the driving circuit of the forward and backward thyristors of the present invention.

Detailed Description

As shown in fig. 1, the main circuit of the integrated circuit is formed by connecting a buffer resistor 4(R1) and an anti-reverse diode 3(D1) in series, and then connecting the buffer resistor in parallel with a forward thyristor 1(T2) and a reverse thyristor 2(T1) which are connected in parallel to prevent the reverse connection of the positive electrode and the negative electrode and buffer the electric shock. The main circuit is connected in series with the front end of the positive electrode on the input direct current side of the power conversion device to form a protection circuit. The buffer resistor R1 is a power resistor, the resistance of R1 is selected, and the maximum allowable value U of the DC input voltage of the power conversion device is selected_maxThe resistance value of R1 is selected to be 10U in relation to the impact current Ic of the bus capacitor C_max/Ic～30U_maxand/Ic. The positive pole of the reverse connection prevention diode 3 is connected with one end of a direct current power supply through a buffer resistor R1, and the negative pole of the reverse connection prevention diode is connected with the direct current of the power conversion deviceAnd a current bus capacitor. Reverse peak voltage V of reverse connection prevention diode D1_RWM1And the maximum allowable value U of the DC input voltage of the power conversion device_maxThe current endurance I1 is related to the maximum allowable value U of the DC input voltage_maxAnd the resistance of the buffer resistor R1, i.e. 3U_max>V_RWM1>2U_max，3U_max/R1>I1>2U_maxand/R1. The positive pole of the forward thyristor 1 is connected with one end of a direct current power supply, the negative pole of the forward thyristor is connected with a direct current bus capacitor of the power conversion device, the negative pole of the reverse thyristor 2 is connected with one end of the direct current power supply, the positive pole of the forward thyristor is connected with the direct current bus capacitor of the power conversion device, and the two thyristors can be selected from modular thyristors (namely one package contains two thyristor elements). Thyristor reverse peak voltage V_RWM2And the maximum allowable value U of the DC input voltage of the power conversion device_maxThe current withstanding value I2 is related to the minimum allowable value U of the DC input voltage of the power conversion device_minThe reverse peak voltage of the thyristor is selected to be 3U according to the power P of the power conversion device_max>V_RWM2>2U_maxThe selection range of the thyristor reverse peak voltage current endurance value is 3P/U_min>I2>2P/U_min。

In this embodiment, the DC input voltage range is 350V-640V, i.e. U_max＝640V，U_min350V, impact current I of bus capacitor_cThe power converter power P is 35kVA at 800A. Through optimized calculation, the resistance value R of the buffer resistor (4)₁0.8-24 Ω, preferably 20 Ω; reverse peak voltage V of reverse connection prevention diode (3)_RWM11280V to 1920V, preferably 1500V, and a flow resistance value I₁64-96A, preferably 60A; current endurance value I of thyristor (1) and inverse thyristor (2)₂200-300A, preferably 250A, inverse peak voltage V_RWM21280V to 1920V, 1500V is preferred.

As shown in fig. 2, a driving circuit of the forward thyristor 1 and the backward thyristor 2 is designed, and three

diodes

6, 7, 8(D2, D3, D4) and a current limiting resistor 5(R4) are connected in series between a positive terminal a point and a negative terminal B point of the input dc power of the power conversion device. The middle anti-reverse diode 7(D3) of the three anti-reverse diodes connected in series in the same direction is connected with an anti-reverse diode in parallelThe negative pole and the positive pole of the phase voltage limiting diode 9(D5) and the negative pole and the positive pole of the reverse voltage limiting diode 9(D5) are respectively connected with the positive pole and the negative pole of the input end of the signal processing optocoupler chip 10 (P1). The three reverse connection preventing diodes and the reverse voltage limiting diode 9 can select the same type of diode, and the reverse voltage withstanding value V of the selected diode_DRM3And the maximum allowable value U of the DC input voltage of the power conversion device_maxIn connection, the average forward current I3 is related to the forward conducting current If1 of the signal processing optocoupler chip 10(P1), i.e. 3U_max>V_DRM3>2U_max，40If1>I3>20If 1. The current limiting resistor 5(R4) is selected as a power resistor, R4 resistance and the minimum allowable value U of the DC input voltage of the power conversion device_min3U related to forward conducting current If1 of signal processing optocoupler chip 10(P1)_min/10If1>R4>3U_min15If 1; rated power P of R4_R4And its resistance value and maximum allowable value U of DC input voltage_maxIn connection with, i.e. 3 (U)_max)2/R4>P_R4>2(U_max) 2/R4. In this embodiment, the DC input voltage range is 350V-640V, i.e. U_max＝640V，U_min350V, the forward conducting current I of the signal processing optical coupling chip (10)_f1Is 5 mA. Through optimization calculation, V_DRM31280V to 1920V, preferably 1500V, I₃100 to 200mA, preferably 100mA, R₄14-21 k omega, preferably 17k omega, P_R4The weight is 48-72W, preferably 60W.

The output end of the signal processing optocoupler chip 10(P1) is connected in series with the pull-down resistor 19(R5) between the circuit power supply VCC (23) AND VCC _ GND (22), AND the serial point of the output end of the signal processing optocoupler chip 10(P1) AND the pull-down resistor 19(R5) is respectively connected with the input pins No. 2 of the logic AND gates 11 AND 12(AND1 AND 2). Wherein the resistance of the pull-down resistor R5 and the voltage value U of the power supply VCC (22)_VCCAnd the loading capacity of the signal processing optocoupler chip 10 (P1). If the load current of the signal processing optocoupler chip 10(P1) is Icb, 15U_VCC/Icb<R5<20U_VCCand/Icb. VCC (22) voltage value U_VCCHigh level V of AND-AND-logic AND gates 11, 12(AND1, AND2)_highIn relation to, i.e. V_high<U_VCC<1.2V_high. Wherein, the logic AND gates 11, 12(AND1, AND2) canIntegrated in the same chip. The 1 pin of the input end of the logic AND gates 11 AND 12(AND1 AND2) is connected to the delay control signal T _ Drive to control whether the circuit works or not. When T _ Drive reaches the high level V of the logical AND gates 11, 12(AND1, AND2)_highWhen the voltage is applied to the first pin, the level of the second pin is determined, AND otherwise, the output of the logic AND gates 11 AND 12(AND1 AND2) is always low, so that the circuit cannot work.

In the embodiment, the logic AND gates (11) (12) are integrated with the high level V of the chip_highThe load current of the signal processing optocoupler chip (10) is I (3.3V)_cb5 mA. Then U is_VCC3.3-4V, preferably 3.3V; r₅8.6-13.2 k omega, preferably 10k omega. And a pin 1 at the input end of the logic AND gates (11) and (12) is connected with a control signal T _ Drive to control whether the circuit works or not. When T _ Drive reaches the high level (3.3V) of the logic and gates 11 and 12, the level of the output level can be determined by judging the level of the pin No. 2, otherwise, the outputs of the logic and gates 11 and 12 are always low, and the circuit cannot work.

The output end of the logic AND gate 11(AND1) is connected to the input anode of the thyristor-driven optocoupler chip 13(P2), AND a current-limiting resistor 20(R2) is connected in series between the two. The resistance value of the current limiting resistor 20(R2) AND the high-level voltage V of the logic AND gate (11) (AND1) integrated chip_highAnd a forward conducting current If2 of the signal processing optocoupler chip 13(P2), and 1.1V_high/If2<R2<1.5V_highand/If 2. The thyristor drives the input negative pole of the optocoupler chip (13) (P2) to be grounded VCC _ GND (22). The output end of the logic AND gate 12(AND2) is connected to the input anode of the thyristor-driven optocoupler chip 14(P3), AND a current-limiting resistor 21(R3) is connected in series between the two. The resistance value of the current limiting resistor 21(R3) AND the high-level voltage V of the logic AND gate 12(AND2) integrated chip_highAnd a forward conducting current If3 of the signal processing optocoupler chip 14(P3), and 1.1V_high/If3<R3<1.5V_highand/If 3. The thyristor drives the input cathode of the optocoupler chip 14(P3) to ground VCC _ GND (22).

In the embodiment, the forward conducting current I of the signal processing optocoupler chip (13)_f25mA, the forward conducting current I of the signal processing optical coupling chip 14_f35mA, high level voltage V of logic AND gate 11, 12 integrated chip_highWhen the voltage is 3.3V, the resistance value R of the current-limiting resistor (20) is₂726-990 Ω, preferably 750 Ω, and the resistance R of the current limiting resistor 21₃726-990 Ω, preferably 750 Ω.

The output end of the thyristor-driven optocoupler chip 13(P2) is connected with the current-limiting resistor 23(R6) in series with a power supply V_DD1(15) And the gate g1 of the triac 2 (T1). In which VDD1(15) power supply voltage U_VDD1In relation to the trigger voltage VT2 of the inverse thyristor 2(T1), i.e. VT2<U_VDD1<1.2VT 2. The resistance of the current limiting resistor 23(R6) is related to the holding current Id2 of the inverse thyristor 2(T1), and 0.8U_VDD1/Id2<R6<U_VDD1and/Id 2. In the present embodiment, the inverse thyristor (2) triggers a voltage V_T2Holding current I of 5V_d2250 mA. Then R is₆20-16 omega, preferably 18 omega, U_VDD1＝5V；U_VDD1The voltage is 5-6V, and 5V is preferred.

The output end of the thyristor-driven optocoupler chip 14(P3) and the current-limiting resistor 24(R7) are connected in series between a power supply VDD1(16) and the gate g2 of the forward thyristor 1 (T2). And VDD1(15) and VDD2(16) must be isolated from each other. Wherein V_DD2(16) Supply voltage U_VDD2Related to the trigger voltage VT1 of the forward thyristor 1(T2), i.e. VT1<U_VDD2<1.2VT 1. The resistance of the current limiting resistor 24(R7) is related to the holding current Id1 of the forward thyristor 1(T2), and 0.8U_VDD2/Id1<R7<U_VDD2and/Id 1. In the present embodiment, the inverse thyristor (2) triggers a voltage V_T1Holding current I of 5V_d1250 mA. Then R is₇20-16 omega, preferably 18 omega, U_VDD2＝5V；U_VDD2The voltage is 5-6V, and 5V is preferred.

The cathode S1 of the reverse thyristor (2) is connected with the ground VDD1_ GND (17) of the VDD1(15), and the cathode S2 of the forward thyristor 1(T2) is connected with the ground VDD2_ GND (18) of the VDD2 (16). And VDD1_ GND (17) and VDD2_ GND (18) must be isolated from each other.

When the polarity of the direct-current input voltage of the power conversion device is correct, the signal processing optocoupler chip 10(P1) is turned on, and the 1 pin of the logic AND gates 11 and 12 sets a high level (3.3V), so that the thyristor is ensured to have a turn-on condition. When the T _ Drive delay reaches the high level (3.3V) of the logic AND gates 11 and 12, the logic AND gates 11 and 12 output the high level, and further Drive the signal processing optocoupler chips 13(P2) and 14(P3) to be conducted, so that the power supply VDD1 is added to the g1 end, the VDD2 is added to the g2 end, the forward thyristor 1 and the reverse thyristor 2 are driven to be conducted, and the buffering power-on process is completed. When the direct-current input power supply of the power conversion device is reversely connected, the signal processing optocoupler chip 10(P1) cannot be turned on, the 1 pin of the logic and gates 11 and 12 is constantly low, and the outputs of the logic and gates 11 and 12 are both low no matter whether T _ Drive reaches the high level (3.3V) of the logic and gates 11 and 12, so that the driving signal processing optocoupler chips 13(P2) and 14(P3) are not turned on, so that the forward thyristor 1 and the reverse thyristor 2 cannot obtain driving signals, and the off state is maintained, and further equipment is protected from being damaged.

Claims

1. The integrated circuit is characterized in that a buffer resistor R1 and an anti-reverse diode D1 are connected in series and then connected in parallel with a forward thyristor T2 and a reverse thyristor T1 which are connected in parallel to form a main circuit, the main circuit is connected in series at the front end of the input direct current side positive electrode of a power conversion device to form a protection circuit, a direct current power supply is connected into the power conversion device, a direct current power supply output signal passes through a driving circuit for identifying the polarity of the direct current power supply, and the driving circuit outputs gate signals of the forward thyristor T2 and the reverse thyristor T1 to conduct or block the main circuit.

2. The integrated circuit for preventing the reverse connection of the positive electrode and the negative electrode and buffering the electrification according to claim 1, wherein the driving circuit sequentially comprises an identification circuit, a delay circuit and a trigger circuit,

a trigger circuit:

the output end of the logic AND gate AND1 is connected to the input anode of the thyristor-driven optocoupler chip P2, a current-limiting resistor R2 is connected between the output end of the logic AND gate AND1 in series, AND the output end of the thyristor-driven optocoupler chip P2 AND the current-limiting resistor R6 are connected in series with a power supply V_DD1And the gate g1 of the inverse thyristor T1,

the cathode S1 of the reverse thyristor T1 is grounded to VDD1_ GND, the cathode S2 of the forward thyristor T2 is grounded to VDD2_ GND, and VDD1_ GND and VDD2_ GND are isolated from each other.