CN210958960U - Multilayer circuit board test structure - Google Patents
Multilayer circuit board test structure Download PDFInfo
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- CN210958960U CN210958960U CN201922338162.7U CN201922338162U CN210958960U CN 210958960 U CN210958960 U CN 210958960U CN 201922338162 U CN201922338162 U CN 201922338162U CN 210958960 U CN210958960 U CN 210958960U
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Abstract
The utility model discloses a multilayer circuit board test structure, wherein the surface of each layer of circuit board is provided with at least one conducting layer; the conductive layer includes: the first test area is used for forming a first test hole, and all the conductive layers are electrically connected through the first test hole; and a second test area which is hollowed out and exposes the substrate and is used for forming a second test hole, and the second test hole penetrates through the multilayer circuit board. When the multilayer circuit board has no short circuit problem, the second test holes penetrate all the second test areas, and an open circuit is formed between the first test holes and the second test holes. When the multilayer circuit board has the short circuit problem between the hole and the adjacent line, the second test hole deviates from the second test area of the layer of circuit board, so that the second test hole is conducted with the conductive layer of the layer of circuit board, and the short circuit phenomenon exists between the first test hole and the second test hole, so that the multilayer circuit board is judged to have the short circuit problem, and the multilayer circuit board is prevented from flowing out to the next procedure.
Description
Technical Field
The utility model belongs to the technical field of the multilayer circuit board, especially, relate to a multilayer circuit board test structure.
Background
In the manufacturing process of the multilayer circuit board, since the distance between a hole (such as a kebang hole) and an adjacent line is small, the problem of short circuit between the hole and the adjacent line is easy to occur. However, in the prior art, the short circuit problem is usually detected only when the manufacturing process reaches the electrical measurement process, thereby causing the problems of wasting the processing cost of the work station and reducing the production efficiency.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a multilayer circuit board test structure can short circuit problem between the short-circuit hole and the adjacent circuit of short-circuit fast detection, prevents that the multilayer circuit board of short circuit from continuing to flow to next process, and then avoids the extravagant processing cost who causes from this and reduction in production efficiency's problem.
To achieve the purpose, the utility model adopts the following technical proposal:
a multilayer circuit board test structure is provided, wherein the surface of each layer of circuit board is provided with at least one conducting layer; the conductive layer includes:
the first test area is used for forming a first test hole, the first test hole penetrates through the multilayer circuit board, and all the conductive layers are electrically connected through the first test hole;
and the second testing area is hollowed out and exposed out of the substrate and is used for forming a second testing hole, the second testing hole penetrates through the multilayer circuit board, and the distance between the boundary of the second testing hole and the boundary of the second testing area is equal to a preset short-circuit distance.
Optionally, the conductive layer is a copper sheet.
Optionally, four conductive layers are disposed on the surface of each layer of the circuit board, and the four conductive layers are respectively located at four corners of the circuit board.
Optionally, the second test area comprises a plurality of test sub-areas of different diameters for testing different multilayer circuit boards.
Optionally, all the test small areas in each conductive layer are distributed in a straight line.
Optionally, there are five small test regions in each conductive layer, and the short circuit distances corresponding to the five small test regions are 4mil, 5mil, 6mil, 7mil and 8mil, respectively.
Optionally, the second test area is circular in shape.
Optionally, the multilayer circuit board test structure further comprises a test instrument for testing a short circuit between the first test hole and the second test hole.
Optionally, the test instrument is a multimeter.
Optionally, the multilayer circuit board comprises an outer layer circuit board and a plurality of inner layer circuit boards;
and the second test area on the outer layer circuit board is provided with an aperture windowing structure for opening the second test hole.
Compared with the prior art, the embodiment of the utility model provides a following beneficial effect has:
the embodiment of the utility model provides a pair of multilayer circuit board test structure, every layer circuit board all is equipped with the conducting layer, because first test area territory possesses the conductive characteristic of conducting layer, first test hole runs through the first test area territory of multilayer circuit board, and all conducting layers are in the same place through first test hole electric connection. The second testing hole penetrates through the multilayer circuit board, and the second testing area is hollow and exposes the substrate (non-conducting), so that the second testing area is non-conducting. When the multilayer circuit board has no short circuit problem, the second test holes penetrate all the second test areas, and an open circuit is formed between the first test holes and the second test holes. However, when the multilayer circuit board has a short circuit problem between the hole and the adjacent line, that is, at least one layer of circuit board has a manufacturing error (i.e., the offset distance between the hole and the adjacent line) greater than the short circuit distance, the second test hole deviates from the second test area of the layer of circuit board, which causes the second test hole to be conducted with the conductive layer of the layer of circuit board, so that a short circuit phenomenon exists between the first test hole and the second test hole, thereby determining that the multilayer circuit board has a short circuit problem and preventing the multilayer circuit board from flowing out to the next process.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
The structure, ratio, size and the like shown in the present specification are only used for matching with the content disclosed in the specification, so as to be known and read by people familiar with the technology, and are not used for limiting the limit conditions which can be implemented by the present invention, so that the present invention has no technical essential significance, and any structure modification, ratio relationship change or size adjustment should still fall within the range which can be covered by the technical content disclosed by the present invention without affecting the efficacy and the achievable purpose of the present invention.
Fig. 1 is a structural diagram of a multilayer circuit board test structure according to an embodiment of the present invention;
fig. 2 is another structural diagram of a multilayer circuit board testing structure according to an embodiment of the present invention;
fig. 3 is an outer circuit board structure diagram of a multi-layer circuit board testing structure according to an embodiment of the present invention.
Illustration of the drawings:
the circuit board 10, the conductive layer 20, the second test area 30, the outer layer circuit board 40, the first test small area 31, the second test small area 32, the third test small area 33, the fourth test small area 34, the fifth test small area 35, and the aperture windowing structure 36.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the embodiments of the present invention are clearly and completely described with reference to the drawings in the embodiments of the present invention, and obviously, the embodiments described below are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Please refer to fig. 1.
The embodiment provides a multilayer circuit board test structure which can be used for carrying out short circuit detection on a multilayer circuit board before an electrical testing process.
Specifically, a conductive layer 20 is provided on the surface of each layer of the circuit board 10. According to the requirement, four conductive layers 20 are arranged on the surface of each layer of circuit board 10, and the four conductive layers 20 are respectively positioned at four corners of the circuit board 10. The conductive layer 20 may be a copper sheet, which covers the surface of each layer of the circuit board 10.
The conductive layer 20 includes a first testing area (not shown) for forming a first testing hole (not shown), and the specific position of the first testing area is not limited as long as the first testing area is located on the conductive layer 20 and not located on the second testing area 30, and when the first testing hole penetrates through the multilayer circuit board, all the conductive layers 20 can be electrically connected through the first testing hole.
The conductive layer 20 further includes a second test area 30 that is hollowed out and exposed out of the substrate, which is non-conductive. The second test area 30 is used for forming a second test hole (not shown). In this embodiment, the second test area 30 is circular in shape.
The distance between the kebang hole and the adjacent line should be a predetermined distance for each layer of circuit board 10. When the kebang hole is short-circuited with the adjacent line, that is, when the layer of circuit board 10 is processed, the kebang hole is deviated from the adjacent line by a position greater than the predetermined distance, which causes short-circuiting. Therefore, the position deviation is generated during short circuit, when a short circuit is generated on any layer of circuit board 10, and the second test hole penetrates through each layer of circuit board 10, the second test hole directly collides with the conductive layer 20 of the layer, namely, the conductive layer 20 can be contacted in the second test hole, so that a short circuit phenomenon exists between the first test hole and the second test hole, namely, a short circuit between the first test hole (electrically connected to the conductive layer 20 of the short-circuited circuit board) and the second test hole (electrically connected to all the conductive layers 20) can be measured by using a measuring instrument, so as to assist in judging the short circuit of the multilayer circuit board before the electrical measurement process, prevent the short-circuited multilayer circuit board from flowing out to the next process, avoid the waste of production cost and reduce of production efficiency. Alternatively, the test instrument is a multimeter.
It should be noted that, when the multilayer circuit board is normal, the second test hole penetrates through the multilayer circuit board, and the distance between the boundary of the second test hole and the boundary of the second test area 30 is equal to the short-circuit distance. The short circuit distance needs to be greater than or equal to the above preset distance.
During testing, as long as the first test hole and the second test hole in any one of the conductive layers 20 are short-circuited, the multilayer circuit board is determined to be a defective product.
In another embodiment of the present application, please refer to fig. 2. The second test area 30 includes a plurality of test sub-areas of different diameters for testing different sized multilayer circuit boards. And selecting corresponding small test areas for testing according to the requirements of the multilayer circuit boards with different specifications.
Specifically, for example, there are five test small areas in each conductive layer 20, which are a first test small area 31, a second test small area 32, a third test small area 33, a fourth test small area 34, and a fifth test small area 35. The short circuit distances for the five test small areas were 4mil, 5mil, 6mil, 7mil, and 8mil, respectively. Corresponding to the multilayer circuit boards with different specifications, when the preset distance is 4mil, the first testing small area is selected to open the second testing hole, when the preset distance is 5mil, the second testing small area 32 is selected to open the second testing hole, and so on.
Specifically, the five test small regions in each conductive layer can be selected to be in a straight line distribution.
In another embodiment of the present application, the multilayer circuit board includes an outer layer circuit board 40 and a plurality of inner layer circuit boards. The structure of the inner layer circuit board is shown in fig. 2. The structure of the outer circuit board 40 is shown in fig. 3.
The second testing area 30 on the outer circuit board 40 is provided with an aperture windowing structure 36 for opening a second testing hole.
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "including," and "having" are intended to be inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed and illustrated, unless explicitly indicated as an order of performance. It should also be understood that additional or alternative steps may be employed.
When an element or layer is referred to as being "on" … … "," engaged with "… …", "connected to" or "coupled to" another element or layer, it can be directly on, engaged with, connected to or coupled to the other element or layer, or intervening elements or layers may also be present. In contrast, when an element or layer is referred to as being "directly on … …," "directly engaged with … …," "directly connected to" or "directly coupled to" another element or layer, there may be no intervening elements or layers present. Other words used to describe the relationship of elements should be interpreted in a similar manner (e.g., "between … …" and "directly between … …", "adjacent" and "directly adjacent", etc.). As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region or section from another element, component, region or section. Unless clearly indicated by the context, use of terms such as the terms "first," "second," and other numerical values herein does not imply a sequence or order. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.
Spatially relative terms, such as "inner," "outer," "below," "… …," "lower," "above," "upper," and the like, may be used herein for ease of description to describe a relationship between one element or feature and one or more other elements or features as illustrated in the figures. Spatially relative terms may be intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example term "below … …" can encompass both an orientation of facing upward and downward. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted.
The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.
Claims (10)
1. A multilayer circuit board test structure is characterized in that the surface of each layer of circuit board is provided with at least one conducting layer; the conductive layer includes:
the first test area is used for forming a first test hole, the first test hole penetrates through the multilayer circuit board, and all the conductive layers are electrically connected through the first test hole;
and a second test area which is hollowed out and exposes out of the substrate and is used for forming a second test hole, wherein the second test hole penetrates through the multilayer circuit board.
2. The multilayer circuit board test structure of claim 1, wherein the conductive layer is a copper sheet.
3. The multi-layer circuit board test structure of claim 1, wherein four conductive layers are disposed on the surface of each layer of the circuit board, and the four conductive layers are respectively disposed at four corners of the circuit board.
4. A multilayer circuit board test structure according to claim 1 or 3, wherein the second test area comprises a plurality of test sub-areas of different diameters for testing different multilayer circuit boards.
5. The multilayer circuit board test structure of claim 4, wherein all of said test sub-areas within each of said conductive layers are linearly disposed.
6. The multi-layer circuit board test structure of claim 5, wherein there are five of said test sub-areas in each of said conductive layers, said five test sub-areas corresponding to short circuit distances of 4 mils, 5 mils, 6 mils, 7 mils, and 8 mils, respectively.
7. The multilayer circuit board test structure of claim 1, wherein the second test area is circular in shape.
8. The multilayer circuit board test structure of claim 1, further comprising a test instrument for testing a short circuit between the first test hole and the second test hole.
9. The multilayer circuit board test structure of claim 8, wherein the test instrument is a multimeter.
10. The multilayer circuit board test structure of claim 1, wherein the multilayer circuit board comprises an outer layer circuit board and a plurality of inner layer circuit boards;
and the second test area on the outer layer circuit board is provided with an aperture windowing structure for opening the second test hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922338162.7U CN210958960U (en) | 2019-12-23 | 2019-12-23 | Multilayer circuit board test structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201922338162.7U CN210958960U (en) | 2019-12-23 | 2019-12-23 | Multilayer circuit board test structure |
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| CN210958960U true CN210958960U (en) | 2020-07-07 |
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| CN201922338162.7U Active CN210958960U (en) | 2019-12-23 | 2019-12-23 | Multilayer circuit board test structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113163592A (en) * | 2021-04-25 | 2021-07-23 | 东莞市五株电子科技有限公司 | Visual blind hole deviation detection structure and printed circuit board |
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2019
- 2019-12-23 CN CN201922338162.7U patent/CN210958960U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113163592A (en) * | 2021-04-25 | 2021-07-23 | 东莞市五株电子科技有限公司 | Visual blind hole deviation detection structure and printed circuit board |
| CN113163592B (en) * | 2021-04-25 | 2023-08-22 | 东莞市五株电子科技有限公司 | Blind hole deviation detection structure capable of being visualized and printed circuit board |
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