CN210956656U

CN210956656U - Chip packaging structure and memory

Info

Publication number: CN210956656U
Application number: CN201922333422.1U
Authority: CN
Inventors: 李振华; 刘焱
Original assignee: Biwin Storage Technology Co Ltd
Current assignee: Biwin Storage Technology Co Ltd
Priority date: 2019-12-23
Filing date: 2019-12-23
Publication date: 2020-07-07
Anticipated expiration: 2029-12-23

Abstract

The utility model discloses a chip packaging structure, this chip packaging structure include PCB base plate, chip wafer and encapsulated layer, the front of PCB base plate is equipped with and is used for the installation position of chip wafer, installation position department is equipped with copper layer and silver thick liquid layer in proper order, the subsides of chip wafer are located on the silver thick liquid layer, the surface cover of chip wafer has the encapsulated layer. The utility model discloses a chip package structure can realize dispelling the heat fast, need not to subtract redundant heat radiation structure design with the help of outside heat radiation structure (like heat conduction silica gel piece and heat dissipation shell), helps the miniaturized development of chip. Furthermore, the utility model discloses still disclose a memory.

Description

Chip packaging structure and memory

Technical Field

The utility model relates to a chip package technical field, in particular to chip package structure and memory.

Background

As is well known, a large amount of heat is generated during the operation of a chip, and if the heat cannot be dissipated in time, the service performance and the service life of the chip are affected.

The chip is mainly formed by packaging a PCB (printed circuit board), an electronic component, epoxy resin and the like, and at present, the chip is used for radiating heat by bonding a heat-conducting silica gel sheet and a heat-radiating shell on the outside. However, due to the design and arrangement of the heat dissipation mechanism, the chip has an excessively large size, occupies a large space, and is not favorable for the miniaturization development of the chip.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a chip packaging structure aims at solving the chip and is unfavorable for its problem towards miniaturized development because of traditional heat radiation structure.

In order to achieve the above object, the utility model provides a chip packaging structure, this chip packaging structure include PCB base plate, chip wafer and encapsulated layer, the front of PCB base plate is equipped with and is used for the installation position of chip wafer, installation position department is equipped with copper layer and silver thick liquid layer in proper order, the chip wafer pastes and locates on the silver thick liquid layer, the surface cover of chip wafer has the encapsulated layer.

Preferably, the bottom of the PCB substrate is provided with a plurality of solder balls.

Preferably, the PCB substrate is provided with a plurality of ground holes which penetrate through the front surface and the back surface of the PCB substrate and are positioned below the copper layer.

Preferably, four side edges of the silver paste layer are upwards bulged to form an enclosing part attached to the side edge of the chip wafer.

Preferably, the area of the silver paste layer is the same as the area of the chip wafer, and the area of the copper layer is larger than the area of the chip wafer.

Preferably, the PCB substrate has a plurality of conductive pads circumferentially arranged along the mounting site, and the chip wafer is connected to the plurality of conductive pads through leads.

Preferably, the front surface of the PCB substrate is provided with a plurality of blind holes located below the copper layer, and the copper layer includes a copper filling portion penetrating into the blind holes.

The utility model also provides a memory, this memory include mainboard and chip package structure, chip package structure sets up on the mainboard, chip package structure includes PCB base plate, chip wafer and encapsulated layer, the front of PCB base plate is equipped with and is used for the installation position of chip wafer, installation position department is equipped with copper layer and silver thick liquid layer in proper order, the subsides of chip wafer are located on the silver thick liquid layer, the surface covering of chip wafer has the encapsulated layer.

In the chip packaging structure, heat generated by the chip wafer is transferred to the copper layer through the silver paste layer, then transferred to the PCB substrate through the copper layer, and finally transferred to the external environment through the PCB substrate. Compared with the prior art, the packaging structure has high heat dissipation efficiency, can reduce thermal resistance in the package, and improves the reliability and stability of the product; and the design of a redundant heat dissipation structure is reduced without an external heat dissipation structure (such as a heat conduction silica gel sheet and a heat dissipation shell), so that the miniaturization development of the chip is facilitated.

Drawings

Fig. 1 is a schematic structural diagram of a chip package structure according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a chip package structure according to another embodiment of the present invention.

Detailed Description

In the following, the embodiments of the present invention will be described in detail with reference to the accompanying drawings, and obviously, the described embodiments are only some embodiments, not all embodiments, of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

The utility model provides a chip package structure, refer to fig. 1, this chip package structure includes PCB base plate 10, chip wafer 20 and packaging layer 30, and PCB base plate 10's front is equipped with the installation position that is used for installing chip wafer 20, and installation position department is equipped with copper layer 40 and silver thick liquid layer 50 in proper order, and on chip wafer 20 pasted and located silver thick liquid layer 50, chip wafer 20's surface covers there is packaging layer 30.

Referring to fig. 1, the chip package structure provided in this embodiment is sequentially disposed from bottom to top as a PCB substrate 10, a copper layer 40, a silver paste layer 50, a chip wafer 20, and a package layer 30. The PCB substrate 10 is divided into a mounting position for mounting the chip wafer 20, a mounting space is provided at a position corresponding to the mounting position at the bottom of the package layer 30, and the package layer 30 is attached to the PCB to package components such as the chip wafer 20 in the mounting space. Preferably, the encapsulating layer 30 is an epoxy layer. The copper layer 40 is disposed at the mounting position of the PCB substrate 10, and the silver paste layer 50 is laid on the copper layer 40, it can be known that the silver paste is a viscous paste of a mechanical mixture composed of particles of high-purity metallic silver, an adhesive, a solvent, and an auxiliary agent, and the silver paste layer 50 of the embodiment is used for fixing the chip wafer 20 and also has a heat conduction function of conducting heat of the chip wafer 20 to the copper layer 40. In addition, copper is selected as the heat transfer layer of the base layer, so that the heat conduction performance is better, and the manufacturing cost is low.

In the chip package structure, the heat transfer path includes the chip wafer 20, the silver paste layer 50, the copper layer 40, and the PCB substrate 10 in sequence, and is finally dissipated to the external environment. Compared with the prior art, the chip packaging structure has high heat dissipation efficiency, can reduce thermal resistance in the package, and improves the reliability and stability of the product; and the design of a redundant heat dissipation structure is reduced without an external heat dissipation structure (such as a heat conduction silica gel sheet and a heat dissipation shell), so that the miniaturization development of the chip is facilitated.

In a preferred embodiment, referring to fig. 1, a plurality of solder balls 60 are disposed on the bottom of the PCB substrate 10. The solder ball 60 has two functions: the heat dissipation structure is used for welding and fixing the PCB substrate 10 on the system mainboard, and can transfer the heat of the PCB substrate 10 to the system mainboard to accelerate the heat dissipation speed of the chip. The solder balls 60 may be uniformly distributed on the bottom of the PCB substrate 10 to achieve uniform heat conduction and improve soldering balance of the PCB. The number of solder balls 60 may be set according to practical situations, and is not limited herein.

Further, referring to fig. 1, the PCB substrate 10 is provided with a plurality of ground holes 1 penetrating through the front and back surfaces thereof and located below the copper layer 40. Specifically, ground holes 1 penetrate through the front and back surfaces of the PCB substrate 10, and the ground holes 1 are located under the copper layer 40 for diffusing heat of the copper layer 40. Through the ground holes 1, the heat of the copper layer 40 can be quickly transferred to the bottom surface of the PCB substrate 10 and the solder balls 60, thereby accelerating the transfer to the system mainboard and further improving the heat dissipation efficiency of the chip. The number of the ground holes 1 can be set according to practical situations, and is not limited herein.

In a preferred embodiment, referring to fig. 2, the silver paste layer 50 has four edges protruding upward to form a surrounding portion 51 attached to the side of the chip wafer 20. Silver thick liquid layer 50 adopts above-mentioned setting, through enclosing the side that closes portion 51 laminating chip wafer 20, enlarges chip wafer 20 and silver thick liquid layer 50 area of contact, and heat transfer area increases promptly helps the produced thermal quick dissipation of chip wafer 20.

In a preferred embodiment, referring to fig. 1, the area of the silver paste layer 50 is the same as the area of the chip wafer 20, and the area of the copper layer 40 is larger than the area of the chip wafer 20. In this embodiment, the area of the silver paste layer 50 is the same as the area of the chip wafer 20, so that the chip wafer 20 can be bonded firmly, the chip shape of the chip wafer 20 is ensured, the contact area between the bottom of the chip wafer 20 and the silver paste layer 50 is maximized, and the heat dissipation efficiency can be improved.

And the area of the copper layer 40 is larger than that of the chip wafer 20, and the copper layer 40 is not in contact with the wiring sites on the PCB substrate 10, so that a sufficient heat dissipation transfer area can be ensured.

In a preferred embodiment, referring to fig. 1 and 2, the PCB substrate 10 has a plurality of conductive pads 70 circumferentially arranged along the mounting site, and the chip wafer 20 is connected to the plurality of conductive pads 70 through wires. The chip wafer 20 and the conductive pads 70 are connected by wires to electrically connect with the system motherboard through the conductive pads 70. Referring to fig. 1, the leads are shaped like an airfoil, and the conductive paths between the chip wafer 20 and the conductive pads 70 are short, and have low self-inductance and wiring resistance in the package, and excellent electrical properties.

In a preferred embodiment, referring to fig. 2, the front surface of the PCB substrate 10 is provided with a plurality of blind holes 2 under the copper layer 40, and the copper layer 40 includes a copper filling portion penetrating into the blind holes 2. The blind holes 2 can be tapered holes, and the number and the positions of the blind holes 2 correspond to the copper filling parts of the copper layer 40 one by one, and can be set according to actual conditions. The copper filling part of the copper layer 40 penetrates into the blind hole 2, the contact area between the copper layer 40 and the PCB substrate 10 is increased, the heat transfer area between the copper layer 40 and the PCB substrate 10 can be enlarged, and the heat transfer speed from the copper layer 40 to the PCB substrate 10 is increased. Wherein, the more the quantity of blind hole 2 is, the better the radiating effect.

The utility model discloses further provide a memory, this memory include mainboard and chip package structure, and chip package structure sets up on the mainboard, and chip package structure's concrete structure refers to above-mentioned embodiment, because this memory has adopted all technical scheme of above-mentioned all embodiments, consequently has all technical effect that the technical scheme of above-mentioned embodiment brought at least, no longer gives unnecessary details one by one here.

The above is only the part or the preferred embodiment of the present invention, no matter the characters or the drawings can not limit the protection scope of the present invention, all under the whole concept of the present invention, the equivalent structure transformation performed by the contents of the specification and the drawings is utilized, or the direct/indirect application in other related technical fields is included in the protection scope of the present invention.

Claims

1. The chip packaging structure is characterized by comprising a PCB substrate, a chip wafer and a packaging layer, wherein the front surface of the PCB substrate is provided with a mounting position for mounting the chip wafer, a copper layer and a silver paste layer are sequentially arranged at the mounting position, the chip wafer is attached to the silver paste layer, and the packaging layer covers the outer surface of the chip wafer.

2. The chip package structure of claim 1, wherein the bottom of the PCB substrate is provided with a plurality of solder balls.

3. The chip package structure of claim 2, wherein the PCB substrate has a plurality of ground vias formed through the front and back surfaces thereof and located under the copper layer.

4. The chip package structure according to claim 1, wherein four side edges of the silver paste layer are raised upwards to form a surrounding portion attached to the side edge of the chip wafer.

5. The chip package structure according to claim 1, wherein an area of the silver paste layer is the same as an area of the chip wafer, and an area of the copper layer is larger than an area of the chip wafer.

6. The chip package structure according to claim 1, wherein the PCB substrate has a plurality of conductive pads circumferentially arranged along the mounting sites, and the chip wafer is connected to the plurality of conductive pads through leads.

7. The chip package structure according to claim 1, wherein the front surface of the PCB substrate is provided with a plurality of blind holes under the copper layer, and the copper layer includes a copper filling portion penetrating into the blind holes.

8. A memory comprising a motherboard and the chip package structure of any of claims 1-7, the chip package structure disposed on the motherboard.