CN210927079U - Fault protection circuit of motor controller - Google Patents
Fault protection circuit of motor controller Download PDFInfo
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- CN210927079U CN210927079U CN201922354709.2U CN201922354709U CN210927079U CN 210927079 U CN210927079 U CN 210927079U CN 201922354709 U CN201922354709 U CN 201922354709U CN 210927079 U CN210927079 U CN 210927079U
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Abstract
The utility model relates to an electronic circuit technical field provides a machine controller's fault protection circuit. Motor controller's fault protection circuit include: the fault signal processing circuit is used for outputting a first level signal with low level and a second level signal with high level when the fault signal is not received, and outputting the first level signal with high level and the second level signal with low level when the fault signal is received; the PWM control circuit is used for controlling the motor to normally operate and outputting the PWM signal to the drive plate when a first level signal of a low level and a second level signal of a high level are reached, and controlling the motor to stop operating and outputting the level signal to the drive plate when the first level signal of the high level and the second level signal of the low level are received. The utility model discloses can detect the trouble of electric drive system and then protect with lower cost of labor and material cost.
Description
Technical Field
The utility model relates to an electronic circuit technical field, in particular to machine controller's fault protection circuit.
Background
As the heart of an electric automobile, an electric drive system plays a crucial role. The motor controller plays an important role as a core part of an electric drive system. However, electric drive systems can fail during operation, and therefore fault detection circuits are currently designed into motor controllers. The existing fault detection circuit generally uses a programmable logic device, the program is complex, a large amount of time and manpower are needed for code editing, the cost of the programmable logic device is high, and a peripheral circuit is needed for supporting when the programmable logic device is used.
SUMMERY OF THE UTILITY MODEL
In view of this, the present invention is directed to a fault protection circuit for a motor controller, which detects faults of an electric drive system and then protects the electric drive system with low labor cost and material cost.
In order to achieve the above purpose, the technical scheme of the utility model is realized like this:
a fault protection circuit for a motor controller, the fault protection circuit comprising: the fault signal processing circuit is used for outputting a first level signal with a low level and a second level signal with a high level when the fault signal is not received, and outputting the first level signal with the high level and the second level signal with the low level when the fault signal is received; the PWM control circuit is connected with the fault signal processing circuit and used for controlling the motor to normally operate and outputting a PWM signal to the drive plate when receiving a first level signal with a low level and a second level signal with a high level, and controlling the motor to stop operating and outputting a level signal to the drive plate when receiving the first level signal with the high level and the second level signal with the low level.
Further, the fault protection circuit further includes: and the fault latch circuit is connected with the micro control unit and used for latching fault signals and sending the latched fault signals to the micro control unit and the fault signal processing circuit.
Further, the fault signal processing circuit includes: the device comprises a PWM wave generating circuit and a trigger circuit, wherein the PWM wave generating circuit is used for generating PWM waves when the fault signal is received; the trigger circuit is used for outputting a first level signal with a low level and a second level signal with a high level when the PWM wave is not received, and outputting the first level signal with the high level and the second level signal with the low level when the PWM wave is received.
Further, the PWM wave generating circuit includes: the first AND gate is used for receiving the level signal and the fault signal output by the comparator, outputting a high level signal when the level signal and the fault signal output by the comparator are both high level, and outputting a low level signal when one of the level signal and the fault signal output by the comparator is a low level signal; the first capacitor is used for charging when the first AND gate outputs a high level signal and discharging when the first AND gate outputs a low level signal; the comparator is used for outputting a low level signal when the voltage of the first capacitor is greater than a preset voltage, and outputting a high level signal when the voltage of the first capacitor is less than the preset voltage.
Further, the PWM control circuit includes: the motor comprises a first buffer and a second buffer, wherein the first buffer and the second buffer are connected between a driving plate and the motor and are used for being switched on to enable the motor to normally operate when receiving a first level signal with a low level and being switched off to enable the motor to stop operating when receiving the first level signal with a high level.
Further, the PWM control circuit further includes: and the third buffer and the fourth buffer are used for being switched off when receiving the second level signal with high level and being switched on when receiving the second level signal with low level.
Further, the fault signal processing circuit further includes: and the fault reset circuit is connected with the micro control unit and is used for sending a reset signal when receiving a reset instruction of the micro control unit.
Further, the PWM control circuit further includes: and the logic gate group circuit is connected with the third buffer and the fourth buffer, and is used for receiving a fault signal of the driving board and a protection signal output by the micro control unit and outputting different combined level signals.
Further, when the upper bridge and the lower bridge of the driving board have no fault, the fault signal of the driving board is a low level signal, and when the upper bridge and the lower bridge of the driving board have a fault, the fault signal of the driving board is a high level signal.
Further, when the rotating speed of the motor is greater than or equal to a threshold value, the protection signal output by the micro control unit is a high level signal, and when the rotating speed of the motor is less than the threshold value, the protection signal output by the micro control unit is a low level signal.
Compared with the prior art, motor controller's fault protection circuit have following advantage:
adopting a fault signal processing circuit and a PWM control circuit, wherein the fault signal processing circuit is used for outputting a first level signal with low level and a second level signal with high level when not receiving a fault signal, and outputting the first level signal with high level and the second level signal with low level when receiving the fault signal; the PWM control circuit is connected with the fault signal processing circuit and used for controlling the motor to normally operate and outputting a PWM signal to the drive plate when receiving a first level signal with a low level and a second level signal with a high level, and controlling the motor to stop operating and outputting a level signal to the drive plate when receiving the first level signal with the high level and the second level signal with the low level. Because the utility model discloses all use comparatively common circuit device to realize detecting and protecting, do not need programming and peripheral circuit to lower cost of labor and material cost detect electric drive system's trouble and then protect.
Other features and advantages of the present invention will be described in detail in the detailed description which follows.
Drawings
The accompanying drawings, which form a part hereof, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention without undue limitation. In the drawings:
fig. 1 is a logic block diagram of a fault protection circuit of a motor controller according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a fault latch circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a fault signal processing circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a PWM control circuit according to an embodiment of the present invention.
Description of reference numerals:
1 fault signal processing circuit 2 PWM control circuit
Detailed Description
In the present invention, the embodiments and the features of the embodiments may be combined with each other without conflict.
The present invention will be described in detail with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1 is a logic block diagram of a fault protection circuit of a motor controller according to an embodiment of the present invention. As shown in fig. 1, the fault protection circuit includes:
a fault signal processing circuit 1 and a PWM control circuit 2, wherein the fault signal processing circuit 1 is configured to output a first level signal of a low level and a second level signal of a high level when a fault signal is not received, and output the first level signal of the high level and the second level signal of the low level when the fault signal is received; the PWM control circuit 2 is connected to the fault signal processing circuit 1, and is configured to control the motor to normally operate and output a PWM signal to the drive board when receiving the first low-level signal and the second high-level signal, and control the motor to stop operating and output a level signal to the drive board when receiving the first high-level signal and the second low-level signal.
The embodiment of the utility model provides an in, fault signal can be detected by little the control Unit (MCU), for example include the overcurrent signal of three phase current, low voltage battery's undervoltage signal, the overvoltage signal of high voltage direct current power, the upper bridge drive fault signal on the drive plate and the lower bridge drive fault signal on the drive plate etc.. It is preferable that the fault signal is a high-level signal, that is, the fault signal processing circuit 1 judges that the fault signal is received when receiving the high-level signal.
In addition, because fault signal's live time is very short, consequently the utility model discloses still set up trouble latch circuit, be connected with little the control Unit (MCU) for receive and latch fault signal, and send the fault signal who latches to MCU and fault signal processing circuit 1.
Through the fault signal processing circuit 1 and the PWM control circuit 2, when the electric drive system has a fault, a fault signal can be detected and an open circuit control strategy can be executed so as to control the motor to stop running, and a level signal is output to a drive plate to keep driving so as to protect the electric drive circuit. The specific structure and components of the fault protection circuit of the motor controller will be described in detail below by way of example.
Fig. 2 is a schematic diagram of a fail latch circuit according to an embodiment of the present invention. As shown in FIG. 2, A14-A18 are Fault signal latches for latching Fault signals, A19-A23 are inverters, and Fault1, Fault2, Fault3, HS-DF and LS-DF all represent initial Fault signals, for example LS-DF and HS-DF represent initial drive Fault signals of upper and lower bridges of a drive board. While Fault1-latch, Fault2-latch, Fault3-latch, HS-DF-latch and LS-DF-latch are latched Fault signals.
Fig. 3 is a schematic diagram of a fault signal processing circuit according to an embodiment of the present invention. As shown in fig. 3, the fault signal processing circuit 1 includes:
a fault detection circuit, a fault reset circuit, a PWM wave generation circuit, and a flip-flop circuit, wherein, specifically,
the Fault detection circuit comprises a diode (such as a schottky diode) D5-D9, a Fault1-Latch passes through a schottky diode D5, a Fault2-Latch passes through a schottky diode D6, a Fault3-Latch passes through a schottky diode D7, an HS-DF-Latch passes through a schottky diode D8, and an LS-DF-Latch passes through a schottky diode D9, wherein the number of the Schottky diodes can be adjusted at any time, and the invention is not limited.
The fault reset circuit is connected with the MCU and used for sending a reset signal when receiving a reset instruction (MCU-CTR) of the MCU, namely the MCU-CTR sends a reset signal RST-DF through the AND gate A4. The MCU-CTR signal is connected to ground through a resistor R3, and a resistor R3 is also connected to one end of a capacitor C1. The other end of the capacitor C1 is connected with a resistor R4.
The PWM wave generating circuit is used for generating a PWM wave when receiving the Fault signal (namely any one of Fault1-Latch, Fault2-Latch, Fault3-Latch, HS-DF-Latch and LS-DF-Latch). The PWM wave generating circuit mainly includes: a first and gate a1, a first capacitor C3 and a comparator U3, wherein the first and gate a1 is configured to receive the level signal output by the comparator U3 and the fault signal, output a high level signal when both the level signal output by the comparator U3 and the fault signal are high level, and output a low level signal when one of the level signal output by the comparator U3 and the fault signal is a low level signal; the first capacitor C3 is used for charging when the first and gate a1 outputs a high level signal and discharging when the first and gate a1 outputs a low level signal; the comparator U3 is used for outputting a low level signal when the voltage of the first capacitor C3 is greater than a preset voltage, and outputting a high level signal when the voltage of the first capacitor C3 is less than the preset voltage. Specifically, cathodes of diodes D5-D9 are connected in parallel and then connected to an input end of an AND gate A1, one end of a resistor R2 and an anode of a Schottky diode D1 are connected in parallel and then connected between a capacitor C2 and a capacitor R7, and resistors R9, R10 and R11 form a hysteresis adjusting circuit of a comparator U3. The output end of the first and gate a1 is connected with a resistor R8, a resistor R8 is connected with the inverting input terminal INN of the comparator U3, the output end of the first and gate a1 is further connected with one end of a capacitor C2, and the other end of the capacitor C2 is connected with a resistor R7. The resistor R8 and the capacitor C3 form a charge-discharge circuit of the capacitor. With the above structure, when a fault signal occurs, the fault signal input at the input terminal of the first and gate a1 is at a high level, the output terminal of the comparator U3 is also at a high level, at this time, the first capacitor C3 is charged first, then the level of the output terminal of the comparator U3 is inverted (output low level), the output terminal of the first and gate a1 outputs a low level, the first capacitor C3 also becomes discharged, and such processes are alternated, so that a PWM wave is generated.
The flip-flop circuit is configured to output a first level signal/OE 1 of a low level and a second level signal/OE 2 of a high level when the PWM wave is not received, and output a first level signal/OE 1 of a high level and a second level signal/OE 2 of a low level when the PWM wave is received. Specifically, the PRE terminal of the flip-flop a2 is connected to the resistor R4, the CLR terminal is connected to the resistor R7, the two pins D and CLK of the flip-flop a2 are pulled up to the cathodes of the schottky diodes D3 and D4 through the resistor R5, the level states of the two pins are fixed to a high level, and the state of the flip-flop is determined by mainly switching the states of the pin PRE and the pin CLR to determine whether the flip-flop operates. VCC1 and VCC2 are connected to the power supply port of flip-flop A2 via Schottky diodes D3, D4 as a backup for dual power supplies. One end of the resistor R1 is connected in parallel with the cathode of the Schottky diode D2 and then connected to the cathodes of the Schottky diodes D3 and D4, and the other end of the resistor R1 is connected in parallel with the anode of the Schottky diode D2 and then connected between the capacitors C1 and R4. One end of the resistor R2 is connected in parallel with the cathode of the schottky diode D1 and then connected to the cathodes of the schottky diodes D3 and D4. The signal/OE 2 generated at the Q pin of flip-flop a2 generates the/OE 1 signal through inverter A3, the two signals being at opposite levels.
Fig. 4 is a schematic diagram of a PWM control circuit according to an embodiment of the present invention. As shown in fig. 4, the PWM control circuit 2 includes:
a first buffer S1 and a second buffer S2, wherein the first buffer S1 and the second buffer S2 are connected between the driving board and the motor, and are turned on to enable the motor to normally operate when receiving the first level signal/OE 1 of low level, and turned off to disable the motor when receiving the first level signal/OE 1 of high level. Specifically, the three-phase pulse width modulation signal XH-PWM converts the signal into XH-PWM-BUF through the first buffer S1 to be transmitted to the drive board, the XH-PWM-BUF is connected to the ground through the resistor R12, XL-PWM converts the signal into XL-PWM-BUF through the second buffer S2 to be transmitted to the drive board, and the XL-PWM-BUF signal is connected to the ground through the resistor R13.
The third buffer S3 and the fourth buffer S4 are turned off when receiving the second level signal/OE 2 of a high level and turned on when receiving the second level signal/OE 2 of a low level. Specifically, a level signal may be transmitted to the XH-PWM-BUF and onto the driving board through the third buffer S3, and another level signal may be transmitted to the XL-PWM-BUF and onto the driving board through the third buffer S4.
And a logic gate group circuit connected to the third buffer S3 and the fourth buffer S4, for receiving the fault signals (LS-DF-Latch and HS-DF-Latch) of the driving boards and the protection signal (MCU-SPO/ASC) output from the MCU, and outputting different combined level signals. Specifically, when the upper bridge and the lower bridge of the drive board have no fault, the fault signal of the drive board is a low-level signal, and when the upper bridge and the lower bridge of the drive board have a fault, the fault signal of the drive board is a high-level signal. When the rotating speed of the motor is greater than or equal to the threshold value, the protection signal output by the MCU is a high level signal, and when the rotating speed of the motor is less than the threshold value, the protection signal output by the MCU is a low level signal.
In the logic gate group circuit, an MCU-SPO/ASC signal and an LS-DF-Latch signal are used as input of an AND gate A5, the MCU-SPO/ASC signal and an HS-DF-Latch signal are used as input of an AND gate A12, the LS-DF-Latch signal is connected with an anode of a diode D10, the HS-DF-Latch signal is connected with an anode of a diode D11, cathodes of diodes D10 and D11 are connected in parallel and then pass through an inverter A13, an output of an inverter A13 and the MCU-SPO/ASC signal are used as input of an AND gate A11, output ends of the AND gates A5 and A12 are connected to an input end of an XOR gate A7, an output end of the AND gate A5 and an output end of the XOR gate A7 are used as input signals of an AND gate A6, and an output end of an XOR gate A12 and an output end of an XOR gate A7 are used as input signals of. Through a logic gate group circuit, three high level signals and three low level signals can be output or six low level signals can be output to enable the driving plate to work normally according to different levels of LS-DF-Latch, HS-DF-Latch and MCU-SPO/ASC.
The invention adopts a fault signal processing circuit 1 and a PWM control circuit 2, wherein the fault signal processing circuit 1 is used for outputting a first level signal with low level and a second level signal with high level when a fault signal is not received, and outputting the first level signal with high level and the second level signal with low level when the fault signal is received; the PWM control circuit 2 is connected to the fault signal processing circuit 1, and is configured to control the motor to normally operate and output a PWM signal to the drive board when receiving the first low-level signal and the second high-level signal, and control the motor to stop operating and output a level signal to the drive board when receiving the first high-level signal and the second low-level signal. Because the utility model discloses all use comparatively common circuit device to realize detecting and protecting, do not need programming and peripheral circuit to lower cost of labor and material cost detect electric drive system's trouble and then protect.
The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A fault protection circuit for a motor controller, the fault protection circuit comprising:
a fault signal processing circuit and a PWM control circuit, wherein,
the fault signal processing circuit is used for outputting a first level signal with low level and a second level signal with high level when a fault signal is not received, and outputting the first level signal with high level and the second level signal with low level when the fault signal is received;
the PWM control circuit is connected with the fault signal processing circuit and used for controlling the motor to normally operate and outputting a PWM signal to the drive plate when receiving a first level signal with a low level and a second level signal with a high level, and controlling the motor to stop operating and outputting a level signal to the drive plate when receiving the first level signal with the high level and the second level signal with the low level.
2. The fault protection circuit of a motor controller of claim 1, further comprising:
and the fault latch circuit is connected with the micro control unit and used for latching fault signals and sending the latched fault signals to the micro control unit and the fault signal processing circuit.
3. The fault protection circuit of a motor controller according to claim 1, wherein said fault signal processing circuit comprises:
a PWM wave generating circuit and a flip-flop circuit, wherein,
the PWM wave generating circuit is used for generating PWM waves when the fault signals are received;
the trigger circuit is used for outputting a first level signal with a low level and a second level signal with a high level when the PWM wave is not received, and outputting the first level signal with the high level and the second level signal with the low level when the PWM wave is received.
4. The fault protection circuit of a motor controller according to claim 3, wherein the PWM wave generating circuit includes:
a first AND gate, a first capacitor and a comparator, wherein,
the first AND gate is used for receiving the level signal and the fault signal output by the comparator, outputting a high level signal when the level signal and the fault signal output by the comparator are both high level, and outputting a low level signal when one of the level signal and the fault signal output by the comparator is a low level signal;
the first capacitor is used for charging when the first AND gate outputs a high level signal and discharging when the first AND gate outputs a low level signal;
the comparator is used for outputting a low level signal when the voltage of the first capacitor is greater than a preset voltage, and outputting a high level signal when the voltage of the first capacitor is less than the preset voltage.
5. The fault protection circuit of a motor controller according to claim 1, wherein the PWM control circuit comprises:
a first buffer and a second buffer, wherein,
the first buffer and the second buffer are connected between the driving plate and the motor and are used for conducting to enable the motor to normally operate when receiving a first level signal of a low level and conducting to disable the motor to stop operating when receiving the first level signal of a high level.
6. The fault protection circuit of a motor controller according to claim 1, wherein the PWM control circuit further comprises:
and the third buffer and the fourth buffer are used for being switched off when receiving the second level signal with high level and being switched on when receiving the second level signal with low level.
7. The fault protection circuit of a motor controller according to claim 1, wherein the fault signal processing circuit further comprises:
and the fault reset circuit is connected with the micro control unit and is used for sending a reset signal when receiving a reset instruction of the micro control unit.
8. The fault protection circuit of a motor controller of claim 6, wherein said PWM control circuit further comprises:
and the logic gate group circuit is connected with the third buffer and the fourth buffer, and is used for receiving a fault signal of the driving board and a protection signal output by the micro control unit and outputting different combined level signals.
9. The fault protection circuit of a motor controller according to claim 8, wherein the fault signal of the driving board is a low level signal when the driving board upper and lower bridges have no fault, and the fault signal of the driving board is a high level signal when the driving board upper and lower bridges have a fault.
10. The fault protection circuit of claim 8, wherein the protection signal output by the micro control unit is a high level signal when the rotation speed of the motor is greater than or equal to a threshold value, and the protection signal output by the micro control unit is a low level signal when the rotation speed of the motor is less than the threshold value.
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| CN201922354709.2U CN210927079U (en) | 2019-12-24 | 2019-12-24 | Fault protection circuit of motor controller |
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| CN201922354709.2U CN210927079U (en) | 2019-12-24 | 2019-12-24 | Fault protection circuit of motor controller |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114285001A (en) * | 2021-12-31 | 2022-04-05 | 蜂巢传动科技河北有限公司 | Vehicle motor control system and method |
| CN114895659A (en) * | 2022-07-13 | 2022-08-12 | 东方博沃（北京）科技有限公司 | Fault detection circuit and detection method thereof |
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2019
- 2019-12-24 CN CN201922354709.2U patent/CN210927079U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114285001A (en) * | 2021-12-31 | 2022-04-05 | 蜂巢传动科技河北有限公司 | Vehicle motor control system and method |
| CN114285001B (en) * | 2021-12-31 | 2024-01-26 | 蜂巢传动科技河北有限公司 | Vehicle motor control system and method |
| CN114895659A (en) * | 2022-07-13 | 2022-08-12 | 东方博沃（北京）科技有限公司 | Fault detection circuit and detection method thereof |
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Effective date of registration: 20210625 Address after: 071000 in No.75 Dongsheng Road, Lianchi District, Baoding City, Hebei Province Patentee after: Baoding R & D branch of honeycomb transmission system (Jiangsu) Co.,Ltd. Address before: 071000 No.75 Dongsheng Road, Lianchi District, Baoding City, Hebei Province Patentee before: Beehive electric drive technology Hebei Co.,Ltd. |