CN210925443U - Substrate wiring structure and display device thereof - Google Patents
Substrate wiring structure and display device thereof Download PDFInfo
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- CN210925443U CN210925443U CN202020219724.6U CN202020219724U CN210925443U CN 210925443 U CN210925443 U CN 210925443U CN 202020219724 U CN202020219724 U CN 202020219724U CN 210925443 U CN210925443 U CN 210925443U
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Abstract
The utility model discloses a substrate wiring structure, two sub-pixels adjacent in the same row are not connected with the same scanning line, and each data line is connected with two rows of sub-pixels adjacent to the data line simultaneously; the display area comprises a first display area and a second display area which are opposite along the transverse direction, and the data lines comprise a plurality of first data lines positioned in the first display area and a plurality of second data lines positioned in the second display area; and the source driving wire leads out one of the first data wire and the second data wire which are connected together to the source binding area. The substrate wiring structure can reduce the number of output channels of the source driver or reduce the using number of the source driver, and the cost is lower. The utility model also discloses a display device.
Description
Technical Field
The utility model relates to a display technology especially relates to a base plate wiring structure and display device thereof.
Background
With the vigorous development of the photoelectric display industry, cost reduction and cost performance improvement are effective methods for enhancing the competitiveness of display panels. In the display panel source driver selection, there are some source drivers that support a smaller number of output channels than the required number of channels (number of data lines) of the display panel, especially in the medium-sized and large-sized panels, and it is conventional to select a source driver with a larger number of output channels, and in addition, the method of increasing the number of source drivers is not suitable for the display panel, which leads to the cost increase of the display panel.
SUMMERY OF THE UTILITY MODEL
In order to solve the deficiencies of the prior art, the utility model provides a substrate wiring structure, the output channel quantity of reducible source driver or the use quantity that reduces the source driver, the cost is lower. The utility model also provides a display device.
The utility model discloses the technical problem that will solve realizes through following technical scheme:
a substrate wiring structure comprises a display area and a peripheral area, wherein a source binding area and a plurality of source driving wires are arranged in the peripheral area, a plurality of scanning lines which are wired along the transverse direction, a plurality of data lines which are wired along the longitudinal direction and a sub-pixel array which is distributed in a vertical and horizontal grid formed by the scanning lines and the data lines in a staggered mode in a dot matrix mode are arranged in the display area, and each sub-pixel in the sub-pixel array is electrically connected with the corresponding scanning line and the corresponding data line through a corresponding TFT switch; two adjacent sub-pixels in the same row are not connected with the same scanning line, and each data line is simultaneously connected with two adjacent columns of sub-pixels; the display area comprises a first display area and a second display area which are opposite along the transverse direction, and the data lines comprise a plurality of first data lines positioned in the first display area and a plurality of second data lines positioned in the second display area; the source driving line leads out one of the first data line and the second data line which are connected together to the source binding area.
Furthermore, two scanning lines are arranged between two adjacent rows of sub-pixels.
Furthermore, two columns of sub-pixels are arranged between two adjacent data lines.
Further, the connecting line is located on a side away from the source binding region.
Further, the first data line and the second data line connected together are symmetrical with respect to a longitudinal central axis between the first display region and the second display region.
Furthermore, a gate binding area/gate driving area and a plurality of gate driving lines are also arranged in the peripheral area, and the gate driving lines lead out corresponding scanning lines to the gate binding area/gate driving area.
Further, the scan lines are disconnected to form first scan lines located in the first display region and second scan lines located in the second display region.
Furthermore, a first gate binding area/a first gate driving area and a second gate binding area/a second gate driving area are further arranged in the peripheral area, and a plurality of gate driving lines lead out first scanning lines located in the first display area to the first gate binding area/the first gate driving area and second scanning lines located in the second display area to the second gate binding area/the second gate driving area.
Further, a first data line and a second data line which are connected together are partially connected with the source driving line by the first data line to be led out to the source binding region, and are partially connected with the source driving line by the second data line to be led out to the source binding region; or the first data line and the second data line which are connected together are all connected with the source driving line through the first data line to be led out to the source binding area, or are all connected with the source driving line through the second data line to be led out to the source binding area.
A display device comprises the substrate wiring structure. A display device comprises the substrate wiring structure.
The utility model discloses following beneficial effect has: the wiring structure of the substrate not only adopts a double-gate structure to carry out wiring, reduces the usage amount of the data lines to a half, but also divides the display area into a first display area and a second display area, correspondingly connects the first data lines in the first display area and the second data lines in the second display area together one by one through the connecting lines, leads the first data lines and the second data lines which are connected together to the source binding area by sharing the same source driving line, receives display signals by sharing the same source driving line, can reduce the number of output channels of a source driver or the number of the source drivers, and achieves the purpose of reducing the production cost; although the dual gate structure increases the number of scan lines, the cost of the gate driver or gate driving circuit is lower than that of the source driver, and the cost of the source driver is reduced more than that of the increased gate driver or gate driving circuit, so that the overall cost is reduced.
Drawings
Fig. 1 is a schematic diagram of a substrate wiring structure provided by the present invention;
fig. 2 is a schematic diagram of another substrate wiring structure provided by the present invention;
fig. 3 is a schematic diagram of another substrate wiring structure provided in the present invention;
fig. 4 is a schematic view of another substrate wiring structure provided by the present invention.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings and examples.
Example one
As shown in fig. 1 to 4, a substrate wiring structure includes a display area and a peripheral area, wherein the peripheral area is provided with a source bonding area 21 and a plurality of source driving lines 22, the display area is provided with a plurality of scanning lines 11 running along a transverse direction, a plurality of data lines running along a longitudinal direction, and a sub-pixel array distributed in a crisscross grid formed by the scanning lines 11 and the data lines in a dot matrix, and each sub-pixel 4 in the sub-pixel array is electrically connected to the corresponding scanning line 11 and the corresponding data line through a corresponding TFT switch; two adjacent sub-pixels 4 in the same row are not connected to the same scanning line 11, and each data line is simultaneously connected to two adjacent columns of sub-pixels 4; the display area includes a first display area and a second display area which are opposite in a transverse direction, and the data lines include a plurality of first data lines 121 located in the first display area and a plurality of second data lines 122 located in the second display area; and a plurality of connecting lines 3, wherein the connecting lines 3 electrically connect the first data lines 121 and the second data lines 122 in a one-to-one correspondence, and the source driving line 22 leads one of the first data lines 121 and the second data lines 122 connected together to the source bonding region 21.
The wiring structure of the substrate not only adopts a double-gate structure to carry out wiring, reduces the usage amount of the data lines to half, but also divides the display area into a first display area and a second display area, the first data lines 121 positioned in the first display area and the second data lines 122 positioned in the second display area are correspondingly connected together one by one through the connecting lines 3, the first data lines 121 and the second data lines 122 which are connected together share the same source driving line 22 and are led out to the source binding area 21, and the same source driving line 22 is shared to receive display signals, so that the number of output channels of a source driver can be reduced or the usage amount of the source driver can be reduced, and the purpose of reducing the production cost can be achieved; although the dual gate structure increases the number of the scan lines 11, the cost of the gate driver or the gate driving circuit is lower than that of the source driver, and the cost of the source driver is reduced more than that of the increased gate driver or the increased gate driving circuit, so that the overall cost is reduced.
If the number of the data lines is odd, the most middle data line is drawn out to the source driving region 21 through the source driving line 22 alone, which may be regarded as either the first data line 121 or the second data line 122, or neither the first data line 121 nor the second data line 122.
Besides that one scanning line 11 is separately arranged on the other side of the first row of sub-pixels 4, and one scanning line 11 is also separately arranged on the other side of the last row of sub-pixels 4, two scanning lines 11 are arranged between two adjacent rows of sub-pixels 4, and two columns of sub-pixels 4 are arranged between two adjacent data lines (i.e. two columns of sub-pixels 4 are arranged between two adjacent first data lines 121 in the first display area, and two columns of sub-pixels 4 are also arranged between two adjacent second data lines 122 in the second display area).
The source bonding region 21 is used to bond a source FPC and a source driver, and a display signal output from the source driver is simultaneously transmitted to the first data line 121 and the second data line 122 connected together through the source driving line 22.
Optionally, the connecting line 3 is preferably disposed in the peripheral region and is optimally located on a side away from the source binding region 21, and without affecting the display, the connecting line 3 is not excluded from being disposed in the display region and is also optimally located on a side away from the source binding region 21.
In one embodiment, as shown in fig. 1 and 2, the first data line 121 and the second data line 122 connected together are symmetrical with respect to a longitudinal central axis between the first display region and the second display region.
In this embodiment, a gate bonding area/gate driving area 23 and a plurality of gate driving lines 24 are further disposed in the peripheral area, and the gate driving lines 24 lead out corresponding scanning lines 11 to the gate bonding area/gate driving area 23; the gate binding region/gate driving region 23 is preferably located at a side adjacent to the source binding region 21, the gate binding region being used to bind a gate FPC and a gate driver, and a scan signal output from the gate driver is transmitted to the scan line 11 through the gate driving line 24; a gate driver circuit (GOA) is formed on the gate driving region 23 to replace the scan signal output by the externally-hung gate driver.
In this embodiment, when all the sub-pixels 4 connected to a scan line 11 in the same row are turned on, only one of the two sub-pixels 4 adjacent to the same row is turned on, and the source driver outputs a display signal to the first data line 121 and the second data line 122 connected together through the source driving line 22, so that one of the two sub-pixels 4 connected to the first data line 121 in the sub-pixel 4 in the row and one of the two sub-pixels 4 connected to the second data line 122 display the same content, that is, the display frame of the first display region and the display frame of the second display region are in left-right mirror symmetry.
The substrate wiring structure in this embodiment mode can be applied to some display devices requiring mirror image display, such as electronic meal boards.
As shown in fig. 3 and 4, the scan lines 11 are disconnected to form first scan lines 111 located in the first display region and second scan lines 112 located in the second display region.
In this embodiment, a first gate bonding area/first gate driving area 231 and a second gate bonding area/second gate driving area 232 are further disposed in the peripheral area, and a plurality of gate driving lines 24 are further disposed in the peripheral area, the gate driving lines 24 lead out the first scanning lines 111 located in the first display area to the first gate bonding area/first gate driving area 231, and lead out the second scanning lines 112 located in the second display area to the second gate bonding area/second gate driving area 232; the first gate bonding region/first gate driving region 231 and the second gate bonding region/second gate driving region 232 are preferably respectively located at two sides adjacent to the source bonding region 21, the first gate bonding region is used for bonding a first gate FPC and a first gate driver, a scanning signal output by the first gate driver is transmitted to the first scanning line 111 through the gate driving line 24, the second gate bonding region is used for bonding a second gate FPC and a second gate driver, and a scanning signal output by the second gate driver is transmitted to the second scanning line 112 through the gate driving line 24; the first gate driving region 231 and the second gate driving region 232 are respectively fabricated with a first gate driving circuit (first GOA) and a second gate driving circuit (second GOA) to replace scan signals output by the first gate driver and the second gate driver of the external hanging type.
In this embodiment, the first data line 121 and the second data line 122 connected together are separately addressed and opened by the first scan line 111 and the second scan line 112, respectively, the first data line 121 in the first display region is matched with the first scan line 111 for displaying, and the second data line 122 in the second display region is matched with the second scan line 112 for displaying. When a display signal needs to be output to the sub-pixel 4 on the first data line 121, the sub-pixel 4 on the first data line 121 is turned on by the first scan line 111, the sub-pixel 4 on the second data line 122 is turned off by the second scan line 112, and when a display signal needs to be output to the sub-pixel 4 on the second data line 122, the sub-pixel 4 on the first data line 121 is turned off by the first scan line 111, and the sub-pixel 4 on the second data line 122 is turned on by the second scan line 112. In this way, the sub-pixels 4 connected to the first data line 121 and the sub-pixels 4 connected to the second data line 122 in the same row of sub-pixels 4 may display different contents, that is, the display screen of the first display region and the display screen of the second display region may be different.
The substrate wiring structure in this embodiment can be applied to a conventional display device, and since the cost of the gate driver or gate driving circuit is lower than that of the source driver, the substrate wiring structure in this embodiment increases the cost of the gate driver or gate driving circuit, but reduces the cost of the source driver more, and the overall cost is reduced.
As shown in fig. 1 and 2, the first data line 121 and the second data line 122 connected together may be all connected to the source driving line 22 by the first data line 121 to be led out to the source bonding region 21, or all connected to the source driving line 22 by the second data line 122 to be led out to the source bonding region 21; alternatively, as shown in fig. 3 and 4, the first data line 121 and the second data line 122 connected together may be partially connected to the source driving line 22 by the first data line 121 to be drawn to the source bonding region 21, and partially connected to the source driving line 22 by the second data line 122 to be drawn to the source bonding region 21.
Example two
A display device comprising the substrate wiring structure of the first embodiment.
The above-mentioned embodiments only express the embodiments of the present invention, and the description thereof is specific and detailed, but the invention can not be understood as the limitation of the patent scope of the present invention, but all the technical solutions obtained by adopting the equivalent substitution or equivalent transformation should fall within the protection scope of the present invention.
Claims (10)
1. A substrate wiring structure comprises a display area and a peripheral area, wherein a source binding area and a plurality of source driving wires are arranged in the peripheral area, a plurality of scanning lines which are wired along the transverse direction, a plurality of data lines which are wired along the longitudinal direction and a sub-pixel array which is distributed in a vertical and horizontal grid formed by the scanning lines and the data lines in a staggered mode in a dot matrix mode are arranged in the display area, and each sub-pixel in the sub-pixel array is electrically connected with the corresponding scanning line and the corresponding data line through a corresponding TFT switch; the pixel structure is characterized in that two adjacent sub-pixels in the same row are not connected with the same scanning line, and each data line is simultaneously connected with two adjacent columns of sub-pixels; the display area comprises a first display area and a second display area which are opposite along the transverse direction, and the data lines comprise a plurality of first data lines positioned in the first display area and a plurality of second data lines positioned in the second display area; the source driving line leads out one of the first data line and the second data line which are connected together to the source binding area.
2. The wiring structure of claim 1, wherein two scan lines are provided between two adjacent rows of sub-pixels.
3. The wiring structure of claim 1 or 2, wherein two columns of sub-pixels are provided between two adjacent data lines.
4. The substrate wiring structure of claim 1, wherein the connection line is located on a side away from the source bonding region.
5. The substrate wiring structure according to claim 1, wherein the first data line and the second data line connected together are symmetrical with respect to a longitudinal central axis between the first display region and the second display region.
6. The substrate wiring structure according to claim 5, wherein a gate bonding area/gate driving area and a plurality of gate driving lines are further disposed in the peripheral area, and the gate driving lines lead out corresponding scanning lines to the gate bonding area/gate driving area.
7. The substrate wiring structure according to claim 1, wherein the scan line is disconnected to form a first scan line located in the first display region and a second scan line located in the second display region.
8. The substrate wiring structure according to claim 7, wherein a first gate bonding area/a first gate driving area and a second gate bonding area/a second gate driving area are further provided in the peripheral area, and a plurality of gate driving lines lead out a first scanning line located in the first display area to the first gate bonding area/the first gate driving area and a second scanning line located in the second display area to the second gate bonding area/the second gate driving area.
9. The substrate wiring structure according to claim 1, wherein a first data line and a second data line connected together are partially connected to the source driving line by the first data line to be drawn to the source bonding region, and partially connected to the source driving line by the second data line to be drawn to the source bonding region; or the first data line and the second data line which are connected together are all connected with the source driving line through the first data line to be led out to the source binding area, or are all connected with the source driving line through the second data line to be led out to the source binding area.
10. A display device comprising the substrate wiring structure according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020219724.6U CN210925443U (en) | 2020-02-27 | 2020-02-27 | Substrate wiring structure and display device thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020219724.6U CN210925443U (en) | 2020-02-27 | 2020-02-27 | Substrate wiring structure and display device thereof |
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| Publication Number | Publication Date |
|---|---|
| CN210925443U true CN210925443U (en) | 2020-07-03 |
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| CN202020219724.6U Active CN210925443U (en) | 2020-02-27 | 2020-02-27 | Substrate wiring structure and display device thereof |
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| CN (1) | CN210925443U (en) |
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