CN210864715U - ARM core board for integrating hardware encryption - Google Patents

Abstract

The utility model provides an ARM core plate that integrated hardware encrypted, integrated have CPU and respectively with memory chip, the power chip that CPU is connected, ARM core plate that integrated hardware encrypted still integrates connector, the hardware encryption chip of being connected with CPU respectively, and CPU passes through serial ports, network interface, USB interface, IIC interface, SPI interface, GPIO interface are drawn forth to the connector. The utility model can encrypt the application software developed by users by hardware authorization, and solves the problems that the encryption measures of the existing core board are unreliable, and the encryption piece is easy to be damaged; the functional interface is led out through the connector, so that a user can quickly design main boards or products with different sizes and different interface types conveniently, the expansibility is high, and the core board is easy to disassemble and assemble.

Description

ARM core board for integrating hardware encryption

Technical Field

The utility model relates to a ARM technical field especially relates to a core plate of ARM that integrated hardware encrypted.

Background

ARM nuclear core plate variety is various, has generally all integrateed CPU, memory, storage, power, draws forth display interface, serial ports, net gape, USB interface, IIC interface, SPI interface, GPIO interface, memory card interface etc. and the diverse such as treater model, size of a dimension, connector mode, software system that different nuclear core plate adopted. The user uses the core board for secondary development, the application software needs to be encrypted and authorized, common encryption means comprise binding of a MAC address or a FlashID and using of an external dongle, but the encryption means for binding the MAC address or the FlashID are easy to break, and the external dongle is high in cost, needs to be supported by a driver and is easy to break.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model provides an ARM core plate that integrated hardware was encrypted to solve traditional ARM core plate expansibility not enough, encryption measure unreliable, the easy destroyed problem of encryption piece.

The technical scheme of the utility model is realized like this: the utility model provides an integrated hardware encryption's ARM nuclear core plate, integrated memory chip, the power chip that has CPU and be connected with CPU respectively, integrated hardware encryption's ARM nuclear plate still integrated connector, the hardware encryption chip of being connected with CPU respectively, CPU passes through serial ports, network interface, USB interface, IIC interface, SPI interface, GPIO interface are drawn forth to the connector.

Optionally, the hardware encryption chip is an RJGT102 chip.

Optionally, the number of the serial port, the network interface, the USB interface, the IIC interface, the SPI interface, and the GPIO interface is one or more.

Optionally, the connector is a board-to-board connector.

Optionally, the connectors have two.

Optionally, the connector has 80 pins.

Optionally, the connector is F30FC-80DP-0.4V type.

Optionally, the ARM core board with the encrypted integrated hardware further includes a USB interface protection circuit, where the USB interface protection circuit includes a patch magnetic bead FB, a common mode inductor L1, a TVS diode D1, a TVS diode D2, a resistor R1, a resistor R2, a varistor R3, a capacitor C1, and a capacitor C2, the patch magnetic bead FB is connected to a Vbus line of the USB interface, the Vbus line is grounded through the varistor R3, the common mode inductor L1 is connected between a D + line and a D-line of the USB interface, the D + line is grounded through the TVS diode D1, the D-line is grounded through the TVS diode D2, the resistor R1 is connected to the D + line, the resistor R2 is connected to the D-line, the D + line is grounded through the capacitor C1, and the D-line is grounded through the capacitor C2.

The utility model discloses an ARM nuclear core plate that integrated hardware encrypted has following beneficial effect for prior art:

(1) the ARM core board integrated with hardware encryption of the utility model can encrypt hardware authorization of application software developed by users, and solves the problems that the encryption measures of the existing core board are unreliable, and the encryption piece is easy to be damaged;

(2) the utility model discloses a function interface is drawn forth through the connector to the ARM core plate that integrated hardware encrypted, and the user of being convenient for designs the mainboard or the product of unidimensional, different interface kind fast, and the expansibility is strong and easy dismouting of easy core plate.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an ARM core board for integrated hardware encryption according to the present invention;

fig. 2 is a circuit diagram of the USB interface protection circuit of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work all belong to the protection scope of the present invention.

As shown in fig. 1, the utility model discloses an integrated hardware encryption's ARM nuclear core plate, integrated memory chip, the power chip that has CPU and be connected with CPU respectively, integrated hardware encryption's ARM nuclear plate still integrated connector, the hardware encryption chip of being connected with CPU respectively, CPU passes through serial ports, network interface, USB interface, IIC interface, SPI interface, GPIO interface are drawn forth to the connector.

In the embodiment, the core board integrates minimum system resources such as hardware encryption chips, CPUs, memories, storage and the like, a quad-core Cortex-A53CPU is adopted, 1.5GH major frequency is adopted, the memories support 4GB, the problem of operational performance is solved, the hardware encryption chips and the CPUs are communicated through IIC, an SHA-256 algorithm is used for encryption operation, each encryption chip has an independent chip ID, key data can be written into a designated area of the encryption chip and cannot be read out, the encryption area of the encryption chip can be locked and cannot be written in again, a user binds application software through a key written into the encryption chip, the key is verified through a verification command to judge whether the application software is authorized to run, authorized encryption can be performed on the application software developed by the user, and the problems that encryption measures of the existing core board are unreliable, the encryption pieces are easy to damage and the like are solved. The functional interface is led out through the connector in the embodiment, so that a user can quickly design main boards or products with different sizes and different interface types, the expansibility is strong, and the core board is easy to disassemble and assemble.

Optionally, the hardware encryption chip is an RJGT102 chip. The RJGT102 chip is an encryption chip with high safety, low power consumption and simple and convenient operation, message abstract calculation is carried out by using an SHA-256 encryption algorithm, 4 built-in 32-byte Page areas can store user application data, the unique 8-byte UID serial number is used for distinguishing different application functions, each RJGT102 chip has a unique chip id, and the chip is suitable for being applied to anti-copying boards and anti-copying software, controls the production quantity of factories, prevents schemes from leaking and the like.

Optionally, the number of the serial port, the network interface, the USB interface, the IIC interface, the SPI interface, and the GPIO interface is one or more. The user can select the number of various interfaces according to the self requirement so as to balance the cost, the volume and the expansibility.

Optionally, the connector is a board-to-board connector. Board-to-board connectors are the most powerful connectors currently available, and power and signals between printed circuit boards can be directly connected through the pins of the connectors. Copper alloys have been commonly used for board-to-board connectors to prevent oxidation for many years to prevent conductivity degradation. In electronics manufacturing, the entire device may need to fit into the available space, and if the PCB at the circuit board design stage tends to take up too much space, the device may be split into two or more boards, and board-to-board connectors may connect power and signals between the boards to complete all connections. The use of board-to-board connectors simplifies the circuit board design process: smaller PCBs require manufacturing equipment that may not be able to accommodate larger PCBs, whether by extruding the device or product into a single PCB or multiple PCBs, to account for power consumption, undesirable signal coupling to each other, availability of smaller components, and overall cost of the finished device or product. Furthermore, the use of board-to-board connectors also simplifies the production and testing of electronic devices: in electronics manufacturing, simplified testing reflects a tremendous cost savings, with high density PCBs having more traces and components per unit area. Depending on the investment in complexity of the manufacturing plant, the equipment or product is preferably designed with several interconnected medium density boards instead of a single high density board. Board-to-board connector via technology allows for a third dimension connection of traces and components on a PCB, a first PCB may use conductive copper traces in both horizontal and vertical directions along the PCB, with the addition of more layers of circuit boards, almost a few single layer PCBs between the two sides of a double-sided PCB, a typical multi-layer PCB with five layers may be less than 0.08 inch (2mm) thick, and vias with conductive inner surfaces that can carry current between any two layers of the multi-layer PCB.

Modern electronic devices are more reliable and less expensive to manufacture due to various mature technologies. Multilayer board PCB fabrication has been a significant challenge due to the hidden connections between two or more layers of copper traces. Surface Mount Technology (SMT) promotes miniaturization because components can be easily mounted on a PCB even without drilling. In SMT, the robotic device applies adhesive to the underside of the component prior to adhering the component to the PCB. The leads on the pre-tinned leads of the components and the leads on the pre-tinned pads on the PCB will be reflowed or reflowed and the soldering process is completed as the PCB cools.

Optionally, the connectors have two. In practice, if only one connector is provided, a plurality of interfaces such as a serial port, a network interface, a USB interface, an IIC interface, an SPI interface, and a GPIO interface cannot be simultaneously led out, and the expansibility is limited; the size of the traditional ARM core board has design requirements, and more board-to-board connectors cannot be arranged in a limited space. In this embodiment, two connectors are preferably provided.

Optionally, the connector has 80 pins. The core board adopts 2 boards to the board connector, draws 160pin function pins, and convenience of customers designs the mainboard of different sizes, different interfaces in a flexible way.

Optionally, the connector is F30FC-80DP-0.4V type.

Optionally, as shown in fig. 2, the ARM core board with integrated hardware encryption further includes a USB interface protection circuit, where the USB interface protection circuit includes a magnetic patch bead FB, a common-mode inductor L1, a TVS diode D1, a TVS diode D2, a resistor R1, a resistor R2, a varistor R3, a capacitor C1, and a capacitor C2, the magnetic patch bead FB is connected to a Vbus line of the USB interface, the Vbus line is grounded through the varistor R3, the common-mode inductor L1 is connected between a D + line and a D-line of the USB interface, the D + line is grounded through the TVS diode D1, the D-line is grounded through the TVS diode D2, the resistor R1 is connected to the D + line, the resistor R2 is connected to the D-line, the D + line is grounded through the capacitor C1, and the D-line is grounded through the capacitor C2.

The patch magnetic bead FB is used for eliminating RF noise on a USB interface Vbus line, RF energy is an alternating current sine wave component superposed on a direct current transmission level, the direct current component is a required useful signal, and the radio frequency RF energy is useless electromagnetic interference which is transmitted and radiated along the line. The common mode inductor L1 functions as an EMI filter for suppressing the outward radiation emission of electromagnetic waves generated by the high speed signal lines D +, D-. The resistor R1 and the resistor R2 play a role in current limiting, the varistor R3 is used for electrostatic discharge, the capacitor C1 and the capacitor C2 are used for filtering, and the common-mode inductor L1 and the capacitor C1 or the capacitor C2 form an LC filter for filtering common-mode and differential-mode interference at the input end of the LC filter. The TVS diodes D1 and D2 suppress electrostatic pulses. Therefore, the circuit can perform electrostatic protection and inhibit common-mode interference on the USB interface, and the signal line and the power line are well subjected to electrostatic protection.

The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (8)

1. The ARM core board is characterized in that a connector and a hardware encryption chip which are connected with the CPU respectively are further integrated, and the CPU is led out a serial port, a network interface, a USB interface, an IIC interface, an SPI interface and a GPIO interface through the connector.

2. The integrated hardware cryptographic ARM core board of claim 1, wherein the hardware cryptographic chip is an RJGT102 chip.

3. The integrated hardware encrypted ARM core board of claim 1, wherein the number of the serial port, the network interface, the USB interface, the IIC interface, the SPI interface, and the GPIO interface is one or more.

4. The integrated hardware encrypted ARM core board of claim 1, wherein the connector is a board-to-board connector.

5. The integrated hardware encrypted ARM core board of claim 4, wherein the connectors have two.

6. The integrated hardware encrypted ARM core board of claim 5, wherein the connector has 80 pins.

7. The integrated hardware encrypted ARM core board of claim 6, wherein the connector is of type F30FC-80 DP-0.4V.

8. The integrated hardware encrypted ARM core board of claim 1, further comprising a USB interface protection circuit, wherein the USB interface protection circuit comprises a magnetic patch bead FB, a common mode inductor L1, a TVS diode D1, a TVS diode D2, a resistor R1, a resistor R2, a varistor R3, a capacitor C1, and a capacitor C2, the magnetic patch bead FB is connected to a Vbus line of the USB interface, the Vbus line is connected to ground through the varistor R3, the common mode inductor L1 is connected between a D + line and a D-line of the USB interface, the D + line is connected to ground through the TVS diode D1, the D-line is connected to ground through the TVS diode D2, the resistor R1 is connected to the D + line, the resistor R2 is connected to the D-line, the D + line is further connected to ground through the capacitor C1, and the D-line is further connected to ground through the capacitor C2.

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