CN102650978B

CN102650978B - Adapting card for peripheral component interface (PCI) Express X16 to compact peripheral component interconnect (CPCI) Express X16

Info

Publication number: CN102650978B
Application number: CN201210083268.7A
Authority: CN
Inventors: 周强; 梁剑; 刘亚斌; 徐志跃
Original assignee: Beihang University
Current assignee: Beihang University
Priority date: 2012-03-27
Filing date: 2012-03-27
Publication date: 2015-02-11
Anticipated expiration: 2032-03-27
Also published as: CN102650978A

Abstract

The invention discloses an adapting card for peripheral component interface (PCI) Express X16 to compact peripheral component interconnect (CPCI) Express X16. The adapting card comprises an impedance control circuit board, an adapting circuit board, a PCI Express X16 interface, a CPCI Express signal socket, a CPCI Express power socket, a double-row hole socket, a bent pin double-row plug, a connecting block and a baffle plate, wherein the CPCI Express signal socket and the adapting circuit board are connected with the upper part of the impedance control circuit board; a PCI Express X16 interface is formed in the lower part of the impedance control circuit board; the bent pin double-row plug is arranged on the left middle part of the impedance control circuit board; and the CPCI Express power socket and the bent pin double-row plug are arranged on the adapting circuit board. The quality and the efficiency of a signal are not affected, the application range of the current PCI Express X16 slot is expanded, the difficulty and the cost for the development of a CPCI Express X16 interface card are greatly reduced, and the adapting card is simple in structure and convenient to use.

Description

A kind of adapter for PCI Express X16 to CPCI Express X16

Technical field

The present invention relates to a kind of adapter for PCI Express X16 to CPCI Express X16, for PCI Express X16 slot in computing machine being converted to the CPCI Express X16 slot meeting PICMG EXP.0R1.0 standard, can carry out applying, debug and testing in PCI Express X16 slot to make the CPCI Express X16 plug-in card meeting PICMG EXP.0R1.0 standard.The invention belongs to compunication, computer-aided test and field of automatic testing.

Background technology

PCIExpress is the computer serial bus of a new generation, it instead of traditional synchronous or asynchronous sequential logic bus interface with agreement, have transfer rate high, save hardware resource, without crosstalk, without intersymbol interference, no signal offset, without outstanding features such as direct current biasings.So, just obtain once release and pay attention to widely and apply.Current all kinds of business computer, industrial control computer etc. all have PCI Express expansion slot.Can say, PCI Express bus just progressively substitutes and replaces traditional pci bus.

PCI Express bus can be configured to 1 passage (Lane) and be connected to 32 expanding channels, has very strong retractility, to meet the different system equipment demand different to data transfer bandwidth.The passage configuration that PCI Express bus is commonly used comprises: X1, X4, X8 and X16.The PCI Express card that passage is few can insert in the many PCI Express slots of passage and use, and is called and inserts (Up-plugging).PCI Express expansion card contour dimension and type of attachment and pci bus very similar, but its pinout is completely different, and does not support-12V and 5V power supply.

CompactPCI Express is International Industry Technological Problems In Computer Manufacturing person federation (PCI Industrial Computer Manufacturer ' s Group, be called for short PICMG) both CompactPCI (Compact Peripheral Component Interconnect, be called for short CPCI, Chinese claims compact PCI) after, release in 2005 the compact Express standard (i.e. PICMG EXP.0R1.0) issued.

CompactPCI Express mono-aspect inherits original technical advantage of CompactPCI, adopt highly reliable Eurocard structure, improve radiating condition, improve anti-vibrating and impact ability, meet EMC Requirements, the high speed pin hole connector of employing 2mm density substitutes the golden finger type interconnection mode in PCI Express, further increase reliability, maintain high-speed differential signal integrality, and add load capacity.On the other hand what is more important, transmit in CompactPCI Express mainly at a high speed, low-swing difference signal, compatible whole interface protocols of PCI Express bus.Due to the original advantage of CompactPCI Express, it has boundless application prospect in telecommunications, compunication, industry control and the field such as test, Aero-Space.

But, due to CompactPCI Express Standard Interface clamp and cabinet, cause CompactPCI Express interface card layout in the chassis closely, the exploitation almost cannot carrying out easily being correlated with, test and debugging efforts.Meanwhile, the equipment that CompactPCI Express is correlated with also costly, builds a set of CompactPCI Express basic platform (cabinet and controller) cost high.

Therefore, being necessary for very much CompactPCI Express interface clamp provides both to meet an interface protocol, with low cost, is convenient to again to develop, the environment of test and debugging.In fact, because PCI Express is identical with CompactPCI Express interface protocol, therefore the two has the association of many inherences; And no matter commercial PCI Express is and industrial control system is very universal, cheap, system development is good, be very suitable for as the platform developed, test and debug.But due to the difference of CompactPCI Express and PCI Express AN connector and interface definition, cause CompactPCI Express interface board at all cannot directly application, debugging and test in PCI Express system (computing machine).That is, current PCI Express system incompatible CompactPCI Express interface board (expansion card).

Summary of the invention

The object of the present invention is to provide a kind of adapter for PCI Express X16 to CPCI Express X16, for the PCIExpress X16 slot in commercial and the desk-top computing machine of Industry Control is converted to the CPCI Express X16 slot meeting PICMG EXP.0R1.0 standard, can carry out applying, debug and testing in the PCI Express X16 slot in general commercial and the desk-top computing machine of Industry Control to make CPCI Express X16 interface card (plug-in card) meeting PICMG EXP.0R1.0 standard.

Conversion in the present invention comprises: one, and PCI Express X16 physical slot is converted to CPCI Express X16 signal slot XP3, XP2 and power supply auxiliary slot XP4, they are two years old, the signal utilizing impedance control circuit plate to transfer at least comprises reference clock differential signal (RefClk+ and RefClk-), receive differential signal (PERp0 and PERn0, PERp1 and PERn1, PERp2 and PERn2, PERp3 and PERn3, PERp4 and PERn4, PERp5 and PERn5, PERp6 and PERn6, PERp7 and PERn7, PERp8 and PERn8, PERp9 and PERn9, PERp10 and PERn10, PERp11 and PERn11, PERp12 and PERn12, PERp13 and PERn13, PERp14 and PERn14, PERp15 and PERn15), send differential signal (PETp0 and PETn0, PETp1 and PETn1, PETp2 and PETn2, PETp3 and PETn3, PETp4 and PETn4, PETp5 and PETn5, PETp6 and PETn6, PETp7 and PETn7, PETp8 and PETn8, PETp9 and PETn9, PETp10 and PETn10, PETp11 and PETn11, PETp12 and PETn12, PETp13 and PETn13, PETp14 and PETn14, PETp15 and PETn15) and with reference to earth signal, its three, the power supply utilizing impedance control circuit plate to transfer comprises+12V and+3.3V direct supply.

A kind of adapter for PCI Express X16 to CPCI Express X16 of the present invention, this adapter described comprises: impedance control circuit plate, switching circuit board, PCI Express X16 interface, CPCI Express signal plug, CPCI Express supply socket, double-row hole socket, the double plug of looper, contiguous block and baffle plate, position annexation between them is: impedance control circuit plate profile is L-shaped, its top edge is crimped with CPCI Express signal plug and switching circuit board, its underpart edge placement has PCI Express X16 interface, the middle part to the left of impedance control circuit plate is furnished with the double plug of looper, CPCIExpress supply socket and the double plug of looper, be arranged on switching circuit board, this contiguous block is fixed together vertical with switching circuit board for impedance control circuit plate by screw, this baffle plate, side is connected with impedance control circuit plate, opposite side is fixed together by screw and computer cabinet edge conjunction.

This impedance control circuit plate, in order to the low-swing difference signal (typical in LVDS signal) in high speed, low-loss, short distance is liftoff transmission PCI Express X16 to CPCI Express signal plug.

This switching circuit board, it is vertically fixedly mounted on the top edge of impedance control circuit plate by contiguous block.

This PCI Express X16 interface, it is positioned at the lower edge of impedance control circuit plate, in order to carry out physical connection, transmission of signal and power supply with PCI Express X16 slot.

This CPCI Express signal plug, it is positioned at the top edge of impedance control circuit plate, in order to carry out physical connection, transmission of signal with XP3 and the XP2 Signal plug in CPCI Express X16.

This CPCI Express supply socket, it is arranged on switching circuit board, in order to carry out physical connection with the XP4 attaching plug in CPCI Express X16, transmits power supply.

This double-row hole socket, it is positioned at the top of impedance control circuit plate, in order to transmit power supply.

The double plug of this looper, it is arranged on switching circuit board, in order to be connected with the double-row hole socket on impedance control circuit plate, transmits power supply.

This contiguous block, it is fixed together vertical with switching circuit board for impedance control circuit plate by screw.

This baffle plate, side is connected with impedance control circuit plate, and opposite side is fixed together by screw and computer cabinet edge conjunction.

Wherein, described impedance control circuit plate is more than 6 layers multilayer circuit boards, and its profile is L-shaped, and its thickness of slab is 1.6mm

Above, the length of differential signal line is less than 66mm (2598mil).

Wherein, described impedance control circuit plate at least comprises two with reference to stratum and two signals layers.

Wherein, in described impedance control circuit plate, the differential characteristic impedance of differential signal line is 100 Ω ± 10 Ω.

Wherein, in described impedance control circuit plate, signal wire is 50 Ω ± 10 Ω to the single-ended characteristic impedance with reference to ground.

Wherein, in described impedance control circuit plate, two length differences belonged to the signal wire of a pair differential signal are less than 0.127mm (5mil).

Wherein, the length difference between two different sendaisles is less than 2.54mm (100mil), and the length difference between two different receiving cables is less than 2.54mm (100mil);

Wherein, described PCI Express X16 interface is the PCI Express X16 interface meeting PCI Express Card Electromechanical Specification Revision 1.0 specification;

Wherein, the power supply of described double-row hole socket transmission comprises+12V and+3.3V direct supply;

Wherein, the PCI Express signal that CPCI Express XP3 signal plug and the switching of CPCI Express XP2 signal plug are transmitted at least comprises reference clock differential signal (RefClk+ and RefClk-), receive differential signal (PERp0 and PERn0, PERp 1 and PERn 1, PERp2 and PERn2, PERp3 and PERn3, PERp4 and PERn4, PERp5 and PERn5, PERp6 and PERn6, PERp7 and PERn7, PERp8 and PERn8, PERp9 and PERn9, PERp10 and PERn10, PERp11 and PERn11, PERp12 and PERn12, PERp13 and PERn13, PERp14 and PERn14, PERp15 and PERn15), send differential signal (PETp0 and PETn0, PETp1 and PETn1, PETp2 and PETn2, PETp3 and PETn3, PETp4 and PETn4, PETp5 and PETn5, PETp6 and PETn6, PETp7 and PETn7, PETp8 and PETn8, PETp9 and PETn9, PETp10 and PETn10, PETp11 and PETn11, PETp12 and PETn12, PETp13 and PETn13, PETp14 and PETn14, PETp15 and PETn15) and with reference to earth signal,

Wherein, PCI Express X16 interface sends differential signal (PETp0 and PETn0), and correspondence is transferred to the reception differential signal pin (2PERp0 and 2PER0) of CPCI ExpressXP3 signal plug;

Wherein, PCI Express X16 interface sends differential signal (PETp1 and PETn1, PETp2 and PETn2, PETp3 and PETn3, PETp4 and PETn4, PETp5 and PETn5, PETp6 and PETn6, PETp7 and PETn7, PETp8 and PETn8, PETp9 and PETn9, PETp10 and PETn10, PETp11 and PETn11, PETp12 and PETn12, PETp13 and PETn13, PETp14 and PETn14, PETp15 and PETn15), corresponding reception differential signal pin (2PERp1 and 2PERn1 being transferred to CPCI ExpressXP2 interface socket respectively, 2PERp2 and 2PERn2, 2PERp3 and 2PERn3, 2PERp4 and 2PERn4, 2PERp5 and 2PERn5, 2PERp6 and 2PERn6, 2PERp7 and 2PERn7, 2PERp8 and 2PERn8, 2PERp9 and 2PERn9, 2PERp10 and 2PERn10, 2PERp11 and 2PERn11, 2PERp12 and 2PERn12, 2PERp13 and 2PERn13, 2PERp14 and 2PERn14, 2PERp15 and 2PERn15).

Wherein, PCI Express X16 interface differential signal (PERp0 and PERn0), correspondence is transferred to the transmission differential signal pin (2PETp0 and 2PETn0) of CPCI ExpressXP3 interface socket.

Wherein, PCI Express X16 interface differential signal (PERp1 and PERn1, PERp2 and PERn2, PERp3 and PERn3, PERp4 and PERn4, PERp5 and PERn5, PERp6 and PERn6, PERp7 and PERn7, PERp8 and PERn8, PERp9 and PERn9, PERp10 and PERn10, PERp11 and PERn11, PERp12 and PERn12, PERp13 and PERn13, PERp14 and PERn14, PERp15 and PERn15), corresponding transmission differential signal pin (2PETp1 and 2PETn1 being transferred to CPCI ExpressXP2 interface socket respectively, 2PETp2 and 2PETn2, 2PETp3 and 2PETn3, 2PETp4 and 2PETn4, 2PETp5 and 2PETn5, 2PETp6 and 2PETn6, 2PETp7 and 2PETn7, 2PETp8 and 2PETn8, 2PETp9 and 2PETn9, 2PETp10 and 2PETn10, 2PETp11 and 2PETn11, 2PETp12 and 2PETn12, 2PETp13 and 2PETn13, 2PETp14 and 2PETn14, 2PETp15 and 2PETn15).

Wherein, PCI Express X16 interface clock differential signal (RefClk+ and RefClk-) correspondence is transferred to the clock difference sub-signal pin (2RefClk+ and 2RefClk-) of CPCI ExpressXP3 interface socket.

A kind of adapter for PCI Express X16 to CPCI Express X16 of the present invention, its advantage and effect are: the present invention utilizes the low-swing difference signal (typical as LVDS signal) in multilayer impedance control circuit board transmission high speed, low-loss, short distance is liftoff transmission PCI Express X16 and CPCIExpress X16, as long as impedance Control precision meets the demands, quality and effect of signal can not be affected.Simultaneously, the present invention significantly can expand the application of existing PCI Express X16 slot, make its compatible CPCI Express X16 interface card (expansion card), significantly reduce CPCI Express X16 interface card (expansion card) difficulty developed and cost, be more convenient for scientific research and developer carries out debugging and tests, and also namely increases substantially testability and the adjustable of CPCIExpress X16 interface card (expansion card).Structure of the present invention is simple, very easy to use.

Accompanying drawing explanation

Figure 1A is depicted as axis side view of the present invention.

Figure 1B is depicted as backward axis side view of the present invention.

Figure 2 shows that the contour dimension figure of the impedance control circuit plate 101 in Figure 1A.

Figure 3 shows that the contour dimension figure of the switching circuit board 105 in Figure 1A.

Fig. 4 A is depicted as impedance control circuit plate 101 ground floor (L1) the PCB design figure in Figure 1A.

Fig. 4 B is depicted as impedance control circuit plate 101 third layer (L3) the PCB design figure in Figure 1A.

Fig. 4 C is depicted as impedance control circuit plate 101 the 4th layer of (L4) the PCB design figure in Figure 1A.

Fig. 4 D is depicted as impedance control circuit plate 101 layer 6 (L6) the PCB design figure in Figure 1A.

Fig. 5 A is depicted as switching circuit board 105 ground floor (L1) the PCB design figure in Figure 1A.

Fig. 5 B is depicted as switching circuit board 105 second layer (L2) the PCB design figure in Figure 1A.

Figure 6 shows that the flaggy design drawing of the impedance control circuit plate 101 in Figure 1A.

Figure 7 shows that the flaggy design drawing of the switching circuit board 105 in Figure 1A.

In figure, concrete label is as follows:

101 impedance control circuit plate 102PCI Express X16 interfaces

103CPCI Express XP3 signal plug 104CPCI Express XP2 signal plug

105CPCI Express supply socket XP4

106 switching circuit board 107 baffle plates

The double plug of 108 double-row hole socket 109 looper

110 contiguous block 111M2 screws

112M3 screw

401+3.3V direct supply covers copper II

402WAKE# signal lead I 403 differential reference clock cabling

404PCI Express Reset signal lead 405 System Management Bus cabling

406PCI Express sends signal lead lane0 407+12V direct supply and covers copper I

There is detection signal cabling in 408PCI Express Received signal strength cabling lane0 409 hot plug

410 Φ 3 through hole 411 Φ 2 through holes

412PCI Express X16 golden finger 413CPCI Express signal plug hole

41410 pin double-row hole 415PCI Express send signal lead lane1

416PCI Express Received signal strength cabling lane1 417PCI Express sends signal lead lane2

418PCI Express Received signal strength cabling lane2 419PCI Express sends signal lead lane3

420PCI Express Received signal strength cabling lane3 421PCI Express sends signal lead lane4

422PCI Express Received signal strength cabling lane4 423PCI Express sends signal lead lane5

424PCI Express Received signal strength cabling lane5 425PCI Express sends signal lead lane6

426PCI Express Received signal strength cabling lane6 427PCI Express sends signal lead lane7

428PCI Express Received signal strength cabling lane7 429PCI Express sends signal lead lane8

430PCI Express Received signal strength cabling lane8 431PCI Express sends signal lead lane9

432PCI Express Received signal strength cabling lane9 433PCI Express sends signal lead lane10

434PCI Express Received signal strength cabling lane10 435PCI Express sends signal lead lane11

436PCI Express Received signal strength cabling lane11 437PCI Express sends signal lead 1ane12

438PCI Express Received signal strength cabling lane12 439PCI Express sends signal lead lane13

440PCI Express Received signal strength cabling lane13 441PCI Express sends signal lead lane14

442PCI Express Received signal strength cabling lane14 443PCI Express sends signal lead lane15

444PCI Express Received signal strength cabling lane15

501+12V direct supply covers copper II

502+3.3V direct supply covers copper II 503GND and covers copper

504WAKE# signal lead II 505CPCI Express power plug bore

506 Φ 2 through hole 50710 pin double-row holes

the unit symbol related in the present invention is described as follows:

Ω ohm

Mm millimeter

Mil mil

Embodiment

Please refer to accompanying drawing 1A, a kind of adapter for PCI Express X16 to CPCI Express X16 of better embodiment of the present invention comprises an impedance control circuit plate 101, PCI Express X16 interface 102, switching circuit board 106, CPCIExpress supply socket 105, CPCI Express signal plug 103 and 104, a pair of row-hole socket 108, looper double plug 109, contiguous block 110, baffle plate 107, three M2 screws 111, two M3 screws 110.

The lower edge of described impedance control circuit plate 101 is furnished with PCI ExpressX16 interface 102, in order to carry out physical connection, transmission of signal and direct supply with PCI ExpressX16 slot.

Wherein, described PCI Express X16 interface 102 is specifically arranged in the lower edge of impedance control circuit plate 101 with the form of golden finger.Please refer to table 1, the golden finger pin on PCI Express X16 interface 102 and signal definition as shown in table 1 below, it meets PCI Express Card Electromechanical Specification Revision 2.0 specification.

Table 1

The top edge of described impedance control circuit plate 101 is furnished with CPCI Express XP3 signal plug 103 and CPCI Express XP2 signal plug 104, in order to carry out physical connection, transmission of signal with CPCI Express interface card XP3 and XP2 Signal plug.XP3 please refer to table 2a, XP2 please refer to table 2b its meet PXI Express Hardware Specification Revision 1.0 specification.

Table 2a

Table 2b

The middle part to the left of described impedance control circuit plate 101 is furnished with the double plug 109 of looper, in order to carry out physical connection with double-row hole socket 108, direct supply is passed to switching circuit board 105 from impedance control circuit plate 101.

Described switching circuit board 106 level is fixed on the top edge of impedance control circuit plate 101, in order to direct supply is passed to CPCI Express supply socket 105 from double-row hole socket 108.

Described CPCI Express supply socket 105, in order to carry out physical connection with CPCI Express interface card XP4 attaching plug, transmits direct supply.

Please refer to accompanying drawing 2, described impedance control circuit plate 101 profile is L-shaped, and contour dimension is with reference to accompanying drawing 2, and dimensional data unit is mm.

Please refer to accompanying drawing 6, described impedance control circuit plate 101 is six layer impedance control circuit boards.

Wherein, the ground floor (L1) of described impedance control circuit plate 101 is signals layer 1, the second layer (L2) is ground plane, third layer (L3) is signals layer, 4th layer (L4) is signals layer, layer 5 (L5) is ground plane, and layer 6 (L6) is signals layer.Every layer and relevant thickness as shown in table 3 below.

Level number	Model	Thickness
			L1	1.4
	Prepreg
			L2	1.4
	Central layer
			L3	1.4
	Prepreg
			L4	1.4
	Prepreg
			L5	1.4
	Central layer
			L6	1.4

Table 3

Wherein, for the signal lead of signals layers 1 all on described impedance control circuit plate 101 and signals layer 2, its single-ended impedance is 50 Ω ± 10 Ω, and its differential impedance is 100 Ω ± 10 Ω.

On described impedance control circuit plate 101 signal impedance control method be that differential signal line width is 5mil, the spacing between two signal line in a pair differential signal line is 7mil, different differential signal lines between distance should be greater than at least 20mil.The differential impedance that be can be calculated differential signal line by signal impedance is 101.8 Ω, and single-ended impedance is 51.78 Ω.

Please refer to accompanying drawing 4A, the ground floor (L1) of described impedance control circuit plate 101, namely signals layer 1 comprises System Management Bus (System Management Bus) signal lead 405, differential reference clock (Reference clock) signal lead 403, PCIExpress difference sends (PCI Express Transmitter Lane 0) signal lead 406, and hot-swappable exist detection signal cabling 409 and+12V direct supply covers copper I 407.

Described System Management Bus (System Management Bus) signal lead 405 comprises, SMCLK (SMBUS clock) signal and SMDAT (SMBUS data) signal.Wherein, SMCLK signal is connected to the pin B3 of CPCI Express signal plug 103 by the golden finger pin B5 of PCI Express X16 interface 102.Wherein, SMDAT signal is connected to the pin A3 of CPCI Express signal plug 103 by the golden finger pin B6 of PCI ExpressX16 interface 102.

Described differential reference clock signal cabling 403 comprises a pair differential reference clock signal REFCLK+ and REFCLK-.Wherein, REFCLK+ signal is connected to the pin C4 of CPCI Express signal plug 103 by the golden finger pin A13 of PCI Express X16 interface 102.Wherein, REFCLK-signal is connected to the pin D4 of CPCI Express signal plug 103 by the golden finger pin A14 of PCI Express X16 interface 102.

Described PCI Express difference sends signal lead and comprises PETp0 and PETn0, PETp1 and PETn1, PETp2 and PETn2, PETp3 and PETn3, PETp4 and PETn4, PETp5 and PETn5, PETp6 and PETn6, PETp7 and PETn7, PETp8 and PETn8, PETp9 and PETn9, PETp10 and PETn10, PETp11 and PETn11, PETp12 and PETn12, PETp13 and PETn13, PETp14 and PETn14, PETp15 and PETn15.

Wherein, PETp0 signal is connected to the pin A10 of CPCI Express signal plug 103 by the golden finger pin B14 of PCI Express X16 interface 102.Wherein, PETn0 signal is connected to the pin B10 of CPCI Express signal plug 103 by the golden finger pin D15 of PCI Express X16 interface 102.

Wherein, PETp1 signal is connected to the pin A1 of CPCI Express signal plug 104 by the golden finger pin B19 of PCI Express X16 interface 102.Wherein, PETn0 signal is connected to the pin B1 of CPCI Express signal plug 104 by the golden finger pin B20 of PCIExpress X16 interface 102.

Wherein, PETp2 signal is connected to the pin E1 of CPCI Express signal plug 104 by the golden finger pin B23 of PCI Express X16 interface 102.Wherein, PETn2 signal is connected to the pin F1 of CPCI Express signal plug 104 by the golden finger pin B24 of PCI Express X16 interface 102.

Wherein, PETp3 signal is connected to the pin A2 of CPCI Express signal plug 104 by the golden finger pin B27 of PCI Express X16 interface 102.Wherein, PETn3 signal is connected to the pin B2 of CPCI Express signal plug 104 by the golden finger pin B28 of PCI Express X16 interface 102.

Wherein, PETp4 signal is connected to the pin A3 of CPCI Express signal plug 104 by the golden finger pin B33 of PCI Express X16 interface 102.Wherein, PETn4 signal is connected to the pin B3 of CPCI Express signal plug 104 by the golden finger pin B34 of PCI Express X16 interface 102.

Wherein, PETp5 signal is connected to the pin E3 of CPCI Express signal plug 104 by the golden finger pin B37 of PCI Express X16 interface 102.Wherein, PETn5 signal is connected to the pin F3 of CPCI Express signal plug 104 by the golden finger pin B38 of PCIExpress X16 interface 102.

Wherein, PETp6 signal is connected to the pin A4 of CPCI Express signal plug 104 by the golden finger pin B41 of PCI Express X16 interface 102.Wherein, PETn6 signal is connected to the pin B4 of CPCI Express signal plug 104 by the golden finger pin B42 of PCI Express X16 interface 102.

Wherein, PETp7 signal is connected to the pin A5 of CPCI Express signal plug 104 by the golden finger pin B45 of PCI Express X16 interface 102.Wherein, PETn7 signal is connected to the pin B5 of CPCI Express signal plug 104 by the golden finger pin B46 of PCIExpress X16 interface 102.

Wherein, PETp8 signal is connected to the pin E5 of CPCI Express signal plug 104 by the golden finger pin B50 of PCI Express X16 interface 102.Wherein, PETn8 signal is connected to the pin F5 of CPCI Express signal plug 104 by the golden finger pin B51 of PCI Express X16 interface 102.

Wherein, PETp9 signal is connected to the pin A6 of CPCI Express signal plug 104 by the golden finger pin B54 of PCI Express X16 interface 102.Wherein, PETn9 signal is connected to the pin B6 of CPCI Express signal plug 104 by the golden finger pin B55 of PCI Express X16 interface 102.

Wherein, PETp10 signal is connected to the pin A7 of CPCI Express signal plug 104 by the golden finger pin B58 of PCI Express X16 interface 102.Wherein, PETn10 signal is connected to the pin B7 of CPCI Express signal plug 104 by the golden finger pin B59 of PCI Express X16 interface 102.

Wherein, PETp11 signal is connected to the pin E7 of CPCI Express signal plug 104 by the golden finger pin B62 of PCI Express X16 interface 102.Wherein, PETn11 signal is connected to the pin F7 of CPCI Express signal plug 104 by the golden finger pin B63 of PCIExpress X16 interface 102.

Wherein, PETp12 signal is connected to the pin A8 of CPCI Express signal plug 104 by the golden finger pin B66 of PCI Express X16 interface 102.Wherein, PETn12 signal is connected to the pin B8 of CPCI Express signal plug 104 by the golden finger pin B67 of PCI Express X16 interface 102.

Wherein, PETp13 signal is connected to the pin A9 of CPCI Express signal plug 104 by the golden finger pin B14 of PCI Express X16 interface 102.Wherein, PETn13 signal is connected to the pin B9 of CPCI Express signal plug 104 by the golden finger pin B15 of PCIExpress X16 interface 102.

Wherein, PETp14 signal is connected to the pin E9 of CPCI Express signal plug 104 by the golden finger pin B70 of PCI Express X16 interface 102.Wherein, PETn14 signal is connected to the pin F9 of CPCI Express signal plug 104 by the golden finger pin B71 of PCI Express X16 interface 102.

Wherein, PETp15 signal is connected to the pin A10 of CPCI Express signal plug 104 by the golden finger pin B74 of PCI Express X16 interface 102.Wherein, PETn15 signal is connected to the pin B10 of CPCI Express signal plug 104 by the golden finger pin B75 of PCI Express X16 interface 102.

Receive differential signal and comprise cabling PERp0 and PERn0, PERp1 and PERn1, PERp2 and PERn2, PERp3 and PERn3, PERp4 and PERn4, PERp5 and PERn5, PERp6 and PERn6, PERp7 and PERn7, PERp8 and PERn8, PERp9 and PERn9, PERp10 and PERn10, PERp11 and PERn11, PERp12 and PERn12, PERp13 and PERn13, PERp14 and PERn14, PERp15 and PERn15.

Wherein, PERp0 signal is connected to the pin C10 of CPCI Express signal plug 103 by the golden finger pin A16 of PCI Express X16 interface 102.Wherein, PERn0 signal is connected to the pin D10 of CPCI Express signal plug 103 by the golden finger pin A17 of PCIExpress X16 interface 102.

Wherein, PERp1 signal is connected to the pin C1 of CPCI Express signal plug 104 by the golden finger pin A21 of PCI Express X16 interface 102.Wherein, PERn1 signal is connected to the pin D1 of CPCI Express signal plug 104 by the golden finger pin A22 of PCI Express X16 interface 102.

Wherein, PERp2 signal is connected to the pin E2 of CPCI Express signal plug 104 by the golden finger pin A25 of PCI Express X16 interface 102.Wherein, PERn2 signal is connected to the pin F2 of CPCI Express signal plug 104 by the golden finger pin A26 of PCI Express X16 interface 102.

Wherein, PERp3 signal is connected to the pin C2 of CPCI Express signal plug 104 by the golden finger pin A29 of PCI Express X16 interface 102.Wherein, PERn3 signal is connected to the pin D2 of CPCI Express signal plug 104 by the golden finger pin A30 of PCI Express X16 interface 102.

Wherein, PERp4 signal is connected to the pin C3 of CPCI Express signal plug 104 by the golden finger pin A35 of PCI Express X16 interface 102.Wherein, PERn4 signal is connected to the pin D3 of CPCI Express signal plug 104 by the golden finger pin A36 of PCI Express X16 interface 102.

Wherein, PERp5 signal is connected to the pin E4 of CPCI Express signal plug 104 by the golden finger pin A39 of PCI Express X16 interface 102.Wherein, PERn5 signal is connected to the pin F4 of CPCI Express signal plug 104 by the golden finger pin A40 of PCI Express X16 interface 102.

Wherein, PERp6 signal is connected to the pin C4 of CPCI Express signal plug 104 by the golden finger pin A43 of PCI Express X16 interface 102.Wherein, PERn6 signal is connected to the pin D4 of CPCI Express signal plug 104 by the golden finger pin A44 of PCI Express X16 interface 102.

Wherein, PERp7 signal is connected to the pin C4 of CPCI Express signal plug 104 by the golden finger pin B14 of PCI Express X16 interface 102.Wherein, PERn7 signal is connected to the pin D5 of CPCI Express signal plug 104 by the golden finger pin B15 of PCIExpress X16 interface 102.

Wherein, PERp8 signal is connected to the pin E6 of CPCI Express signal plug 104 by the golden finger pin A47 of PCI Express X16 interface 102.Wherein, PERn8 signal is connected to the pin F6 of CPCI Express signal plug 104 by the golden finger pin A48 of PCI Express X16 interface 102.

Wherein, PERp9 signal is connected to the pin C6 of CPCI Express signal plug 104 by the golden finger pin B14 of PCI Express X16 interface 102.Wherein, PERn9 signal is connected to the pin D6 of CPCI Express signal plug 104 by the golden finger pin B15 of PCIExpress X16 interface 102.

Wherein, PERp10 signal is connected to the pin C7 of CPCI Express signal plug 104 by the golden finger pin A56 of PCI Express X16 interface 102.Wherein, PERn10 signal is connected to the pin D7 of CPCI Express signal plug 104 by the golden finger pin A57 of PCIExpress X16 interface 102.

Wherein, PERp11 signal is connected to the pin E8 of CPCI Express signal plug 104 by the golden finger pin A64 of PCI Express X16 interface 102.Wherein, PERn11 signal is connected to the pin F8 of CPCI Express signal plug 104 by the golden finger pin A65 of PCIExpress X16 interface 102.

Wherein, PERp12 signal is connected to the pin C8 of CPCIExpress signal plug 104 by the golden finger pin A68 of PCI Express X16 interface 102.Wherein, PERn12 signal is connected to the pin D8 of CPCI Express signal plug 104 by the golden finger pin A69 of PCIExpress X16 interface 102.

Wherein, PERp13 signal is connected to the pin C9 of CPCI Express signal plug 104 by the golden finger pin A72 of PCI Express X16 interface 102.Wherein, PERn13 signal is connected to the pin D9 of CPCI Express signal plug 104 by the golden finger pin A73 of PCI Express X16 interface 102.

Wherein, PERp14 signal is connected to the pin E10 of CPCI Express signal plug 104 by the golden finger pin A76 of PCI Express X16 interface 102.Wherein, PERn14 signal is connected to the pin F10 of CPCI Express signal plug 104 by the golden finger pin A77 of PCI Express X16 interface 102.

Wherein, PERp15 signal is connected to the pin C10 of CPCI Express signal plug 104 by the golden finger pin A80 of PCI Express X16 interface 102.Wherein, PERn15 signal is connected to the pin D10 of CPCI Express signal plug 104 by the golden finger pin A81 of PCI Express X16 interface 102.

Described hot-swappablely exist detection signal cabling 409 and comprise PRSNT1# signal and PRSNT2# signal.

Wherein, the golden finger pin A1 (PRSNT1# signal) of PCI Express X16 the interface 102 and golden finger pin B17 of PCI Express X16 interface 102, detection signal cabling 409 is there is and is interconnected in B31, B48, B81 (PRSNT2# signal) by hot-swappable.

Described+12V direct supply covers copper I 407 by the golden finger pin B1 of+12V direct supply from PCI Express X16 interface 102, and the golden finger pin B2 of A2 and PCI Express X16 interface 102, A3 are sent to the double plug 108 of looper.

Please refer to accompanying drawing 4D, the layer 6 (L4) of described impedance control circuit plate 101, namely signals layer 2 comprises WAKE# signal lead I 402, differential reference clock (Reference clock) signal lead 403, PCI Express differential received signal cabling 408 and PCI Express Reset send signal lead 404 ,+3.3V direct supply and cover copper I 401.

Described WAKE# signal lead I 402 is connected to the double plug of looper by the golden finger pin B11 of PCI Express X16 interface 102.

Described differential reference clock signal cabling 403 comprises a pair differential signal REFCLK+ and REFCLK-.Wherein, REFCLK+ signal is connected to the pin E4 of CPCI Express signal plug 103 by the golden finger pin A13 of PCI Express X16 interface 102.Wherein, REFCLK-signal is connected to the pin F4 of CPCI Express signal plug 103 by the golden finger pin A14 of PCI Express X16 interface 102.

Described PCI Express Reset signal lead 404 comprises PERST# signal.Wherein, PERST# signal is connected to the pin B4 of CPCI Express signal plug 103 by the golden finger pin A11 of PCI ExpressX16 interface 102.

Described+3.3V direct supply covers copper I 401 by the golden finger pin A9 of+3.3V direct supply from PCIExpress X16 interface 102, and the golden finger pin A10 of A10, B8 and PCIExpress X16 interface 102 is sent to the double plug of looper.

Please refer to accompanying drawing 3, described switching circuit board 105 profile is rectangular, and thickness is 1.6mm, and contour dimension is with reference to Fig. 3, and dimensional data unit is mm.

Please refer to accompanying drawing 7, described switching circuit board 105 is two layers of switching circuit board.

Wherein, the ground floor (L1) of described switching circuit board 105 is signals layer 1, and the second layer (L2) is signals layer 2.The thickness of every layer is as shown in table 4 below.

Level number	Type	Thickness (mils)
			L1	0.6
	Central layer	60.4
			L2	0.6

Table 4

Please refer to accompanying drawing 5A, the ground floor (L1) of described switching circuit board 105, comprise+12V direct supply and cover copper II 501 ,+3.3V direct supply and cover copper II 502.

Described+12V direct supply covers copper II 501 and+12V direct supply is sent to the pin A3 of CPCI Express the supply socket 104 and pin B3 of CPCI Express supply socket 104 from double-row hole socket 107.

Described+3.3V direct supply covers+3.3V direct supply is sent to CPCI Express supply socket 104 by copper II 502 pin C4 from double-row hole socket 107, the pin D4 of CPCI Express the supply socket 104 and pin E4 of CPCI Express supply socket 104.

Please refer to accompanying drawing 5B, the ground floor (L1) of described switching circuit board 105, comprise GND and cover copper 503, WAKE# signal lead II 504.

Described WAKE# signal lead II 504 is connected to the pin D2 of CPCI Express supply socket 104 by double-row hole socket 107.

Please refer to accompanying drawing 1B, the installation steps of the described adapter for PCI Express X16 to CPCI Express X16 are as follows:

CPCI Express signal plug 103 and the double plug 108 of looper are welded on impedance control circuit plate 101.

CPCI Express supply socket 104 and double-row hole socket 107 are welded on switching circuit board 105.

Switching circuit board 105 level as shown in accompanying drawing 1A and accompanying drawing 1B is placed in impedance control circuit plate 101 top edge, and the double plug 108 of physical connection looper and double-row hole socket 107.

By contiguous block 109 and M2 screw 111, switching circuit board 105 and impedance control circuit plate 101 are connected and fixed.

By M3 screw 110, impedance control circuit plate 101 and baffle plate 106 are connected and fixed.

Claims

1. for an adapter of PCI Express X16 to CPCI Express X16, it is characterized in that: comprise an impedance control circuit plate, PCI Express X16 interface, a switching circuit board, a CPCI Express supply socket, a CPCI Express signal plug, a pair of row-hole socket, the double plug of a looper, a contiguous block, a baffle plate, three M2 screws and two M3 screws;

The lower edge of described impedance control circuit plate is furnished with PCI ExpressX16 interface, in order to carry out physical connection, transmission of signal and direct supply with PCI Express X16 slot;

Wherein, described PCI Express X16 interface is specifically arranged in the lower edge of impedance control circuit plate with the form of golden finger; Please refer to table 1, the golden finger pin on PCI Express X16 interface and signal definition as shown in table 1 below;

Table 1

The top edge of described impedance control circuit plate is furnished with CPCI Express XP3 signal plug and CPCI Express XP2 signal plug, in order to carry out physical connection, transmission of signal with CPCI Express interface card XP3 and XP2 Signal plug; XP3 please refer to table 2a, XP2 and please refer to table 2b;

Table 2a

Table 2b

The middle part to the left of described impedance control circuit plate is furnished with the double plug of looper, in order to carry out physical connection with double-row hole socket, direct supply is passed to switching circuit board from impedance control circuit plate;

Described built-up circuit plate level is fixed on the top edge of impedance control circuit plate, in order to direct supply is passed to CPCI Express supply socket from double-row hole socket;

Described CPCI Express supply socket, in order to carry out physical connection with CPCI Express interface card XP4 attaching plug, transmits direct supply;

Described impedance control circuit plate profile is L-shaped;

Described impedance control circuit plate is six layer impedance control circuit boards;

Wherein, the ground floor L1 of described impedance control circuit plate is signals layer 1, and second layer L2 is ground plane, and third layer L3 is signals layer, and the 4th layer of L4 is signals layer, and layer 5 L5 is ground plane, and layer 6 L6 is signals layer 2; Every layer and relevant thickness as shown in table 3 below;

Table 3

Wherein, for the signal lead of signals layer 1 and signals layer 2 on described impedance control circuit plate, its single-ended impedance is 50 Ω ± 10 Ω, and its differential impedance is 100 Ω ± 10 Ω;

On described impedance control circuit plate signal impedance control method be that differential signal line width is 5mil, the spacing between two signal line in a pair differential signal line is 7mil, different differential signal lines between distance be at least 20mil; The differential impedance of differential signal line is 101.8 Ω, and single-ended impedance is 51.78 Ω;

The ground floor of described impedance control circuit plate comprises System Management Bus signal lead, differential reference clock signal cabling, and PCI Express difference sends signal lead, and hot-swappable exist detection signal cabling and+12V direct supply and cover copper I;

Described System Management Bus signal lead comprises, SMCLK signal lead and SMDAT signal lead; Wherein, SMCLK signal lead is connected to the pin B3 of CPCI Express signal plug by the golden finger pin B5 of PCI Express X16 interface; Wherein, SMDAT signal lead is connected to the pin A3 of CPCI Express signal plug by the golden finger pin B6 of PCI Express X16 interface;

Described differential reference clock signal cabling comprises a pair differential reference clock signal cabling REFCLK+ and REFCLK-; Wherein, REFCLK+ signal lead is connected to the pin C4 of CPCI Express signal plug by the golden finger pin A13 of PCI Express X16 interface; Wherein, REFCLK-signal lead is connected to the pin D4 of CPCI Express signal plug by the golden finger pin A14 of PCI Express X16 interface;

Described PCI Express difference sends signal lead and comprises PETp0 and PETn0, PETp1 and PETn1, PETp2 and PETn2, PETp3 and PETn3, PETp4 and PETn4, PETp5 and PETn5, PETp6 and PETn6, PETp7 and PETn7, PETp8 and PETn8, PETp9 and PETn9, PETp10 and PETn10, PETp11 and PETn11, PETp12 and PETn12, PETp13 and PETn13, PETp14 and PETn14, PETp15 and PETn15;

Wherein, PETp0 signal lead is connected to the pin A10 of CPCI Express signal plug by the golden finger pin B14 of PCI Express X16 interface; Wherein, PETn0 signal lead is connected to the pin B10 of CPCI Express signal plug by the golden finger pin D15 of PCI Express X16 interface;

Wherein, PETp1 signal lead is connected to the pin A1 of CPCI Express signal plug by the golden finger pin B19 of PCI Express X16 interface; Wherein, PETn0 signal lead is connected to the pin B1 of CPCI Express signal plug by the golden finger pin B20 of PCI Express X16 interface;

Wherein, PETp2 signal lead is connected to the pin E1 of CPCI Express signal plug by the golden finger pin B23 of PCI Express X16 interface; Wherein, PETn2 signal lead is connected to the pin F1 of CPCI Express signal plug by the golden finger pin B24 of PCI Express X16 interface;

Wherein, PETp3 signal lead is connected to the pin A2 of CPCI Express signal plug 104 by the golden finger pin B27 of PCI Express X16 interface; Wherein, PETn3 signal lead is connected to the pin B2 of CPCI Express signal plug 104 by the golden finger pin B28 of PCI Express X16 interface 102;

Wherein, PETp4 signal lead is connected to the pin A3 of CPCI Express signal plug by the golden finger pin B33 of PCI Express X16 interface; Wherein, PETn4 signal lead is connected to the pin B3 of CPCI Express signal plug by the golden finger pin B34 of PCI Express X16 interface;

Wherein, PETp5 signal lead is connected to the pin E3 of CPCI Express signal plug by the golden finger pin B37 of PCI Express X16 interface; Wherein, PETn5 signal lead is connected to the pin F3 of CPCI Express signal plug by the golden finger pin B38 of PCI Express X16 interface;

Wherein, PETp6 signal lead is connected to the pin A4 of CPCI Express signal plug by the golden finger pin B41 of PCI Express X16 interface; Wherein, PETn6 signal lead is connected to the pin B4 of CPCI Express signal plug by the golden finger pin B42 of PCI Express X16 interface;

Wherein, PETp7 signal lead is connected to the pin A5 of CPCI Express signal plug by the golden finger pin B45 of PCI Express X16 interface; Wherein, PETn7 signal lead is connected to the pin B5 of CPCI Express signal plug by the golden finger pin B46 of PCI Express X16 interface;

Wherein, PETp8 signal lead is connected to the pin E5 of CPCI Express signal plug by the golden finger pin B50 of PCI Express X16 interface; Wherein, PETn8 signal lead is connected to the pin F5 of CPCI Express signal plug by the golden finger pin B51 of PCI Express X16 interface;

Wherein, PETp9 signal lead is connected to the pin A6 of CPCI Express signal plug by the golden finger pin B54 of PCI Express X16 interface; Wherein, PETn9 signal lead is connected to the pin B6 of CPCI Express signal plug by the golden finger pin B55 of PCI Express X16 interface;

Wherein, PETp10 signal lead is connected to the pin A7 of CPCI Express signal plug by the golden finger pin B58 of PCI Express X16 interface; Wherein, PETn10 signal lead is connected to the pin B7 of CPCI Express signal plug by the golden finger pin B59 of PCI Express X16 interface;

Wherein, PETp11 signal lead is connected to the pin E7 of CPCI Express signal plug by the golden finger pin B62 of PCI Express X16 interface; Wherein, PETn11 signal lead is connected to the pin F7 of CPCI Express signal plug by the golden finger pin B63 of PCI Express X16 interface;

Wherein, PETp12 signal lead is connected to the pin A8 of CPCI Express signal plug by the golden finger pin B66 of PCI Express X16 interface; Wherein, PETn12 signal lead is connected to the pin B8 of CPCI Express signal plug by the golden finger pin B67 of PCI Express X16 interface;

Wherein, PETp13 signal lead is connected to the pin A9 of CPCI Express signal plug by the golden finger pin B14 of PCI Express X16 interface; Wherein, PETn13 signal lead is connected to the pin B9 of CPCI Express signal plug by the golden finger pin B15 of PCI Express X16 interface;

Wherein, PETp14 signal lead is connected to the pin E9 of CPCI Express signal plug by the golden finger pin B70 of PCI Express X16 interface; Wherein, PETn14 signal lead is connected to the pin F9 of CPCI Express signal plug by the golden finger pin B71 of PCI Express X16 interface;

Wherein, PETp15 signal lead is connected to the pin A10 of CPCI Express signal plug by the golden finger pin B74 of PCI Express X16 interface; Wherein, PETn15 signal lead is connected to the pin B10 of CPCI Express signal plug by the golden finger pin B75 of PCI Express X16 interface;

Receive differential signal and comprise cabling PERp0 and PERn0, PERp1 and PERn1, PERp2 and PERn2, PERp3 and PERn3, PERp4 and PERn4, PERp5 and PERn5, PERp6 and PERn6, PERp7 and PERn7, PERp8 and PERn8, PERp9 and PERn9, PERp10 and PERn10, PERp11 and PERn11, PERp12 and PERn12, PERp13 and PERn13, PERp14 and PERn14, PERp15 and PERn15;

Wherein, PERp0 signal lead is connected to the pin C10 of CPCI Express signal plug by the golden finger pin A16 of PCI Express X16 interface; Wherein, PERn0 signal lead is connected to the pin D10 of CPCI Express signal plug by the golden finger pin A17 of PCI Express X16 interface;

Wherein, PERp1 signal lead is connected to the pin C1 of CPCI Express signal plug by the golden finger pin A21 of PCI Express X16 interface; Wherein, PERn1 signal lead is connected to the pin D1 of CPCI Express signal plug by the golden finger pin A22 of PCI Express X16 interface;

Wherein, PERp2 signal lead is connected to the pin E2 of CPCI Express signal plug by the golden finger pin A25 of PCI Express X16 interface; Wherein, PERn2 signal lead is connected to the pin F2 of CPCI Express signal plug by the golden finger pin A26 of PCI Express X16 interface;

Wherein, PERp3 signal lead is connected to the pin C2 of CPCI Express signal plug by the golden finger pin A29 of PCI Express X16 interface; Wherein, PERn3 signal lead is connected to the pin D2 of CPCI Express signal plug by the golden finger pin A30 of PCI Express X16 interface;

Wherein, PERp4 signal lead is connected to the pin C3 of CPCI Express signal plug by the golden finger pin A35 of PCI Express X16 interface; Wherein, PERn4 signal lead is connected to the pin D3 of CPCI Express signal plug by the golden finger pin A36 of PCI Express X16 interface;

Wherein, PERp5 signal lead is connected to the pin E4 of CPCI Express signal plug by the golden finger pin A39 of PCI Express X16 interface; Wherein, PERn5 signal lead is connected to the pin F4 of CPCI Express signal plug by the golden finger pin A40 of PCI Express X16 interface;

Wherein, PERp6 signal lead is connected to the pin C4 of CPCI Express signal plug by the golden finger pin A43 of PCI Express X16 interface; Wherein, PERn6 signal lead is connected to the pin D4 of CPCI Express signal plug by the golden finger pin A44 of PCI Express X16 interface;

Wherein, PERp7 signal lead is connected to the pin C4 of CPCI Express signal plug by the golden finger pin B14 of PCI Express X16 interface; Wherein, PERn7 signal lead is connected to the pin D5 of CPCI Express signal plug by the golden finger pin B15 of PCI Express X16 interface;

Wherein, PERp8 signal lead is connected to the pin E6 of CPCI Express signal plug by the golden finger pin A47 of PCI Express X16 interface; Wherein, PERn8 signal lead is connected to the pin F6 of CPCI Express signal plug by the golden finger pin A48 of PCI Express X16 interface;

Wherein, PERp9 signal lead is connected to the pin C6 of CPCI Express signal plug by the golden finger pin B14 of PCI Express X16 interface; Wherein, PERn9 signal lead is connected to the pin D6 of CPCI Express signal plug by the golden finger pin B15 of PCI Express X16 interface;

Wherein, PERp10 signal lead is connected to the pin C7 of CPCIExpress signal plug by the golden finger pin A56 of PCI Express X16 interface 102; Wherein, PERn10 signal lead is connected to the pin D7 of CPCI Express signal plug by the golden finger pin A57 of PCI Express X16 interface;

Wherein, PERp11 signal lead is connected to the pin E8 of CPCI Express signal plug by the golden finger pin A64 of PCI Express X16 interface; Wherein, PERn11 signal lead is connected to the pin F8 of CPCI Express signal plug by the golden finger pin A65 of PCI Express X16 interface;

Wherein, PERp12 signal lead is connected to the pin C8 of CPCI Express signal plug by the golden finger pin A68 of PCI Express X16 interface; Wherein, PERn12 signal lead is connected to the pin D8 of CPCI Express signal plug by the golden finger pin A69 of PCI Express X16 interface;

Wherein, PERp13 signal lead is connected to the pin C9 of CPCI Express signal plug by the golden finger pin A72 of PCI Express X16 interface; Wherein, PERn13 signal lead is connected to the pin D9 of CPCI Express signal plug by the golden finger pin A73 of PCI Express X16 interface;

Wherein, PERp14 signal lead is connected to the pin E10 of CPCI Express signal plug by the golden finger pin A76 of PCI Express X16 interface; Wherein, PERn14 signal lead is connected to the pin F10 of CPCI Express signal plug by the golden finger pin A77 of PCI Express X16 interface;

Wherein, PERp15 signal lead is connected to the pin C10 of CPCI Express signal plug by the golden finger pin A80 of PCI Express X16 interface; Wherein, PERn15 signal lead is connected to the pin D10 of CPCI Express signal plug by the golden finger pin A81 of PCI Express X16 interface;

Described hot-swappablely exist detection signal cabling and comprise PRSNT1# signal lead and PRSNT2# signal lead;

Wherein, be there is detection signal cabling be interconnected by hot-swappable in the golden finger pin A1 of PCI Express X16 interface and golden finger pin B17, B31, B48, B81 of PCI Express X16 interface;

Described+12V direct supply covers copper I and+12V direct supply is sent to the double plug of looper from golden finger pin B2, A3 of golden finger pin B1, A2 and PCI Express X16 interface of PCI Express X16 interface;

The layer 6 of described impedance control circuit plate comprises WAKE# signal lead I, differential reference clock signal cabling, and PCIExpress differential received signal cabling and PCI Express Reset send signal lead, and+3.3V direct supply covers copper I;

Described WAKE# signal lead I is connected to the double plug of looper by the golden finger pin B11 of PCI Express X16 interface;

Described differential reference clock signal cabling comprises a pair differential signal cabling REFCLK+ and REFCLK-; Wherein, REFCLK+ signal lead is connected to the pin E4 of CPCI Express signal plug by the golden finger pin A13 of PCI Express X16 interface; Wherein, REFCLK-signal lead is connected to the pin F4 of CPCIExpress signal plug by the golden finger pin A14 of PCI Express X16 interface;

Described PCI Express Reset signal lead comprises PERST# signal lead; Wherein, PERST# signal lead is connected to the pin B4 of CPCI Express signal plug by the golden finger pin A11 of PCIExpress X16 interface;

Described+3.3V direct supply covers copper I and+3.3V direct supply is sent to the double plug of looper from the golden finger pin A10 of golden finger pin A9, A10, B8 and PCI Express X16 interface of PCI Express X16 interface;

Described switching circuit board profile is rectangular, and thickness is 1.6mm;

Described switching circuit board is two layers of switching circuit board;

The ground floor of described switching circuit board, comprise+12V direct supply and cover copper II ,+3.3V direct supply covers copper II;

Described+12V direct supply covers copper II and+12V direct supply is sent to the pin A3 of CPCI Express the supply socket 104 and pin B3 of CPCI Express supply socket from double-row hole socket;

Described+3.3V direct supply covers+3.3V direct supply is sent to CPCI Express supply socket by copper II pin C4 from double-row hole socket, the pin D4 of CPCI Express supply socket and the pin E4 of CPCI Express supply socket;

The second layer of described switching circuit board, comprises GND and covers copper, WAKE# signal lead II;

Described WAKE# signal lead II is connected to the pin D2 of CPCI Express supply socket by double-row hole socket;

The installation steps of the described adapter for PCI Express X16 to CPCI Express X16 are as follows:

CPCI Express signal plug and the double plug of looper are welded on impedance control circuit plate;

CPCI Express supply socket and double-row hole socket are welded on switching circuit board;

Built-up circuit plate level is placed in impedance control circuit plate top edge, and the double plug of physical connection looper and double-row hole socket;

By contiguous block and M2 screw, switching circuit board and impedance control circuit plate are connected and fixed;

By M3 screw, impedance control circuit plate and baffle plate are connected and fixed.