CN114020668B - Signal processing system, mainboard and server - Google Patents
Signal processing system, mainboard and server Download PDFInfo
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- CN114020668B CN114020668B CN202111164877.0A CN202111164877A CN114020668B CN 114020668 B CN114020668 B CN 114020668B CN 202111164877 A CN202111164877 A CN 202111164877A CN 114020668 B CN114020668 B CN 114020668B
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- 238000012545 processing Methods 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 7
- IHIDFKLAWYPTKB-UHFFFAOYSA-N 1,3-dichloro-2-(4-chlorophenyl)benzene Chemical compound C1=CC(Cl)=CC=C1C1=C(Cl)C=CC=C1Cl IHIDFKLAWYPTKB-UHFFFAOYSA-N 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- JHBVPKZLIBDTJR-UHFFFAOYSA-N 1,2-dichloro-4-(3-chlorophenyl)benzene Chemical compound ClC1=CC=CC(C=2C=C(Cl)C(Cl)=CC=2)=C1 JHBVPKZLIBDTJR-UHFFFAOYSA-N 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
Abstract
The application discloses signal processing system, mainboard and server, include: the PCIe connector is arranged on the main board and connected with a PCIe port of the CPU on the main board; the first cable is used for detachably connecting the OCP equipment with the PCIe connector, and the PCIe connector is provided with a processing module for processing sideband signals of the OCP equipment; and the NVME device is detachably connected with the PCIe connector through the second cable, and the second cable is provided with an address module for indicating address information of PCIe signals sent to the NVME device. According to the method and the device, the connection of the same PCIe port on the CPU of the main board and the connection of the OCP3.0 network card and the NVME backboard can be simultaneously compatible, the main board can support more NVME hard disks, and the requirement of higher configuration of clients is met.
Description
Technical Field
The present disclosure relates to the field of servers, and in particular, to a signal processing system, a motherboard, and a server.
Background
With the rapid development of computer technology, informatization gradually covers various fields of society, and demands for performance and flexibility of applications of servers are increasing. For the server, the rapid development of network technology makes higher demands on application and types of network card devices of the server, so that an OCP (Open Compute Project, open source computing item) NIC (Network Interface Card ) appears in the field of view of people, an OCP NIC 3.0 network card also becomes a configuration item of a server standard, and for storage technology, NVME (Non-Volatile Memory Express, non-volatile memory host controller interface specification) is increasingly and widely applied to computer products, because of the appearance of NVME, the performance of a hard Disk is greatly improved, and an SSD (Solid State Disk) of the NVME also becomes a mainstream configuration of the server.
Referring to fig. 1, PCIe Port0 PCIe signals and power, NCSI (Network Controller Sideband Interface ) signals on the motherboard and other sideband signals are connected to a 4c+ connector, and the OCP network card is directly plugged into the connector through a gold finger, if NVME needs to be supported simultaneously, another PCIe Port needs to be led out, that is, PCIe (Peripheral Component Interconnect Express, high speed serial computer expansion bus standard) signals and NVME address signals on PCIe Port1 are connected to an X8 slot connector, and then connected to the NVME backplane through a cable, so that an NVME function is implemented.
Therefore, how to provide a solution to the above technical problem is a problem that a person skilled in the art needs to solve at present.
Disclosure of Invention
The purpose of the application is to provide a signal processing system, a main board and a server, which can realize the connection of the same PCIe port on the CPU of the main board and the connection of an OCP3.0 network card and an NVME backboard, and the main board can support more NVME hard disks, thereby meeting the requirement of higher configuration of clients.
In order to solve the above technical problem, the present application provides a signal processing system, including:
the PCIe connector is arranged on the main board and connected with a PCIe port of the CPU on the main board;
the first cable is used for detachably connecting the OCP equipment with the PCIe connector, and the PCIe connector is provided with a processing module for processing sideband signals of the OCP equipment;
and the NVME device is detachably connected with the PCIe connector through the second cable, and the second cable is provided with an address module for indicating address information of PCIe signals sent to the NVME device.
Optionally, the first cable is a triple cable, a first end of the first cable is connected with the OCP device, a second end of the first cable is connected with the power module on the motherboard, a third end of the first cable is connected with the out-of-band management module on the motherboard, and a fourth end of the first cable is connected with the PCIe connector.
Optionally, the first end of the first cable is connected to the OCP device through a 4c+ connector.
Optionally, the second cable further includes a first gold finger, a second gold finger, a first bonding pad, a second bonding pad, a first PCB board and a second PCB board, wherein:
the first golden finger is connected with the NVME device, the second golden finger is connected with the PCIe connector, the first bonding pad is connected with the first PCB, the first PCB is connected with the first golden finger, the second bonding pad is connected with the second PCB, the second PCB is connected with the second golden finger, and the address module is arranged on the first PCB.
Optionally, the power supply end of the address module is connected with the p3v3_stby end on the motherboard, and the ground end of the address module is connected with the ground end on the motherboard.
Optionally, the address module includes a pull-up resistor unit and a pull-down resistor unit.
In order to solve the above technical problems, the present application further provides a motherboard, including the signal processing system as described in any one of the above.
In order to solve the technical problem, the application further provides a server, which comprises the main board.
The application provides a signal processing system comprising: the PCIe connector is arranged on the main board and connected with a PCIe port of the CPU on the main board; the first cable is used for detachably connecting the OCP equipment with the PCIe connector, and the PCIe connector is provided with a processing module for processing sideband signals of the OCP equipment; and the NVME device is detachably connected with the PCIe connector through the second cable, and the second cable is provided with an address module for indicating address information of PCIe signals sent to the NVME device.
In practical application, adopt the scheme of this application, OCP equipment adopts first cable and mainboard connection, compare more nimble on OCP cut straightly to the mainboard, this application can no longer be limited by the restriction of mechanism and realize the OCP function, the sideband signal of OCP no longer uses an independent connector simultaneously, but put these signals to the PCIe connector on the mainboard above realize, can make full use of connector's space like this, reduce the use of connector on the mainboard, more save the cost, set up NVME address signal processing and realize on the second cable, can more nimble use on the mainboard, can compatible OCP3.0 network card's connection and NVME backplate's connection under the same PCIe port on the CPU of mainboard, the mainboard can support more NVME hard disks, satisfy the higher requirement of configuration of customer.
The application also provides a mainboard and a server, which have the same beneficial effects as the signal processing system.
Drawings
For a clearer description of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a connection between a motherboard and NVME and OCP devices in the prior art;
fig. 2 is a schematic structural diagram of a signal processing system provided in the present application
Fig. 3 is a schematic structural diagram of connection between an OCP device and a motherboard provided in the present application;
fig. 4 is a schematic structural diagram of connection between an NVME device and a motherboard;
fig. 5 is a schematic structural diagram of a second cable provided in the present application.
Detailed Description
The core of the application is to provide a signal processing system, a main board and a server, which can realize the connection of the same PCIe port on the CPU of the main board and the connection of the NVME backboard and the OCP3.0 network card simultaneously, and the main board can support more NVME hard disks and meet the requirement of higher configuration of clients.
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a signal processing system provided in the present application, where the signal processing system includes:
a PCIe connector 1 arranged on the main board and connected with a PCIe port of the CPU on the main board;
the first cable 2, the OCP device is detachably connected with the PCIe connector 1 through the first cable 2, and the PCIe connector 1 is provided with a processing module 21 for processing sideband signals of the OCP device;
and the NVME device is detachably connected with the PCIe connector 1 through the second cable 3, and the second cable 3 is provided with an address module for indicating address information of PCIe signals sent to the NVME device.
Specifically, the connector disposed on the motherboard is specifically a SLIMLINE connector, one end of the connector is connected with a PCIe port of the CPU on the motherboard for transmitting PCIe signals, and in this embodiment, the OCP device and the NVME device are connected with the SLIMLINE connector through a first cable 2 and a second cable 3 respectively.
As an alternative embodiment, referring to fig. 3, fig. 3 is a schematic diagram of connection of the OCP device to the motherboard through the first cable 2, where the first cable 2 is a triple cable, a first end of the first cable 2 is provided with a 4c+ connector for connecting the OCP device, a second end of the first cable 2 is connected to a POWER module POWER on the motherboard, a third end of the first cable 2 is connected to an out-of-band management module NCSI on the motherboard, and a fourth end of the first cable 2 is connected to the connector. Compared with the scheme that the OCP device is directly plugged into the main board, the scheme of the embodiment is more flexible, the OCP function can be realized without being limited by the limit of a mechanism, in addition, regarding the sideband signals of the OCP device, a processing module 21 for processing the sideband signals of the OCP device is arranged on the PCIe connector 1, a separate connector is not used, and the sideband signals are placed on the PCIe slimline connector, so that the space of the slimline connector can be fully utilized, the use of the connector on the main board is reduced, and the cost is saved.
It should be noted that, the signals of the NVME are divided into two parts, one part is a PCIe signal, the other part is an NVME address signal, and the NVME address signal comprises CPU_ADDR [2:0] and VPP_ADDR [3:0], wherein CPU_ADDR represents which CPU the PCIe signal connected to the NVME comes from, and VPP_ADDR represents which PCIe port under the CPU the PCIe signal connected to the NVME comes from. For example, we define CPU_ADDR [2:0] to be 000 to represent CPU0, VPP_ADDR [3:0] to be 0000 to represent PCIe port0, and NVME ADDRESS signal to CPLD of the backplane, then if CPLD recognizes NVME ADDRESS as 000_0000, then NVME hard disk in the CPU0_PE0 position can be located.
Normally, if designed separately, both of these partial signals would be placed on top of the PCIe slot connector as shown in the NVME section of fig. 1, but such a connection would not be satisfactory as required by the compatible OCP and NVME, since the spare locations on the PCIe slot connector other than the part of the PCIe signal would already be occupied by the OCP sideband signal, and the NVME address signal would not be connected to the PCIe slot connector. In order to realize the connection of the OCP3.0 network card and the requirement of NVME compatible under the same PCIe port, the embodiment designs the NVME address signal to the upper surface of the NVME cable, namely the upper surface of the second cable 3.
As an alternative embodiment, referring to fig. 4, the second cable 3 further includes a first gold finger 31, a second gold finger 36, a first pad 33, a second pad 34, a first PCB board 32, and a second PCB board 35, wherein: the first golden finger 31 is connected with NVME equipment, the second golden finger 36 is connected with the connector, the first bonding pad 33 is connected with the first PCB 32, the first PCB 32 is connected with the first golden finger 31, the second bonding pad 34 is connected with the second PCB 35, the second PCB 35 is connected with the second golden finger 36, and the address module is arranged on the first PCB 32. The first PCB 32 is shown in fig. 5, and the address module is composed of a pull-up resistor and a pull-down resistor.
Specifically, the PCIe SLIMLIN connector at the motherboard end has p3v3_stby and GND at the position of the mis, the second cable 3 has a small PCB board at the end of the butted NVME backplane, and the first PCB board 32, the first pad 33 is on the left side of the first PCB board 32, the second PCB board 35 connected to the end of the butted motherboard of the second cable 3, the first golden finger 31 is on the right side of the first PCB board 32, and the first PCB board 32 is connected to the slimline connector of the NVME backplane. The P3V3_STBY and GND on the main board are led into the first PCB 32 where the second cable 3 is connected with the NVME back board end instead of being directly connected with the golden finger, the first PCB 32 of the second cable 3 is respectively connected with the address signals of CPU_ADDR [2:0], VPP_ADDR [3:0] to the P3V3_STBY and GND through pull-up resistors, and then the address signals of CPU_ADDR [2:0], VPP_ADDR [3:0] are connected with the golden finger where the second cable 3 is connected with the NVME back board end.
In summary, through the design of special cables and connection modes, the connection of the OCP3.0 network card and the connection of the NVME backboard can be compatible at the same time under the same PCIe PORT, and the main board can support more NVME hard disks.
The application provides a signal processing system comprising: the PCIe connector is arranged on the main board and connected with the PCIe port of the CPU on the main board; the first cable is used for detachably connecting the OCP equipment with the PCIe connector, and the PCIe connector is provided with a processing module for processing sideband signals of the OCP equipment; and the NVME device is detachably connected with the PCIe connector through the second cable, and the second cable is provided with an address module for indicating address information of PCIe signals sent to the NVME device.
In another aspect, the present application further provides a motherboard, including a signal processing system as defined in any one of the above.
For an introduction to a motherboard provided in the present application, refer to the above embodiment, and the description is omitted herein.
The mainboard has the same beneficial effects as the signal processing system.
In another aspect, the present application also provides a server including a motherboard as above.
For an introduction to a server provided in the present application, reference is made to the above embodiments, and the description is omitted herein.
The server provided by the application has the same beneficial effects as the signal processing system.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. A signal processing system, comprising:
the PCIe connector is arranged on the main board and connected with a PCIe port of the CPU on the main board;
the first cable is used for detachably connecting the OCP equipment with the PCIe connector, and the PCIe connector is provided with a processing module for processing sideband signals of the OCP equipment;
the NVME device is detachably connected with the PCIe connector through the second cable, and the second cable is provided with an address module for indicating address information of PCIe signals sent to the NVME device;
the first cable is a triple cable, a first end of the first cable is connected with the OCP equipment, a second end of the first cable is connected with a power module on the main board, a third end of the first cable is connected with an out-of-band management module on the main board, and a fourth end of the first cable is connected with the PCIe connector;
the second cable still includes first golden finger, second golden finger, first pad, second pad, first PCB board and second PCB board, wherein:
the first golden finger is connected with the NVME device, the second golden finger is connected with the PCIe connector, the first bonding pad is connected with the first PCB, the first PCB is connected with the first golden finger, the second bonding pad is connected with the second PCB, the second PCB is connected with the second golden finger, and the address module is arranged on the first PCB.
2. The signal processing system of claim 1, wherein the first end of the first cable is connected to the OCP device via a 4c+ connector.
3. The signal processing system of claim 1, wherein a power supply terminal of the address module is connected to a p3v3_stby terminal on the motherboard, and a ground terminal of the address module is connected to a ground terminal on the motherboard.
4. A signal processing system according to any of claims 1-3, wherein the address module comprises a pull-up resistor unit and a pull-down resistor unit.
5. A motherboard comprising a signal processing system as claimed in any one of claims 1 to 4.
6. A server comprising the motherboard of claim 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111164877.0A CN114020668B (en) | 2021-09-30 | 2021-09-30 | Signal processing system, mainboard and server |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111164877.0A CN114020668B (en) | 2021-09-30 | 2021-09-30 | Signal processing system, mainboard and server |
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| Publication Number | Publication Date |
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| CN114020668A CN114020668A (en) | 2022-02-08 |
| CN114020668B true CN114020668B (en) | 2024-02-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202111164877.0A Active CN114020668B (en) | 2021-09-30 | 2021-09-30 | Signal processing system, mainboard and server |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN209640782U (en) * | 2019-04-12 | 2019-11-15 | 深圳市同泰怡信息技术有限公司 | A kind of PCIE expansion card of NVMe hard-disk interface |
| CN110502462A (en) * | 2019-08-09 | 2019-11-26 | 苏州浪潮智能科技有限公司 | A kind of OCP adapter and server |
| CN212571566U (en) * | 2020-06-17 | 2021-02-19 | 安费诺电子装配（厦门）有限公司 | Hybrid cable connector and connector assembly |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWM584035U (en) * | 2019-06-18 | 2019-09-21 | 貝爾威勒電子股份有限公司 | Plug connector with protective member for replacing gold finger of circuit board |
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2021
- 2021-09-30 CN CN202111164877.0A patent/CN114020668B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN209640782U (en) * | 2019-04-12 | 2019-11-15 | 深圳市同泰怡信息技术有限公司 | A kind of PCIE expansion card of NVMe hard-disk interface |
| CN110502462A (en) * | 2019-08-09 | 2019-11-26 | 苏州浪潮智能科技有限公司 | A kind of OCP adapter and server |
| CN212571566U (en) * | 2020-06-17 | 2021-02-19 | 安费诺电子装配（厦门）有限公司 | Hybrid cable connector and connector assembly |
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| Publication number | Publication date |
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| CN114020668A (en) | 2022-02-08 |
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