CN210839522U

CN210839522U - Clear CMOS trigger circuit, mainboard and computer

Info

Publication number: CN210839522U
Application number: CN201922359310.3U
Authority: CN
Inventors: 常正中; 肖瑞彬
Original assignee: Nanjing Weizhi New Technology Co ltd
Current assignee: Nanjing Weizhi New Technology Co ltd
Priority date: 2019-12-24
Filing date: 2019-12-24
Publication date: 2020-06-23
Anticipated expiration: 2029-12-24

Abstract

The utility model discloses a clear CMOS trigger circuit, including first switch module, second switch module and time delay module, the first switch-on end of first switch module connects the conduction control end of second switch module, and its second conduction end is ground connection, and its conduction control end is used for connecting the start button of computer; the first conduction end of the second switch module is used for connecting the clear CMOS control end of the south bridge, and the second conduction end of the second switch module is grounded; the delay end of the delay module is connected with the first conducting end of the first switch module; when the startup key is kept in a pressed state, the first switch module is switched off, the voltage of the delay end of the delay module is gradually increased, when the voltage of the delay end is increased to be larger than the conduction threshold value of the second switch module, the second switch module is switched on, and the first conduction end of the second switch module pulls down the clear CMOS control end of the south bridge, so that the computer clears the CMOS. The utility model discloses still disclose a computer. The utility model discloses it is more convenient to make the user clear CMOS operation.

Description

Clear CMOS trigger circuit, mainboard and computer

Technical Field

The utility model relates to a computer circuit field, in particular to clear CMOS trigger circuit, mainboard and computer.

Background

The CMOS is an important chip in the computer, the CMOS parameters record important resource configuration parameters of the computer, when the CMOS parameters are set incorrectly, the computer cannot be normally started, and at this time, the computer needs to be recovered to be normally started by manually cleaning the CMOS. At present, the way of manually clearing the CMOS by a computer is generally: 1. cutting off the power supply of the computer host, then opening the case to take down the lithium battery for supplying power to the CMOS or short-circuit to clear the CMOS jump cap; 2. a key for triggering and executing COMS clearing processing is additionally arranged on a computer host case. The first manual CMOS cleaning mode is troublesome to operate, and for most of ordinary users, the operation mode is not clear, so that the users can directly perform after-sales maintenance as failure reports, and the maintenance workload of manufacturers is increased; the second method requires additional openings in the chassis, which may affect the appearance of the whole device.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a clear CMOS trigger circuit, mainboard and computer aims at convenience of customers and carries out manual clear CMOS operation, and does not influence the computer outward appearance.

In order to achieve the above object, the present invention provides a clear CMOS trigger circuit for a computer, which includes a first switch module, a second switch module and a delay module, wherein the first switch module and the second switch module each have a first conducting terminal, a second conducting terminal and a conducting control terminal; the first conduction end of the first switch module is connected with the conduction control end of the second switch module, the second conduction end of the first switch module is grounded, and the conduction control end of the first switch module is used for being connected with a starting button of a computer and receiving a low level generated by pressing the starting button; the first conduction end of the second switch module is used for connecting a clear CMOS control end of a south bridge, and the second conduction end of the second switch module is grounded; the delay end of the delay module is connected with the first conducting end of the first switch module;

when the startup key is kept pressed, the first switch module receives a low level generated by pressing the startup key, the first conduction end of the first switch module is disconnected with the second conduction end of the first switch module, the voltage of the delay end of the delay module gradually rises, when the voltage of the delay end rises to be larger than the conduction threshold value of the second switch module, the second switch module is conducted, the first conduction end of the second switch module is conducted with the second conduction end of the second switch module and grounded, and the first conduction end of the second switch module pulls down the CMOS clearing control end of the south bridge, so that the computer clears CMOS.

Preferably, the first switch module is a first switch tube, and the second switch module is a second switch tube.

Preferably, the first switch tube is a first NMOS tube, and the conduction control end, the first conduction end and the second conduction end of the first switch tube are respectively a gate, a drain and a source of the first NMOS tube; the second switch tube is a second NMOS tube, and the conduction control end, the first conduction end and the second conduction end of the second switch tube are respectively a grid electrode, a drain electrode and a source electrode of the second NMOS tube.

Preferably, the delay module includes a delay resistor and a delay capacitor, one end of the delay resistor is connected to the power supply, the other end of the delay resistor is the delay end of the delay module, one end of the delay capacitor is connected to the delay end, and the other end of the delay capacitor is grounded.

Preferably, the clear CMOS trigger circuit further includes a first resistor, the first resistor is connected in series to the first conducting terminal of the second switch module, and the first conducting terminal of the second switch module is used to connect the clear CMOS control terminal of the south bridge through the first resistor.

The utility model also provides a mainboard, including start button, south bridge and clear CMOS trigger circuit, clear CMOS trigger circuit includes first switch module, second switch module and time delay module, first switch module and second switch module all have first conduction end, second conduction end and conduction control end; the first conduction end of the first switch module is connected with the conduction control end of the second switch module, the second conduction end of the first switch module is grounded, and the conduction control end of the first switch module is connected with the starting button and receives a low level generated by pressing the starting button; the first conduction end of the second switch module is used for connecting the clear CMOS control end of the south bridge, and the second conduction end of the second switch module is grounded; the delay end of the delay module is connected with the first conducting end of the first switch module;

The utility model also provides a computer, including the mainboard, the mainboard includes start button, south bridge and clear CMOS trigger circuit, clear CMOS trigger circuit includes first switch module, second switch module and time delay module, first switch module and second switch module all have first conduction end, second conduction end and conduction control end; the first conduction end of the first switch module is connected with the conduction control end of the second switch module, the second conduction end of the first switch module is grounded, and the conduction control end of the first switch module is connected with the starting button and receives a low level generated by pressing the starting button; the first conduction end of the second switch module is used for connecting the clear CMOS control end of the south bridge, and the second conduction end of the second switch module is grounded; the delay end of the delay module is connected with the first conducting end of the first switch module;

The technical scheme of the utility model, adopt the mode of pressing the start button for a long time to produce the low level and give the clear CMOS control end of south bridge, make the south bridge control computer clear CMOS, and can not trigger clear CMOS to handle by mistake when pressing the start button for a short time, have guaranteed the original normal start function of start button; compared with the existing mode, the CMOS can be cleared only by keeping the starting-up key in a pressed state for more than a period of time (for example, 0.5 second), the case does not need to be disassembled, the operation is convenient and simple, the starting-up key of the computer is adopted for triggering, a new key does not need to be additionally arranged on the case, the integral attractiveness of the computer is ensured, and the corresponding cost for additionally arranging the key is saved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

FIG. 1 is a block diagram of a preferred embodiment of the CMOS trigger circuit of the present invention;

fig. 2 is a circuit diagram of a preferred embodiment of the CMOS trigger circuit of the present invention.

The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

It should be noted that all the directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.

The utility model provides a clear CMOS trigger circuit of computer can be applied to products such as desktop mainboard, industrial computer mainboard, all-in-one.

Referring to fig. 1, the CMOS flip-flop circuit of this embodiment includes a first switch module 11, a second switch module 12 and a delay module 13, where the first switch module 11 has a first conducting terminal a1, a second conducting terminal a2 and a conducting control terminal A3, and the second switch module 12 also has a first conducting terminal B1, a second conducting terminal B2 and a conducting control terminal B3. The first conduction end a1 of the first switch module 11 is connected to the conduction control end B3 of the second switch module 12, the second conduction end a2 of the first switch module 11 is grounded, and the conduction control end A3 of the first switch module 11 is used for connecting the power-on key 20 of the computer and receiving a low level generated by pressing the power-on key 20; the first conducting terminal B1 of the second switch module 12 is used to connect the clean CMOS control terminal W of the south bridge 30 (the clean CMOS control terminal W of the south bridge 30 is used to control the computer to execute clean CMOS processing, and is triggered at low level), and the second conducting terminal B2 of the second switch module 12 is grounded; the delay terminal Y of the delay module 13 is connected to the first conducting terminal a1 of the first switch module 11.

The working condition of the clear CMOS trigger circuit in this embodiment in a computer is: after the computer is powered on, the power-on key 20 is at a high level, the conduction control end A3 of the first switch module 11 is at a high level, the first switch module 11 is turned on, the first conduction end a1 and the second conduction end a2 of the first switch module 11 are conducted and grounded, the delay module 13 is also just powered on and works, and the potential of the delay end Y is not yet pulled high, so the first conduction end a1 of the first switch module 11 is directly pulled down to a low level by grounding, the conduction control end B3 of the second switch module 12 (connected with the first conduction end a1 of the first switch module 11) is also at a low level, the second switch module 12 is not conducted, the first conduction end B1 of the second switch module 12 is not pulled down, the clear CMOS control end W of the south bridge 30 does not receive a low level signal, and no CMOS clear operation of the computer is performed. When the power-on key 20 is pressed, a low level is generated at the power-on key 20, the first switch module 11 receives the low level generated when the power-on key 20 is pressed, the first switch module 11 is not conducted, that is, the first conducting end a1 of the first switch module 11 is disconnected from the second conducting end a2 thereof, at this time, the delay end Y of the delay module 13 is not grounded, but due to the delay action of the delay module 13, the voltage of the delay end Y thereof does not immediately become a high level voltage, but gradually and slowly rises, so the conduction control end B3 of the second switch module 12 does not immediately become a high level at the moment when the power-on key 20 is pressed, that is, the second switch module 12 is not immediately conducted, a low level cannot be generated to the south bridge CMOS control end W of the south bridge 30, that is, that the power-on operation of the computer cannot falsely trigger a CMOS clearing action; when the power-on key 20 is kept pressed, the voltage at the delay terminal Y of the delay module 13 gradually increases, after the power-on key 20 is kept pressed for a certain period of time (for example, 0.5 second), the voltage at the delay terminal Y increases to be greater than the conduction threshold of the second switch module 12, the second switch module 12 is turned on, the first conduction terminal B1 of the second switch module 12 and the second conduction terminal B2 thereof are turned on and grounded, and the first conduction terminal B1 of the second switch module 12 pulls the CMOS clearing control terminal W of the south bridge 30 down, which only makes the computer perform CMOS clearing operation.

The clear CMOS trigger circuit of this embodiment generates a low level to the clear CMOS control terminal W of the south bridge 30 by pressing the power button 20 for a long time, so that the south bridge 30 controls the computer to clear CMOS, and the clear CMOS processing is not erroneously triggered when the power button 20 is pressed for a short time, thereby ensuring the original normal power function of the power button 20; compared with the existing mode, the method can clear the CMOS only by keeping the starting-up key 20 in a pressed state for more than a period of time (for example, 0.5 second), does not need to disassemble the case, is convenient and simple to operate, adopts the starting-up key 20 of the computer to trigger, does not need to add a new key on the case, ensures the whole machine aesthetic property of the computer, and saves the corresponding cost of adding the key.

Further, in this embodiment, it is preferable that the first switch module 11 is a first switch tube, and the second switch module 12 is a second switch tube. Of course, in other embodiments, the first switch module 11 and the second switch module 12 may also be other circuits or switch devices that perform the same function as the switch tube performs.

Referring to fig. 2, in the present embodiment, the first switch transistor is a first NMOS transistor Q1, and the turn-on control terminal A3, the first turn-on terminal a1 and the second turn-on terminal a2 of the first switch transistor are respectively a gate, a drain and a source of the first NMOS transistor Q1; the second switch tube is a second NMOS tube Q2, and the turn-on control terminal B3, the first turn-on terminal B1 and the second turn-on terminal B2 of the second switch tube are respectively a gate, a drain and a source of the second NMOS tube Q2. It should be noted that, in this embodiment, it is only preferable to adopt the example that the first switching tube and the second switching tube are both NMOS tubes, and in other embodiments, the first switching tube and the second switching tube may also be other types of MOS tubes or other types of switching tubes (for example, a triode).

Further, referring to fig. 2, the delay module 13 of this embodiment includes a delay resistor Rs and a delay capacitor C, one end of the delay resistor Rs is connected to the power supply, the other end of the delay resistor Rs is the delay end Y of the delay module 13, one end of the delay capacitor C is connected to the delay end Y, and the other end of the delay capacitor C is grounded. The delay module 13 in this embodiment preferably adopts an RC delay circuit composed of a delay resistor Rs and a delay capacitor C as an example, and of course, in other embodiments, the delay module 13 may also be a delay circuit composed of other elements and having the same function as the RC delay circuit.

With reference to fig. 1 and fig. 2, the specific operating principle of the CMOS trigger circuit of this embodiment is as follows: 1. after the computer is powered on, the gate of the first NMOS transistor Q1 is at a high level, the first NMOS transistor Q1 is turned on, the drain and the source of the first NMOS transistor Q1 are turned on and grounded, at this time, the RC delay circuit is just powered on, the delay capacitor C is just charged and then discharged by the drain of the first NMOS transistor Q1 being grounded, and the delay terminal Y is always kept at a low level state, so that the drain potential of the first NMOS transistor Q1 is directly pulled to a low level by the grounded state of the source thereof, and thus the gate of the second NMOS transistor Q2 is also at a low level, the second NMOS transistor Q2 is not turned on, and no low level is provided to the clear CMOS control terminal W of the south bridge 30, and the computer does not perform clear CMOS operation. 2. When the power-on key 20 is pressed to generate a low level, the first NMOS transistor Q1 is turned from on to off, the drain of the first NMOS is no longer grounded, the delay capacitor C starts to be charged by the power supply Vcc, the voltage of the delay terminal Y gradually increases (i.e., the drain voltage of the first NMOS transistor Q1 gradually increases), if the power-on key 20 is released (when a user only performs the power-on operation, the user only presses the power-on key 20 to release), the first NMOS transistor Q1 is turned on again, the delay capacitor C is turned from the charging state to the discharging state, the voltage of the delay terminal Y is still greater than the conducting voltage (0.7V) of the second NMOS transistor Q2, the second NMOS transistor Q2 is still off, no low level is provided for the clean CMOS control terminal W of the south bridge 30, and the computer does not perform the clean CMOS operation. 3. When the power-on key 20 is kept pressed, the power-on key 20 continuously provides a low level to the gate of the first NMOS transistor Q1, the first NMOS transistor Q1 is always kept in a non-conducting state, and the delay capacitor C is continuously charged, when the power-on key 20 is kept pressed for a certain time (for example, 0.5 second), the delay capacitor C is charged to a voltage higher than the conducting voltage of the second NMOS transistor Q2 (i.e., the voltage of the delay terminal Y is higher than the conducting voltage of the second NMOS transistor Q2), the second NMOS transistor Q2 is conducted, the drain and the source of the second NMOS transistor Q2 are conducted to the ground, the second NMOS transistor Q2 generates a low level to the CMOS clearing control terminal W of the south bridge 30, and the computer executes CMOS clearing operation.

As can be seen from the above, the clear CMOS trigger circuit of the embodiment has a simple circuit structure, few components, low cost, and simple operation for executing clear CMOS triggering, and only needs to press the start button 20 for a long time, although the start button 20 is shared for triggering, the normal start function of the start button 20 is not affected.

Further, the clear CMOS trigger circuit of this embodiment further includes a first resistor R1, the first resistor R1 is connected in series to the first conducting terminal of the second switch module 12, the first conducting terminal B1 of the second switch module 12 is used to connect the clear CMOS control terminal W of the south bridge 30 through the first resistor R1, that is, the first resistor is connected in series to the drain of the second NMOS transistor Q2, and the first resistor R1 is connected in series between the first conducting terminal B1 of the second switch module 12 and the clear CMOS control terminal W, so as to ensure the stability of the potential of the clear CMOS control terminal W.

The utility model discloses still provide a mainboard, including start button, south bridge and clear CMOS trigger circuit, this clear CMOS trigger circuit's circuit structure can refer to above-mentioned embodiment, because this mainboard includes the above-mentioned technical scheme who clears all embodiments of CMOS trigger circuit, consequently has all beneficial effects that the technical scheme of above-mentioned embodiment brought at least, does not do here and gives unnecessary detail.

The utility model discloses still provide a computer, including above-mentioned mainboard, the event this computer includes the technical scheme of the clear all embodiments of CMOS trigger circuit of the aforesaid, consequently has all beneficial effects that the technical scheme of above-mentioned embodiment brought at least, does not do here and describe repeatedly.

The above is only the preferred embodiment of the present invention, and the patent scope of the present invention is not limited thereby, all the equivalent structure changes made by the contents of the specification and the drawings are utilized under the inventive concept of the present invention, or the direct/indirect application in other related technical fields is included in the patent protection scope of the present invention.

Claims

1. A clear CMOS trigger circuit of a computer is characterized by comprising a first switch module, a second switch module and a delay module, wherein the first switch module and the second switch module are respectively provided with a first conduction end, a second conduction end and a conduction control end; the first conduction end of the first switch module is connected with the conduction control end of the second switch module, the second conduction end of the first switch module is grounded, and the conduction control end of the first switch module is used for being connected with a starting button of a computer and receiving a low level generated by pressing the starting button; the first conduction end of the second switch module is used for connecting a clear CMOS control end of a south bridge, and the second conduction end of the second switch module is grounded; the delay end of the delay module is connected with the first conducting end of the first switch module;

2. The CMOS trigger circuit of claim 1, wherein the first switch module is a first switch transistor and the second switch module is a second switch transistor.

3. The CMOS trigger circuit of claim 2, wherein the first switch tube is a first NMOS tube, and the conduction control end, the first conduction end and the second conduction end of the first switch tube are respectively a gate, a drain and a source of the first NMOS tube; the second switch tube is a second NMOS tube, and the conduction control end, the first conduction end and the second conduction end of the second switch tube are respectively a grid electrode, a drain electrode and a source electrode of the second NMOS tube.

4. The CMOS trigger circuit according to any one of claims 1 to 3, wherein the delay module comprises a delay resistor and a delay capacitor, one end of the delay resistor is connected to a power supply, the other end of the delay resistor is a delay end of the delay module, one end of the delay capacitor is connected to the delay end, and the other end of the delay capacitor is grounded.

5. The CMOS flip-flop circuit of claim 4, further comprising a first resistor connected in series to the first conducting terminal of said second switch module, said first conducting terminal of said second switch module being configured to connect to the CMOS control terminal of said south bridge via said first resistor.

6. A motherboard comprising a power-on key and a south bridge, wherein the motherboard further comprises the CMOS flip-flop circuit according to any one of claims 1 to 5.

7. A computer, characterized by comprising the main board of claim 6.