CN210837172U - Large-capacity solid state disk - Google Patents
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- CN210837172U CN210837172U CN201921725869.7U CN201921725869U CN210837172U CN 210837172 U CN210837172 U CN 210837172U CN 201921725869 U CN201921725869 U CN 201921725869U CN 210837172 U CN210837172 U CN 210837172U
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Abstract
The utility model provides a large capacity solid state hard drives, including SATA interface, redundant module of disk and two hard disk controllers, SATA interface connection redundant module of disk, first hard disk controller, second hard disk controller all are connected with the redundant module of disk, and each hard disk controller all is connected with polylith storage chip. The utility model discloses a redundant technique of disk carries on two hard disk controllers in solid state hard drives to realize the multiplication of solid state hard drive capacity, realize the design based on the dual control ware standard large capacity solid state hard drives of redundant technique of disk.
Description
Technical Field
The utility model belongs to the technical field of solid-state storage device design technique and specifically relates to a large capacity solid state hard drives is related to.
Background
With the continuous development of information technology, solid state disks gradually replace traditional mechanical hard disks due to high performance and low latency, and become the first choice of mainstream computer architecture storage components. However, due to the special electronic architecture of the solid state disk, which is limited by the development of the controller and the Flash, the current mainstream solid state disk has a certain difference from the mechanical hard disk, and how to realize the multiplication of the solid state disk capacity becomes a problem to be solved urgently.
SUMMERY OF THE UTILITY MODEL
To the defect that exists among the prior art, the utility model provides a large capacity solid state hard drives. The utility model provides a carry on dual control ware storage to current solid state hard drives through the redundant technique of disc to realize the multiplication of solid state hard drive capacity, realize the design based on the dual control ware standard large capacity solid state hard drives of the redundant technique of disc.
In order to achieve the technical purpose, the utility model discloses a specific technical scheme as follows:
a high-capacity solid state disk comprises double hard disk controllers, wherein each hard disk controller is connected with a plurality of storage chips.
Preferably, the plurality of memory chips connected with each hard disk controller of the present invention at least include a dynamic random access memory DRAM and a NAND Flash.
Preferably, the utility model discloses still include SATA interface and the redundant module of disk, SATA interface connection redundant module of disk, first hard disk controller, the hard disk controller of second all are connected with the redundant module of disk.
Preferably, the utility model discloses redundant code module of disk includes RAID chip, SATA interface circuit, first hard disk controller interface circuit and second hard disk controller interface circuit, and wherein the RAID chip passes through SATA interface circuit and SATA interface connection, and the RAID chip passes through first hard disk controller interface circuit of first hard disk controller interface circuit connection, and the RAID chip passes through second hard disk controller interface circuit connection second hard disk controller.
Preferably, the SATA interface is connected to the RAID chip through two pairs of differential pairs, the RAID chip includes pins S1_ RXP, S1_ RXN, S1_ TXP and S1_ TXN, pins S1_ RXP, S1_ RXN, S1_ TXP and S1_ TXN respectively fan out differential signals and are connected to four pins S2, S3, S5 and S6 of the SATA interface, pins S1_ RXP and S1_ RXN form a pair of differential signals, pins S1_ TXP and S1_ TXN form a pair of differential signals, and two pairs of differential signals on the RAID chip are separated by one pin and are grounded.
Preferably, the first hard disk controller is in communication connection with the RAID chip through the GPIO port and the two pairs of differential pairs. Similarly, the second hard disk controller is in communication connection with the RAID chip through the GPIO port and the two pairs of differential pairs.
Preferably, the first hard disk controller is connected with a first dynamic random access memory DRAM and a first NAND Flash, and the second hard disk controller is connected with a second dynamic random access memory DRAM and a second NAND Flash.
Preferably, the utility model discloses still include two power down protection modules, first, the hard disk controller of second corresponds a power down protection module respectively. Specifically, the power down protection module comprises a first power down protection module, a first energy storage module, a power conversion module, a second power down protection module and a second energy storage module, an external power supply is connected with the first power down protection module, the first power down protection module is connected with the first energy storage module, the first power down protection module is connected with a plurality of power conversion modules, each power conversion module is respectively connected with each storage chip connected with a hard disk controller (a first hard disk controller or a second hard disk controller) and the hard disk controller (a first hard disk controller or a second hard disk controller), and each power conversion module converts an input power into a working power of each storage chip connected with the hard disk controller and the hard disk controller (the first hard disk controller or the second hard disk controller). At least one power conversion module is connected with a second-level power-down protection module, the second-level power-down protection module is connected with a corresponding storage chip, and the second-level power-down protection module is connected with a second-level energy storage module.
Preferably, the first power-down protection module and the second power-down protection module both comprise a voltage boosting and stabilizing circuit.
The utility model has the advantages as follows:
at present, the mainstream solid state disk is limited by the number of channels of a mainstream controller and the number of mounted NAND Flash, so that the corresponding storage capacity of a single controller is often limited, and the maximum storage capacity is generally about 2TB-4 TB. The utility model discloses a two hard disk controllers that carry large capacity memory chip can realize realizing under standard 2.5 cun plate frame constructs to the current controller support under the capacity doubling to realize solid state hard disk's large capacity storage.
Specifically, the utility model discloses a RAID0 carries out unified capacity management to two hard disk controller of solid state hard drives is established to the RAID chip to the multiplication of capacity is realized to the large capacity storage chip through each hard disk controller mount, promotes maximum storage capacity, and to the chip storage capacity after showing unified multiplication outward, realizes the promotion to present mainstream solid state hard drives maximum capacity.
Drawings
Fig. 1 is a schematic structural diagram of an embodiment of the present invention.
Fig. 2 is a circuit diagram of a redundant module according to an embodiment of the present invention.
Fig. 3 is a block diagram of a power down protection module used in an embodiment of the present invention.
FIG. 4 is a circuit schematic of a first stage power down protection module;
FIG. 5 is a circuit schematic of a first stage energy storage module;
FIG. 6 is a circuit schematic of a second stage power down protection module;
fig. 7 is a circuit schematic of a second stage energy storage module.
Detailed Description
In order to make the technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.
Referring to fig. 1, the present embodiment provides a large-capacity solid state disk, which includes dual hard disk controllers, and each hard disk controller is connected to a plurality of memory chips. Specifically, the system comprises a SATA interface, a disk redundancy module, a first hard disk controller, a second hard disk controller, a first Dynamic Random Access Memory (DRAM), a first NAND Flash, a second DRAM and a second NAND Flash.
The SATA interface is connected with the disk redundancy module, and the first hard disk controller and the second hard disk controller are both connected with the disk redundancy module. The SATA interface is connected with the redundant module of the magnetic disc and two hard disc controllers to form a channel for data storage, wherein: and the redundant modules of the disks and the hard disk controller construct RAID 0.
The first hard disk controller is connected with a first dynamic random access memory DRAM and a first NAND Flash, and the second hard disk controller is connected with a second dynamic random access memory DRAM and a second NAND Flash.
And establishing RAID0 for the two hard disk controller controllers through the disk redundancy module. At this time, the memory chips to which both hard disk controllers are connected are the maximum memory capacity chips employed in the connectable capacity. Therefore, the capacity is multiplied through the building of RAID0, and the large capacity of the dual controller is realized.
Referring to fig. 2, this embodiment provides a redundant code module for a disk, including a RAID chip, an SATA interface circuit, a first hard disk controller interface circuit, and a second hard disk controller interface circuit, where the RAID chip is connected to the SATA interface through the SATA interface circuit, the RAID chip is connected to the first hard disk controller through the first hard disk controller interface circuit, the RAID chip is connected to the second hard disk controller through the second hard disk controller interface circuit, and a storage module is mounted below the RAID chip, regardless of the first hard disk controller or the second hard disk controller. The RAID chip, the first hard disk controller and the second hard disk controller form a RAID0 array, and the realization principle is as follows: external data is written into the RAID chip through the SATA interface, at the moment, the RAID chip is reasonably distributed, internal judgment data is stored in a storage module under a first hard disk or a storage module under a second hard disk, when the internal judgment data is stored under the first data storage module, a channel with the first hard disk storage module is opened, an enabling signal is sent to enable the first hard disk to start working, after certain data is stored, enabling signals are alternately sent to enable the second hard disk to work, meanwhile, the first hard disk is closed, and the data is written into the storage module mounted under the second hard disk controller. Correspondingly, no matter the first hard disk controller or the second hard disk controller is used, the self storage state can be fed back to the RAID chip through the feedback pin, and if the mounted storage module below the first storage controller reaches the maximum value, the controller feeds back a high level to the RAID chip at the moment, and then data is written back to the RAID chip to start the second hard disk controller by default. The specific implementation functions and connection pins are defined as follows:
the SATA interface circuit comprises an interface in FIG. 2, and can be divided into the following steps: s1_ RXP, S1_ RXN, S1_ TXP and S1_ TXN corresponding to the RAID chip pins are respectively connected with S2, S3, S5 and S6 of the SATA interface through fanout differential signals. Since the SATA is a high-speed differential signal, one SATA connection includes a transmission signal pair and a reception signal pair, two pairs of differential signals are connected to the RAID chip, and in order to ensure impedance consistency and reduce EMC radiation, the differential signal transceiver pins are brought close to each other, and at the same time, the RAID chip separates the two pairs of differential signals from the ground pins, that is, the two pairs of differential signals are separated from each other by the ground, so that mutual interference between the two pairs of differential signals is reduced, and the stability of connection between the SATA interface and the RAID chip and the high efficiency of signal transmission are ensured.
And the first hard disk controller is in communication connection with the RAID chip through the GPIO port and the two pairs of differential pairs. The GPIO ports of the RAID chip include corresponding GPIO19, GPIO18, and GPIO17 pins in fig. 2. The differential signals of the RAID chip include the corresponding S2_ TXP, S2_ TXN, S2_ RXN and S2_ RXP pins of FIG. 2. When the first hard disk controller realizes the functions, the working state is as follows, the RAID chip gives a low level through the GPIO17 pin to control the first hard disk controller to work, and the first hard disk controller is enabled by the low level. When the Flash memory mounted on the first hard disk controller reaches the maximum, the feedback pin of the first hard disk controller connected with the pin of the GPIO18 feeds back a high level, and after receiving the high level, the RAID chip stops enabling the first hard disk controller and starts the second hard disk controller. The GPIO19 pin of the RAID chip is connected with a destruction circuit of the first hard disk controller, when the hard disk needs to be destroyed, the RAID chip gives a low level, the destruction pin of the first hard disk controller is pulled down through the GPIO19 pin, and the destruction function is started. The RAID chip is connected with the first hard disk controller through two pairs of differential signal pairs consisting of S2_ TXP, S2_ TXN, S2_ RXN and S2_ RXP pins, and the data receiving and transmitting functions are realized. After the two pairs of differential signals are connected with the first hard disk controller, the design of the differential pair connection between the RAID chip and the SATA interface should be referred.
And the second hard disk controller is in communication connection with the RAID chip through the GPIO port and the two pairs of differential pairs. The GPIO ports of the RAID chip include GPIO1 and GPIO6 corresponding to those in fig. 2, which surround the GPIO0 pin. The differential signals of the RAID chip include corresponding pins SSTXN, SSTXP, SSRXN, and SSRXP in fig. 2. When the second hard disk controller realizes the functions, the working state is as follows, the RAID chip gives a low level through the GPIO1 pin to control the second hard disk controller to work, and the second hard disk controller is enabled by the low level. And a feedback pin of the second hard disk controller, which is connected with the pin of the GPIO6, feeds back a high level when the Flash storage mounted on the second hard disk controller reaches the maximum, and the RAID chip stops enabling the control of the second hard disk and starts the first hard disk controller after receiving the high level. The GPIO0 pin of the RAID chip is connected with a destruction circuit of the second hard disk controller, when the hard disk needs to be destroyed, the RAID chip gives a low level, the destruction pin of the second hard disk controller is pulled down through the GPIO0 pin, and the destruction function is started. The RAID chip is connected with the second hard disk controller through two pairs of differential signals consisting of SSTX, SSRXN and SSRXP pins to realize the data receiving and transmitting functions. After the two pairs of differential signals are connected with the second hard disk controller, the design of the differential pair connection between the RAID chip and the SATA interface should be referred.
The utility model discloses still include two power down protection modules, first, the hard disk controller of second corresponds a power down protection module respectively. Referring to fig. 3, a schematic structural diagram of a power down protection module provided in this embodiment is shown. The power-down protection module comprises a first-stage power-down protection module, a first-stage energy storage module, a 1# power conversion module, a 2# power conversion module, a 3# power conversion module, a second-stage power-down protection module and a second-stage energy storage module. The 1# power conversion module, the 2# power conversion module and the 3# power conversion module are used for voltage conversion and mainly comprise a DC-DC voltage conversion chip. The first-stage energy storage module and the second-stage energy storage module realize the storage and the release of energy and mainly comprise a tantalum capacitor super capacitor array.
The external power supply is connected with the first-stage power-down protection module, the first-stage power-down protection module is connected with the first-stage energy storage module, the first-stage power-down protection module is connected with the 1# power conversion module, the 2# power conversion module and the 3# power conversion module, the 1# power conversion module, the 2# power conversion module and the 3# power conversion module are respectively connected with the dynamic random access memory DRAM, the hard disk controller and the NAND Flash, and each power conversion module converts respective input power into a working power supply of the dynamic random access memory DRAM, the hard disk controller and the NAND Flash to supply power to the dynamic random access memory DRAM, the hard disk controller and.
The 3# power conversion module connected with the NAND Flash is connected with the second-level power-down protection module, the second-level power-down protection module is connected with the second-level energy storage module, and the second-level power-down protection module is connected with the NAND Flash.
In this embodiment: the first-stage power-down protection module comprises a voltage boosting and stabilizing circuit, and the voltage boosting and stabilizing circuit boosts 5V input voltage provided by the host end to 12V to charge and store energy of the first-stage energy storage module. The second-stage power-down protection module comprises a voltage boosting and stabilizing circuit, and the voltage boosting and stabilizing circuit boosts 3.3V input voltage to 12V to charge and store energy for the second-stage energy storage module. The 1# power supply conversion module comprises a DC-DC voltage reduction circuit, and the 5V power supply voltage output by the first-stage power-down protection module is reduced to 1.5V for the DRAM to work. The 2# power supply conversion module comprises a DC-DC voltage reduction circuit, and the voltage of the 5V power supply voltage output by the first-stage power failure protection module is reduced to 1.8V power supply voltage for the hard disk controller to work. The 3# power supply conversion module comprises a DC-DC voltage reduction circuit, and the voltage of the 5V power supply voltage output by the first-stage power failure protection module is reduced to 3.3V power supply voltage for the NAND Flash and the second-stage power failure protection module to work.
When the solid state disk is normally powered on and works, 5V power supply voltage is provided by an external power supply (such as a host end), the first-stage power-down protection module boosts the first-stage energy storage module to 12V for charging and energy storage, after the first-stage energy storage module finishes energy storage, a stable power supply pool is constructed, 5V stable power supply voltage consistent with the external power supply (such as the host end) can be output again through the first-stage power-down protection module, the power supply voltage is reduced to 1.5V through the 1# power conversion module for DRAM (dynamic random access memory) to work, the power supply voltage is reduced to 1.8V through the 2# power conversion module for the hard disk controller to work, the power supply voltage is reduced to 3.3V through the 3# power conversion module for NAND Flash and the second-stage power-down protection module to work, meanwhile, the second-stage power-down protection module charges and stores energy to the second-stage energy storage, after the second-stage energy storage module finishes energy storage work, a stable power supply pool is also constructed. The energy storage work of the multi-stage power failure protection of the solid state disk is completed through the steps.
When an external power supply (such as a host end) is unexpectedly powered down, the working voltage of the solid state disk drops instantly, the hard disk controller cuts off communication with the host after detecting power down, at the moment, the first-stage power down protection module releases electric quantity in the first-stage energy storage module after detecting power down unexpectedly, power supply voltage is continuously provided for the 1# power conversion module, the 2# power conversion module and the 3# power conversion module, so that the hard disk controller provides cache data in the dynamic random access memory DRAM and writes the cache data back to the NAND Flash until the electric quantity in the first-stage energy storage module is exhausted, the data write back in the hard disk controller and the dynamic random access memory DRAM is successful, and the first-stage power down protection is finished. Meanwhile, the second power-down protection module detects the voltage drop in the 3# power conversion module, writes data into a page of the NAND Flash to protect an internal NVRAM in the NAND Flash, starts up the second power-down protection module, releases electric quantity in the second energy storage module, continues to maintain the power supply voltage of the NAND Flash until the electric quantity is exhausted, and finishes protecting the data.
Fig. 4 is a schematic circuit diagram of a first stage power-down protection module in an embodiment; the power failure protection circuit comprises a main chip (a power supply energy storage chip) and a peripheral circuit thereof, wherein a first-stage power failure protection module manages an external input voltage VCC5I through the power supply energy storage chip, stores the external input voltage to a VCAP _ MP end, and inputs the external input voltage into the first-stage energy storage module through the VCAP _ MP.
As shown in fig. 5, the schematic circuit diagram of the first-stage energy storage module is that the first-stage energy storage module is an energy storage array composed of a tantalum capacitor or a super capacitor, and when an unexpected power failure occurs, the power failure protection module starts a protection mechanism to release electric energy at the VCAP _ MP terminal, and continues to maintain VCC5I voltage until the cache data is completely written into the NAND Flash.
In the circuit design of the second-level power-down protection module, the key protection is the cache data in the NAND FLASH chip, and similarly, the same design principle of the first-level power-down protection module is adopted. Fig. 6 is a schematic circuit diagram of a second-stage power-down protection module, which includes a main chip (power storage chip) and a peripheral circuit thereof, and performs energy storage protection on VCCFQ for the NAND Flash CORE voltage shown in fig. 6, and stores VCCFQ in the second-stage energy storage module (as shown in fig. 7, fig. 7 is a schematic circuit diagram of the second-stage energy storage module) through the same power management as that of the first-stage power-down protection module, and forms an energy storage array through a tantalum capacitor or a super capacitor, so as to continuously maintain VCCFQ when power is unexpectedly turned off, and ensure successful data write-back.
To sum up, with the aid of the technical scheme of the utility model, through multistage power down protection mechanism
To sum up, with the help of the above technical scheme of the utility model, through multistage power down protection mechanism, to SSD master controller, cache chip, NVRAM in the NAND Flash carries out additional power down protection after the unexpected power down handles to effectual solution accident falls various buffer memory data that lead to of falling the electricity and loses, lets the interim data of buffer memory through the additional power supply that lasts, thereby in the complete NAND Flash of writing into, has proposed a high reliability's technical method for solid state hard disk's design.
To sum up, with the help of the utility model discloses an above-mentioned technical scheme, through the redundant technique of magnetic disk, make the stack of hard disk maximum capacity through establishing RAID0 to the controller, make the within range promotion solid state hard disk capacity in limited space and NAND Flash, realize the multiplication of solid state hard disk capacity.
In summary, although the present invention has been described with reference to the preferred embodiments, it should be understood that the present invention is not limited thereto, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention.
Claims (10)
1. A large capacity solid state hard drives, its characterized in that: including two hard disk controller, SATA interface and redundant module of magnetic disk, each hard disk controller all is connected with polylith storage chip, SATA interface connection redundant module of magnetic disk, first hard disk controller, second hard disk controller all are connected with redundant module of magnetic disk, the SATA interface links to each other with redundant module of magnetic disk and two hard disk controllers and constitutes data storage's passageway, wherein: and the redundant modules of the disks and the hard disk controller construct RAID 0.
2. A large capacity solid state disk as claimed in claim 1, wherein: the plurality of memory chips connected with each hard disk controller at least comprise a dynamic random access memory DRAM and a NAND Flash.
3. A large capacity solid state disk as claimed in claim 2, wherein: the first hard disk controller is connected with a first dynamic random access memory DRAM and a first NAND Flash, and the second hard disk controller is connected with a second dynamic random access memory DRAM and a second NAND Flash.
4. A large capacity solid state disk as claimed in claim 3, wherein: the redundant code module of the magnetic disk comprises an RAID chip, an SATA interface circuit, a first hard disk controller interface circuit and a second hard disk controller interface circuit, wherein the RAID chip is connected with the SATA interface through the SATA interface circuit, the RAID chip is connected with the first hard disk controller through the first hard disk controller interface circuit, and the RAID chip is connected with the second hard disk controller through the second hard disk controller interface circuit.
5. A large capacity solid state disk as claimed in claim 3, wherein: the SATA interface and the RAID chip are connected with the RAID chip through two pairs of differential pairs, the RAID chip comprises S1_ RXP pins, S1_ RXN pins, S1_ TXP pins and S1_ TXN pins, S1_ RXP pins, S1_ RXN pins, S1_ TXP pins and S1_ TXN pins are respectively connected with four pins S2, S3 pins, S5 pins and S6 pins of the SATA interface, the S1_ RXP pins and S1_ RXN pins form a pair of differential signal pairs, the S1_ TXP pins and S1_ TXN pins form a pair of differential signal pairs, and one pin is arranged between the two pairs of differential signal pairs on the RAID chip and is grounded.
6. A large capacity solid state disk as claimed in claim 3, wherein: the first hard disk controller is in communication connection with the RAID chip through the GPIO port and the two pairs of differential pairs;
the RAID chip comprises GPIO19, GPIO18 and GPIO17 pins, the RAID chip gives out a low level through the GPIO17 pin and controls the first hard disk controller to work, and the first hard disk controller is enabled by the low level; when the Flash storage mounted on the first hard disk controller reaches the maximum, a feedback pin of the first hard disk controller connected with the GPIO18 feeds back a high level, and after receiving the high level, the RAID chip stops enabling the first hard disk controller and starts a second hard disk controller; the GPIO19 pin of the RAID chip is connected with a destruction circuit of the first hard disk controller, when the hard disk needs to be destroyed, the RAID chip gives a low level, the destruction pin of the first hard disk controller is pulled down through the GPIO19 pin, and the destruction function is started;
the RAID chip comprises S2_ TXP, S2_ TXN, S2_ RXN and S2_ RXP pins, wherein S2_ TXP and S2_ TXN form a pair of differential signal pairs, and S2_ RXN and S2_ RXP form a pair of differential signal pairs; the RAID chip is connected with the first hard disk controller through two pairs of differential signal pairs consisting of S2_ TXP, S2_ TXN, S2_ RXN and S2_ RXP pins, and the data receiving and transmitting functions are realized.
7. A large capacity solid state disk as claimed in claim 3, wherein: the second hard disk controller is in communication connection with the RAID chip through the GPIO port and the two pairs of differential pairs;
the RAID chip comprises GPIO1, GPIO6 and GPIO0 pins; the RAID chip gives out a low level through a GPIO1 pin, controls a second hard disk controller to work, and the second hard disk controller is enabled by the low level; when the Flash storage mounted on the second hard disk controller reaches the maximum, the feedback pin of the second hard disk controller connected with the GPIO6 feeds back a high level, and after receiving the high level, the RAID chip stops enabling the control of the second hard disk and starts the first hard disk controller; the GPIO0 pin of the RAID chip is connected with a destruction circuit of the second hard disk controller, when the hard disk needs to be destroyed, the RAID chip gives a low level, the destruction pin of the second hard disk controller is pulled down through the GPIO0 pin, and the destruction function is started;
the RAID chip comprises SSTXN, SSTXP, SSRXN and SSRXP pins, wherein the SSTXN and the SSTXP form a pair of differential signal pairs, and the SSRXN and the SSRXP form a pair of differential signal pairs; the RAID chip is connected with the second hard disk controller through two pairs of differential signals consisting of SSTX, SSRXN and SSRXP pins to realize the data receiving and transmitting functions.
8. A large capacity solid state disk as claimed in any one of claims 3 to 7, wherein: the system also comprises two power failure protection modules, wherein the first hard disk controller and the second hard disk controller respectively correspond to one power failure protection module.
9. A large capacity solid state disk as claimed in claim 8, wherein: the power-down protection module comprises a first-stage power-down protection module, a first-stage energy storage module, a power conversion module, a second-stage power-down protection module and a second-stage energy storage module, an external power supply is connected with the first-stage power-down protection module, the first-stage power-down protection module is connected with the first-stage energy storage module, the first-stage power-down protection module is connected with a plurality of power conversion modules, each power conversion module is respectively connected with a hard disk controller and each storage chip connected with the hard disk controller, and each power conversion module converts an input power supply into a working power supply of each storage chip connected with the hard disk controller and the hard;
at least one power conversion module is connected with a second-level power-down protection module, the second-level power-down protection module is connected with a corresponding storage chip, and the second-level power-down protection module is connected with a second-level energy storage module.
10. A large capacity solid state disk as claimed in claim 9, wherein: the first-stage power-down protection module and the second-stage power-down protection module both comprise a voltage boosting and stabilizing circuit.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111949579A (en) * | 2020-08-07 | 2020-11-17 | 天津市英贝特航天科技有限公司 | Device for realizing multi-hard-disk mounting by one-path SATA interface |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111949579A (en) * | 2020-08-07 | 2020-11-17 | 天津市英贝特航天科技有限公司 | Device for realizing multi-hard-disk mounting by one-path SATA interface |
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