CN210778080U

CN210778080U - Multilayer chip varistor

Info

Publication number: CN210778080U
Application number: CN201921941482.5U
Authority: CN
Inventors: 刘树英; 周斌扬; 颜健
Original assignee: Dongguan Littelfuse Electronic Co Ltd
Current assignee: Dongguan Littelfuse Electronic Co Ltd; Littelfuse Dongguan Manufacturing Facility
Priority date: 2019-11-11
Filing date: 2019-11-11
Publication date: 2020-06-16
Anticipated expiration: 2029-11-11

Abstract

The utility model discloses a multilayer chip varistor, it includes ceramic main part, ceramic main part's inside is equipped with a plurality of parallelly connected varistor units of range upon range of setting, and is a plurality of mutual independence between the varistor unit, and every the varistor unit includes polarity reversal and two inner electrodes of interval arrangement in the plane of perpendicular to range upon range of direction. According to the multilayer chip varistor, the two inner electrodes in each varistor unit are arranged at intervals in a plane perpendicular to the stacking direction, so that the inter-pole distance IED is greatly increased, and the change space is large.

Description

Multilayer chip varistor

Technical Field

The present disclosure relates to a varistor, and more particularly, to a multilayer chip varistor.

Background

With the development of electronic products toward miniaturization, thinning, integration, and multi-functionalization, the varistor has been developed into a multilayer chip varistor (hereinafter, abbreviated as MLV). MLV has features of small size, light weight, high reliability, etc., and thus is widely used in various fields.

MLV structures typically include a rectangular ceramic body with internal electrodes arranged in a staggered pattern: the rated voltage Vnom of the MLV is usually controlled by the inter-electrode distance IED between the first and second internal electrodes (Vnom ═ Ev × IED, where Ev is a specific voltage), and at present, there are two main ways of arranging the internal electrodes: (1) the first internal electrodes and the second internal electrodes are staggered in the stacking direction, (2) the first internal electrodes and the second internal electrodes are at least partially overlapped in the overlapping direction. In both arrangements, the inter-electrode distance IED between the first and second internal electrodes is measured in the height direction of the ceramic body, and is limited by the size of the ceramic body, resulting in a small inter-electrode distance between the first and second internal electrodes, which results in an unsatisfactory voltage rating and poor antistatic properties.

SUMMERY OF THE UTILITY MODEL

An object of the present disclosure is to solve at least one aspect of the above problems and disadvantages in the related art.

According to an embodiment of one aspect of the present disclosure, there is provided a multilayer chip varistor including a ceramic main body, a plurality of varistor units arranged in parallel in a stacked manner are provided inside the ceramic main body, the plurality of varistor units are independent of each other, and each varistor unit includes two inner electrodes having opposite polarities and arranged at intervals in a plane perpendicular to a stacking direction.

According to an embodiment of the present disclosure, the two internal electrodes include a first internal electrode and a second internal electrode, and the first internal electrodes in the plurality of varistor units completely overlap in the lamination direction.

According to an embodiment of the present disclosure, the second inner electrodes in the plurality of varistor units completely overlap in the stacking direction.

According to an embodiment of the present disclosure, when a length of the ceramic main body in an arrangement direction of the internal electrodes is L, then an inter-polar distance IED between the first and second internal electrodes satisfies the following equation:

0.8L≥IED≥0.2L。

according to an embodiment of the present disclosure, the arrangement direction coincides with a length direction of the ceramic main body.

According to an embodiment of the present disclosure, lengths of the first and second internal electrodes in the arrangement direction are equal.

According to an embodiment of the present disclosure, the ceramic main body includes a plurality of ceramic diaphragms stacked, and the plurality of ceramic diaphragms and the plurality of varistor units are alternately arranged.

According to an embodiment of the present disclosure, the internal electrode is formed on the ceramic membrane by screen printing.

According to an embodiment of the present disclosure, the multilayer chip varistor further includes first external electrodes and second external electrodes, the first external electrodes are respectively connected to the first internal electrodes of the plurality of varistor units, and the second external electrodes are respectively connected to the second internal electrodes of the plurality of varistor units.

According to an embodiment of the present disclosure, the first outer electrode and the second outer electrode are in an open box shape, an end of the ceramic body close to the first inner electrode is inserted into the first outer electrode, and an end of the ceramic body close to the second inner electrode is inserted into the second outer electrode.

The multilayer chip varistor according to the above embodiments of the present disclosure has a large variation space compared to the prior art, in which the inter-polar distance IED between two inner electrodes measured in the Z direction (i.e., the height direction) is increased by stacking a plurality of varistor units in a ceramic main body, and each varistor unit includes two inner electrodes having opposite polarities and arranged at an interval in a plane perpendicular to the stacking direction (as shown in fig. 2). Due to rated voltage V_nomEv × IED, so that the maximum rated voltage of the multilayer chip varistor can be greatly increased。

Drawings

Fig. 1 is a schematic structural view of a multilayer chip varistor after a portion thereof is removed according to an exemplary embodiment of the present disclosure; and

fig. 2 is a schematic plan view of the multilayer chip varistor shown in fig. 1.

Detailed Description

While the present disclosure will be fully described with reference to the accompanying drawings, which contain preferred embodiments of the disclosure, it is to be understood before this description that one of ordinary skill in the art can, of course, modify the utility model described herein while obtaining the technical effects of the present disclosure. Therefore, it should be understood that the foregoing description is a broad disclosure directed to persons of ordinary skill in the art, and that there is no intent to limit the exemplary embodiments described in this disclosure.

Furthermore, in the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in schematic form in order to simplify the drawing.

According to the general inventive concept of the present disclosure, there is provided a multilayer chip varistor including a ceramic main body, a plurality of parallel varistor units stacked and disposed inside the ceramic main body, the plurality of varistor units being independent of each other, and each varistor unit including two inner electrodes having opposite polarities and arranged at an interval in a plane perpendicular to a stacking direction.

Fig. 1 is a schematic structural view of a multilayer chip varistor after a portion has been removed according to an exemplary embodiment of the present disclosure; and fig. 2 is a schematic plan view of the multilayer chip varistor shown in fig. 1.

In an exemplary embodiment, as shown in fig. 1 and 2, the multilayer chip varistor includes a ceramic main body 1 having a rectangular parallelepiped structure, a plurality of parallel varistor units 2 stacked and arranged inside the ceramic main body 1, the plurality of varistor units 2 are independent of each other, and each varistor unit 2 includes two

internal electrodes

21, 22 having opposite polarities and arranged at a certain interval in a plane perpendicular to the stacking direction Z.

In one exemplary embodiment, as shown in fig. 1 and 2, the two

internal electrodes

21, 22 include a first internal electrode 21 and a second internal electrode 22, the first internal electrode 21 in each varistor unit 2 completely overlaps in the lamination direction Z, and the second internal electrode 22 in each varistor unit 2 also completely overlaps in the lamination direction Z. The interpolar distance IED between the first inner electrode 21 and the second inner electrode 22 of each varistor cell 2 is therefore equal in order to facilitate the control of the nominal voltage Vnom. It should be noted that, in some other embodiments of the present disclosure, the first internal electrode 21 and/or the second internal electrode 22 in each piezoresistive unit 2 may not completely overlap in the lamination direction Z.

In an exemplary embodiment, as shown in fig. 1 and 2, when the length of the ceramic main body 1 in the arrangement direction (in this embodiment, the X direction) of the

internal electrodes

21, 22 is L, then the polar distance between the first internal electrode 21 and the second internal electrode 22 is IED preferably satisfies the following equation to ensure the reliability of the operation of the varistor unit.

IED is more than or equal to 0.8L and more than or equal to 0.2L equation (1).

In an exemplary embodiment, as shown in fig. 1 and 2, the arrangement direction coincides with the length direction of the ceramic main body 1. Here, the length direction refers to a direction having a longer side length (i.e., X direction) in a rectangular cross section of the ceramic main body 1 parallel to the XY plane, so that the inter-polar distance IED between the first and second

internal electrodes

21 and 22 can be further increased. However, it should be noted that, in some other embodiments of the present disclosure, the arrangement direction may be consistent with the width direction (i.e., Y direction) of the ceramic main body 1.

In an exemplary embodiment, as shown in fig. 1 and 2, the lengths of the first and second

internal electrodes

21 and 22 in the arrangement direction are equal to facilitate better control and calculation of the rated voltage Vnom. However, it should be noted that, in some other embodiments of the present disclosure, the lengths of the first internal electrode 21 and the second internal electrode 22 in the arrangement direction may not be equal.

In one exemplary embodiment, as shown in fig. 1 and 2, the number of the varistor units 2 is 2 to 25. It should be noted, however, that in other embodiments of the present disclosure, the number of the varistor units 2 may be other values, such as 30, 35, etc.

In an exemplary embodiment, as shown in fig. 1 and 2, the ceramic body 1 includes a plurality of ceramic diaphragms stacked and arranged alternately with the plurality of varistor units so that adjacent two varistor units 2 are spaced apart by the ceramic diaphragms.

In an exemplary embodiment, as shown in fig. 1 and 2, the

internal electrodes

21, 22 are formed on the ceramic wafer by screen printing to ensure IED accuracy. However, it should be noted that, in some other embodiments of the present disclosure, the

inner electrodes

21, 22 may be formed in the ceramic main body 1 by other methods.

In an exemplary embodiment, as shown in fig. 1 and 2, the multilayer chip varistor further includes two external electrodes 3: first and second external electrodes 31 and 32, the first external electrode 31 being connected to the first internal electrodes 21 of the plurality of varistor units 2, respectively, and the second external electrode 32 being connected to the second internal electrodes 22 of the plurality of varistor units 2, respectively.

In an exemplary embodiment, as shown in fig. 1 and 2, the first and second external electrodes 31 and 32 have an open box shape, and one end of the ceramic body 1 adjacent to the first internal electrode 21 is inserted into the first external electrode 31 via the opening, and one end of the ceramic body 1 adjacent to the second internal electrode 22 is inserted into the second external electrode 32 via the opening, to improve the reliability of connection.

The multilayer chip varistor provided by the present disclosure is formed by laminating a plurality of varistor units in a ceramic body, and each varistor unitThe resistance unit includes two inner electrodes with opposite polarities and arranged at intervals in a plane perpendicular to the stacking direction, and the inter-polar distance IED of the varistor unit is the distance between the two inner electrodes measured in the X direction (as shown in fig. 2), which is greatly increased and has a large variation space compared to the inter-polar distance IED between the two inner electrodes measured in the Z direction (i.e., the height direction) in the prior art. Due to rated voltage V_nomEv × IED, so that the maximum rated voltage of the multilayer chip varistor can be greatly increased, and the antistatic performance and reliability are greatly improved. For a 0603 size varistor, for example, the nominal voltage achievable by the present disclosure may be as high as 440V.

It will be appreciated by those skilled in the art that the embodiments described above are exemplary and can be modified by those skilled in the art, and that the structures described in the various embodiments can be freely combined without conflict in structure or principle.

Having described preferred embodiments of the present disclosure in detail, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope and spirit of the appended claims, and the disclosure is not limited to the exemplary embodiments set forth herein.

Claims

1. The multilayer chip type piezoresistor is characterized by comprising a ceramic main body, wherein a plurality of piezoresistor units which are connected in parallel and are arranged in a laminated mode are arranged in the ceramic main body, the piezoresistor units are mutually independent, and each piezoresistor unit comprises two inner electrodes which are opposite in polarity and are arranged at intervals in a plane perpendicular to the laminated direction.

2. The multilayer chip varistor of claim 1, wherein the two internal electrodes include a first internal electrode and a second internal electrode, and the first internal electrodes of the plurality of varistor units completely overlap in the stacking direction.

3. The multilayer chip varistor of claim 2, wherein the second internal electrodes of a plurality of the varistor units completely overlap in the stacking direction.

4. The multilayer chip varistor according to claim 3, wherein when the length of the ceramic main body in the arrangement direction of the internal electrodes is L, the inter-electrode distance IED between the first and second internal electrodes satisfies the following equation:

0.8L≥IED≥0.2L。

5. the multilayer chip varistor according to claim 4, wherein the arrangement direction is aligned with a length direction of the ceramic body.

6. The multilayer chip varistor of claim 4, wherein the lengths of the first and second internal electrodes in the arrangement direction are equal.

7. The multilayer chip varistor of any of claims 1-6, wherein the ceramic body comprises a plurality of ceramic diaphragms stacked together, the plurality of ceramic diaphragms alternating with the plurality of varistor units.

8. The multilayer chip varistor of claim 7, wherein said internal electrodes are formed on said ceramic chip by screen printing.

9. The multilayer chip varistor of any of claims 1-6, further comprising a first external electrode and a second external electrode, wherein the first external electrode is connected to the first internal electrodes of the varistor cells, respectively, and the second external electrode is connected to the second internal electrodes of the varistor cells, respectively.

10. The multilayer chip varistor as claimed in claim 9, wherein the first and second external electrodes are in the form of an open box, one end of the ceramic body adjacent to the first internal electrode is inserted into the first external electrode, and one end of the ceramic body adjacent to the second internal electrode is inserted into the second external electrode.