TWI810594B - Multilayer varistor and method of manufacturing the same - Google Patents

Abstract

A multilayer varistor and a method of manufacturing the same are provided. The method includes: providing an initial multilayer structure; sintering the initial multilayer structure to form a sintered multilayer structure; processing the sintered multilayer structure to form a multilayer stacked structure including an insulating carrier, a plurality of first inner conductive layers disposed inside the insulating carrier, and a plurality of second inner conductive layers disposed inside the insulating carrier, and the first inner conductive layers and the second inner conductive layers being alternately arranged; and then forming an outer electrode structure to partially enclose the multilayer stacked structure, the outer electrode structure including a first outer electrode layer electrically contacting a plurality of first inner conductive layers, and a second outer electrode layer electrically contacting a plurality of second inner conductive layers, and the first outer electrode layer and the second outer electrode layer respectively enclosing a first side and a second side of the multilayer stacked structure.

Description

Multilayer varistor and manufacturing method thereof

The invention relates to a varistor and a manufacturing method thereof, in particular to a multilayer varistor and a manufacturing method thereof.

Varistor (Varistor) is an electronic component, also known as Voltage Dependent Resistor (VDR), its resistance changes with the applied voltage, and it has nonlinear characteristics (non-ohmic current-voltage characteristics) similar to diodes. However, contrary to a diode, it has the same characteristics in both lateral current directions. Traditionally, varistors are actually constructed by connecting two rectifiers, such as copper oxide or germanium oxide rectifiers in an antiparallel configuration. At low voltages, varistors have a high resistance that decreases as the voltage increases. Modern varistors are mainly based on sintered ceramic metal oxide materials, which exhibit directionality only on the microscopic scale. This type is commonly referred to as a Metal Oxide Varistor (MOV). In addition, varistors can be used as control or compensation elements in circuits to provide optimum operating conditions or to protect against excessive transient voltages. When varistors are used as protection devices, they shunt the current generated by the excessive voltage from the sensitive component when triggered.

The technical problem to be solved by the present invention is to provide a A multilayer varistor and a manufacturing method thereof.

In order to solve the above technical problems, one of the technical solutions adopted by the present invention is to provide a method for manufacturing a multilayer varistor, which includes: providing an initial multilayer structure; sintering the initial multilayer structure to form A sintered multi-layer structure; the sintered multi-layer structure is made into a multi-layer stack structure, the multi-layer stack structure includes an insulating carrier, a plurality of first inner conductive layers arranged in the insulating carrier and a plurality of first inner conductive layers arranged in the insulating carrier A plurality of second inner conductive layers, and a plurality of first inner conductive layers and a plurality of second inner conductive layers are alternately arranged; and, forming an external electrode structure to partially cover the multi-layer stack structure, the external electrode structure includes electrical A first outer electrode layer contacting a plurality of first inner conductive layers and a second outer electrode layer electrically contacting a plurality of second inner conductive layers, and the first outer electrode layer and the second outer electrode layer are respectively coated with multiple layers A first side end and a second side end of the stacked structure. Wherein, the step of making the sintered multilayer structure into a multilayer stacked structure further includes step (A) or step (B). Wherein, the step (A) includes: soaking the sintered multilayer structure in a first solution containing alkali metal at a concentration of 0.1% to 4.9% for 30 to 120 seconds; immersing the sintered multilayer structure After the formula structure is taken out from the first solution, a drying step is performed to form a baked multi-layer structure; and a metal ion diffusion step is performed on the baked multi-layer structure at a temperature between 600°C and 800°C. Wherein, the step (B) includes: soaking the sintered multilayer structure in a second solution comprising a mixed resin glue containing alkali metal ions at a concentration of 0.1% to 4.9%; immersing the sintered multilayer structure from After the second solution is taken out, a drying step is performed to form a dried multilayer structure; and a metal ion diffusion step is performed on the dried multilayer structure at a temperature between 600° C. and 800° C.

In order to solve the above technical problems, another technical solution adopted by the present invention is to provide a multilayer varistor, which includes: a multilayer stack structure and an external electrode structure. The multi-layer stack structure includes an insulating carrier, a plurality of first inner conductive layers arranged in the insulating carrier, and a plurality of second inner conductive layers arranged in the insulating carrier, and the plurality of first inner conductive layers and the plurality of second inner conductive layers The inner conductive layers are arranged alternately. The outer electrode structure partially covers the multi-layer stack structure, and the outer electrode structure includes a first outer electrode layer electrically contacting a plurality of first inner conductive layers and a second outer electrode layer electrically contacting a plurality of second inner conductive layers layers, and the first external electrode layer and the second external electrode layer cover a first side end and a second side end of the multilayer stack structure respectively. Wherein, the insulating carrier includes an insulating upper cover, an insulating lower cover, and an insulating body connected between the insulating upper cover and the insulating lower cover, and the periphery of the insulating body has a first outer surface, a second outer surface, and a third outer surface. surface and a fourth outer surface, and a plurality of first inner conductive layers and a plurality of second inner conductive layers are alternately arranged in the insulating body.

Furthermore, each first inner conductive layer has a first exposed front end exposed from the first outer surface of the insulating body, a first rear buried end facing the second outer surface of the insulating body, and a first buried end facing the second outer surface of the insulating body. A first left buried end on the third outer surface of the insulating body and a first right buried end facing the fourth outer surface of the insulating body, the first exposed front end electrically contacts the first external electrode layer, and the first rear buried end The end corresponds to the first front exposed end and is covered in the insulating body, the first left buried end is connected between the first front exposed end and the first rear buried end and is covered in the insulating body, and The first right embedded end is connected between the first exposed front end and the first rear embedded end and is covered in the insulating body. Wherein, the second inner conductive layer has a second front exposed end exposed from the second outer surface of the insulating body, a second rear buried end facing the first outer surface of the insulating body, and a fourth outer surface facing the insulating body A second left buried end and a second right buried end facing the third outer surface of the insulating body, the second front exposed end electrically contacts the second external electrode layer, and the second rear buried end corresponds to the first The two front exposed ends are covered in the insulating body, the second left buried end is connected between the second front exposed end and the second rear buried end and covered in the insulating body, and the second right buried end The end is connected between the second front exposed end and the second rear buried end and is covered in the insulating body.

Furthermore, the insulation carrier meets the following conditions: the ratio of G to T1 is 1:0.3~1.0, the ratio of G to T2 is 1:0.3~1.0, the ratio of D11 to G is 1:0.3~1.0, and the ratio of D12 to G is 1:0.3~1.0. The ratio of G is 1:0.3~1.0, the ratio of D21 to G is 1:0.3~1.0, and the ratio of D22 to G is 1:0.3~1.0. Among them, T1 is the thickness of the insulating upper cover, T2 is the thickness of the insulating lower cover, G is the distance between the first inner conductive layer and the second inner conductive layer adjacent to each other, and D11 is the first left side of the first inner conductive layer. The distance between the buried end and the third outer surface of the insulating body, D12 is the distance between the first right embedded end of the first inner conductive layer and the fourth outer surface of the insulating body, and D21 is the second inner conductive layer D22 is the distance between the second right buried end of the second inner conductive layer and the third outer surface of the insulating body.

One of the beneficial effects of the present invention is that the method of manufacturing a multilayer varistor provided by the present invention can be achieved by "immersing the sintered multilayer structure in a first alkali metal containing 0.1%~4.9% concentration. the time in one solution is between 30 and 120 seconds; removing the sintered multilayer structure from the first solution followed by a baking step to form a baked multilayer structure; and at a temperature of 600°C ~800°C, carry out the metal ion diffusion step on the baked multilayer structure" or "immerse the sintered multilayer structure in a mixed resin glue containing alkali metal ions at a concentration of 0.1%~4.9% In the second solution; taking the sintered multi-layer structure out of the second solution and then performing a drying step to form a baked multi-layer structure; The dry multi-layer structure carries out the metal ion diffusion step" technical solution to reduce the leakage current and improve the flow capacity (that is, the maximum peak current value (maximum peak current)).

Another beneficial effect of the present invention is that the multilayer varistor provided by the present invention can pass the "ratio of G to T1: 1:0.3~1.0", "the ratio of G to T2: 1:0.3~1.0" ", "The ratio of D11 to G is 1: 0.3~1.0", "The ratio of D12 to G is 1: 0.3~1.0", "The ratio of D21 to G is 1: 0.3~1.0" and "The ratio of D22 to G 1: 0.3~1.0” technical solution to reduce leakage current and increase flow capacity (ie maximum peak current value (maximum peak current)).

For enabling a further understanding of the present invention's features and technical content, please refer to the following relevant The detailed description and drawings of the present invention, however, the provided drawings are only for reference and illustration, and are not intended to limit the present invention.

V: multilayer varistor

1: Multi-layer stacking structure

1001: first side end

1002: second side end

10: Insulation carrier

101: Insulation upper cover

102: Insulation lower cover

103: insulating body

1031: first outer surface

1032: second outer surface

1033: the third outer surface

1034: the fourth outer surface

11: The first inner conductive layer

110F: First front exposed end

110B: the first rear embedded end

110L: The first left embedded end

110R: The first right embedded end

12: Second inner conductive layer

120F: Second front exposed end

120B: the second rear embedded end

120L: The second left embedded end

120R: The second right embedded end

2: External electrode structure

21: The first outer electrode layer

22: The second outer electrode layer

T1, T2: Thickness

G: Spacing

D11, D12, D21, D22: distance

FIG. 1 is a flow chart of the manufacturing method of the multilayer varistor provided by the first embodiment of the present invention.

FIG. 2 is a schematic perspective view of one viewing angle of the multi-layer stack structure provided by the second embodiment of the present invention.

FIG. 3 is a schematic perspective view of another viewing angle of the multi-layer stack structure provided by the second embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of a multi-layer stack structure provided by a second embodiment of the present invention.

FIG. 5 is a schematic perspective view of one viewing angle of the multilayer varistor provided by the second embodiment of the present invention.

FIG. 6 is a perspective view of another viewing angle of the multilayer varistor provided by the second embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of a multilayer varistor provided by a second embodiment of the present invention.

The following is a description of the implementation of the "multilayer varistor and its manufacturing method" disclosed in the present invention through specific specific examples. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be based on different viewpoints and applications, without departing from Various modifications and changes are made under the concept of the present invention. In addition, the drawings of the present invention are only for simple illustration, and are not drawn according to the actual size, which is stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention. In addition, the term "or" used herein may include any one or a combination of more of the associated listed items depending on the actual situation.

[first embodiment]

Referring to FIGS. 1 to 7, the first embodiment of the present invention provides a method for manufacturing a multilayer varistor, which includes: first, as shown in FIG. 1, providing an initial multilayer structure (step S100); then , as shown in Figure 1, the initial multi-layer structure is sintered to form a sintered multi-layer structure (step S102); then, as shown in Figure 1 and Figure 2 to Figure 4, the sintered multi-layer structure Manufactured into a multi-layer stack structure 1, the multi-layer stack structure 1 includes an insulating carrier 10, a plurality of first inner conductive layers 11 arranged in the insulating carrier 10, and a plurality of second inner conductive layers 12 arranged in the insulating carrier 10 (Step S104); Next, as shown in FIG. 1 and FIGS. A first outer electrode layer 21 of the conductive layer 11 and a second outer electrode layer 22 electrically contact the plurality of second inner conductive layers 12 (step S106 ). It should be noted that a plurality of first inner conductive layers 11 and a plurality of second inner conductive layers 12 are alternately arranged (as shown in FIGS. 2 to 4 ), and the first outer electrode layers 21 and the second outer electrode layers 22 are respectively A first side end 1001 and a second side end 1002 of the multi-layer stack structure 1 are covered (as shown in FIGS. 5 to 7 ). For example, the initial multilayer structure may be a multilayer varistor green body, and its overall shape and internal structure will be similar to the multilayer stack structure 1 shown in FIGS. 2 to 4 . In addition, the sintered multi-layer structure may be a multi-layer varistor cooked blank, and its overall shape and internal structure will be similar to the multi-layer stack structure 1 shown in FIGS. 2 to 4 . However, the present invention is not limited to the above-mentioned examples.

Furthermore, as shown in FIG. 1 , the step S104 of making the sintered multi-layer structure into a multi-layer stacked structure 1 can be, for example, step (A) or step (B). Wherein, the step (A) includes: firstly, immersing the sintered multilayer structure in a first solution (metal ion solution) containing "0.1%~4.9% concentration of alkali metal (LiNO ₃ )" for a period of time Between 30 and 120 seconds (step S1040(A)); then, the sintered multilayer structure is taken out from the first solution and then subjected to a drying step to form a baked multilayer structure (step S1042( A)); then, at a temperature between 600° C. and 800° C., the metal ion diffusion step is performed on the baked multilayer structure (step S1044 (A)). In addition, the step (B) includes: first, immersing the sintered multilayer structure in a second solution (metal ion solution) containing "a mixed resin glue containing alkali metal ions at a concentration of 0.1% to 4.9%" (step S1040(B)); then, take out the sintered multilayer structure from the second solution and perform a drying step to form a baked multilayer structure (step S1042(B)); then, in The temperature is between 600° C. and 800° C., and the metal ion diffusion step is performed on the baked multilayer structure (step S1044 (B)).

For example, as shown in FIG. 1 , before the step S102 of sintering the initial multilayer structure, the manufacturing method further includes: preheating the initial multilayer structure (step S101 ). In addition, in the step S101 of pre-heating the initial multi-layer structure, the initial multi-layer structure is heated at a temperature between 400°C and 600°C. In addition, in the step S102 of sintering the initial multi-layer structure, the initial multi-layer structure is sintered at a temperature between 800°C and 1000°C. However, the present invention is not limited to the above-mentioned examples.

[Second embodiment]

Referring to Fig. 2 to Fig. 7, the second embodiment of the present invention provides a multilayer varistor V, the multilayer varistor V is manufactured by using the manufacturing method provided in the first embodiment, and the multilayer varistor The resistor V includes a multilayer stack structure 1 and an external electrode structure 2 . Furthermore, the multi-layer stack structure 1 includes an insulating carrier 10, a plurality of first inner conductive layers 11 arranged in the insulating carrier 10, and a plurality of second inner conductive layers 12 arranged in the insulating carrier 10, and more first internal conduction Layers 11 are alternately arranged with a plurality of second inner conductive layers 12 . In addition, the external electrode structure 2 includes a first external electrode layer 21 electrically contacting a plurality of first internal conductive layers 11 and a second external electrode layer 22 electrically contacting a plurality of second internal conductive layers 12, and the first The external electrode layer 21 and the second external electrode layer 22 respectively cover a first side end 1001 and a second side end 1002 of the multilayer stack structure 1 .

Furthermore, as shown in FIG. 2 to FIG. 4 , the insulating carrier 10 includes an insulating upper cover 101 , an insulating lower cover 102 and an insulating body 103 connected between the insulating upper cover 101 and the insulating lower cover 102 . In addition, the periphery of the insulating body 103 has a first outer surface 1031, a second outer surface 1032, a third outer surface 1033 and a fourth outer surface 1034, and a plurality of first inner conductive layers 11 and a plurality of second inner conductive layers The inner conductive layers 12 are alternately arranged in the insulating body 103 .

Furthermore, as shown in FIG. 2 and FIG. 4 , each first inner conductive layer 11 has a first exposed front end 110F exposed from the first outer surface 1031 of the insulating body 103 , and a second exposed end 110F facing the insulating body 103 . A first rear buried end 110B of the outer surface 1032, a first left buried end 110L facing the third outer surface 1033 of the insulating body 103, and a first right buried end facing the fourth outer surface 1034 of the insulating body 103 terminal 110R. Furthermore, as shown in FIG. 2 , FIG. 4 , FIG. 5 and FIG. 7 , the first exposed front end 110F is in electrical contact with the first external electrode layer 21 , and the first rear embedded end 110B corresponds to the first exposed front end 110F. And is covered in the insulating body 103, the first left inner buried end 110L is connected between the first front exposed end 110F and the first rear buried end 110B and is covered in the insulating body 103, and the first right inner The buried terminal 110R is connected between the first exposed front terminal 110F and the first buried rear terminal 110B and is encapsulated in the insulating body 103 .

Furthermore, as shown in FIG. 3 and FIG. 4 , the second inner conductive layer 12 has a second exposed front end 120F exposed from the second outer surface 1032 of the insulating body 103 , facing the first outer surface of the insulating body 103 A second rear buried end 120B of 1031, a second left buried end 120L facing the fourth outer surface 1034 of the insulating body 103, and a second right buried end 120R facing the third outer surface 1033 of the insulating body 103 . Furthermore, as shown in FIG. 3 , FIG. 4 , FIG. 6 and FIG. 7 , the second front exposed end 120F is electrically in contact with the second external electrode layer 22 , and the second rear buried end 120B corresponds to the second front exposed end 120F. and Covered in the insulating body 103, the second left embedded end 120L is connected between the second front exposed end 120F and the second rear embedded end 120B and is covered in the insulating body 103, and the second right embedded The end 120R is connected between the second front exposed end 120F and the second rear buried end 120B and is encapsulated in the insulating body 103 .

It is worth noting that, as shown in Figures 2 to 4, the insulating carrier 10 meets the following conditions: the ratio of G to T1 is 1:0.3~1.0, the ratio of G to T2 is 1:0.3~1.0, the ratio of D11 to G The ratio is 1:0.3~1.0, the ratio of D12 to G is 1:0.3~1.0, the ratio of D21 to G is 1:0.3~1.0, and the ratio of D22 to G is 1:0.3~1.0. Wherein, as shown in FIG. 4 , T1 is the thickness of the insulating upper cover 101 , T2 is the thickness of the insulating lower cover 102 , and G is the distance between the first inner conductive layer 11 and the second inner conductive layer 12 adjacent to each other. As shown in FIG. 2 , D11 is the distance between the first left buried end 110L of the first inner conductive layer 11 and the third outer surface 1033 of the insulating body 103, and D12 is the first right end of the first inner conductive layer 11. The distance between the buried end 110R and the fourth outer surface 1034 of the insulating body 103 . As shown in FIG. 3 , D21 is the distance between the second left buried end 120L of the second inner conductive layer 12 and the fourth outer surface 1034 of the insulating body 103 , and D22 is the second right end of the second inner conductive layer 12 . The distance between the buried end 120R and the third outer surface 1033 of the insulating body 103 .

Please refer to the following Table 1, the present invention has a predetermined length (2.2±0.2mm), width (1.7±0.2mm), thickness (1.7±0.2mm) of the insulating carrier 10 and includes a plurality of first inner conductive layers 11 and the total number of layers of multiple second inner conductive layers 12 are tested using 8 layers, and the experimental results are as follows:

[Advantageous Effects of Embodiment]

One of the beneficial effects of the present invention is that the method of manufacturing a multilayer varistor provided by the present invention can be achieved by "immersing the sintered multilayer structure in a first alkali metal containing 0.1%~4.9% concentration. the time in one solution is between 30 and 120 seconds; removing the sintered multilayer structure from the first solution followed by a baking step to form a baked multilayer structure; and at a temperature of 600°C ~800°C, carry out the metal ion diffusion step on the baked multilayer structure" or "immerse the sintered multilayer structure in a mixed resin glue containing alkali metal ions at a concentration of 0.1%~4.9% In the second solution; taking the sintered multi-layer structure out of the second solution and then performing a drying step to form a baked multi-layer structure; The dry multi-layer structure carries out the metal ion diffusion step" technical solution to reduce the leakage current and improve the flow capacity (that is, the maximum peak current value (maximum peak current)).

Another beneficial effect of the present invention is that the multilayer varistor provided by the present invention can pass the "ratio of G to T1: 1:0.3~1.0", "the ratio of G to T2: 1:0.3~1.0" ", "The ratio of D11 to G is 1: 0.3~1.0", "The ratio of D12 to G is 1: 0.3~1.0", "The ratio of D21 to G is 1: 0.3~1.0" and "The ratio of D22 to G 1: 0.3~1.0” technical solution to reduce leakage current and increase flow capacity (ie maximum peak current value (maximum peak current)).

The content disclosed above is only a preferred feasible embodiment of the present invention, and does not therefore limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made by using the description and drawings of the present invention are included in the application of the present invention. within the scope of the patent.

1: Multi-layer stacking structure

10: Insulation carrier

1031: first outer surface

1032: second outer surface

1033: the third outer surface

1034: the fourth outer surface

11: The first inner conductive layer

110F: First front exposed end

110B: the first rear embedded end

110L: The first left embedded end

110R: The first right embedded end

12: Second inner conductive layer

120F: Second front exposed end

120B: the second rear embedded end

120L: The second left embedded end

120R: The second right embedded end

G: Spacing

D11, D12: distance

Claims (10)

A method for manufacturing a multilayer varistor, comprising: providing an initial multi-layered structure; sintering the initial multilayer structure to form a sintered multilayer structure; The sintered multi-layer structure is fabricated into a multi-layer stack structure, the multi-layer stack structure includes an insulating carrier, a plurality of first inner conductive layers arranged in the insulating carrier, and a plurality of first inner conductive layers arranged in the insulating carrier a plurality of second inner conductive layers, and a plurality of the first inner conductive layers are arranged alternately with a plurality of the second inner conductive layers; and forming an external electrode structure to partially cover the multi-layer stack structure, the external electrode structure includes a first external electrode layer electrically contacting a plurality of the first internal conductive layers and electrically contacting a plurality of the first internal conductive layers A second outer electrode layer of the second inner conductive layer, and the first outer electrode layer and the second outer electrode layer respectively cover a first side end and a second side of the multi-layer stack structure Ends; Wherein, the step of making the sintered multilayer structure into the multilayer stacked structure further includes step (A) or step (B); Wherein, the step (A) includes: immersing the sintered multilayer structure in a first solution containing an alkali metal at a concentration of 0.1% to 4.9% for 30 to 120 seconds; The sintered multilayer structure is taken out from the first solution and then subjected to a drying step to form a baked multilayer structure; and at a temperature between 600°C and 800°C, The multilayer structure carries out the metal ion diffusion step; Wherein, the step (B) includes: soaking the sintered multilayer structure in a second solution comprising a mixed resin glue containing alkali metal ions at a concentration of 0.1% to 4.9%; The sintered multi-layer structure is taken out from the second solution and subjected to a drying step to form a baked multi-layer structure; The structure undergoes a metal ion diffusion step. The method for manufacturing a multilayer varistor according to Claim 1, wherein, before the step of sintering the initial multilayer structure, the manufacturing method further includes: pre-sintering the initial multilayer structure Heating; wherein, in the step of pre-heating the initial multi-layer structure, the initial multi-layer structure is heated at a temperature between 400°C and 600°C; wherein, the initial In the step of sintering the multilayer structure, the initial multilayer structure is sintered at a temperature between 800°C and 1000°C. A multilayer varistor, the multilayer varistor is made by the manufacturing method described in claim 1, the multilayer varistor includes the multilayer stack structure and the external electrode structure; Wherein, the insulating carrier includes an insulating upper cover, an insulating lower cover, and an insulating body connected between the insulating upper cover and the insulating lower cover, and the surrounding of the insulating body has a first outer surface, a first Two outer surfaces, a third outer surface, and a fourth outer surface, and a plurality of the first inner conductive layers and a plurality of the second inner conductive layers are alternately arranged in the insulating body; Wherein, each of the first inner conductive layers has a first exposed front end exposed from the first outer surface of the insulating body, and a first rear end facing the second outer surface of the insulating body. The buried end, a first left buried end facing the third outer surface of the insulating body, and a first right buried end facing the fourth outer surface of the insulating body, the first The front exposed end electrically contacts the first external electrode layer, the first rear embedded end corresponds to the first front exposed end and is covered in the insulating body, and the first left embedded end The end is connected between the first exposed front end and the first rear embedded end and is covered in the insulating body, and the first right embedded end is connected to the first exposed front end Between the first rear buried end and covered in the insulating body; Wherein, the second inner conductive layer has a second front exposed end exposed from the second outer surface of the insulating body, a second rear embedded end facing the first outer surface of the insulating body end, a second left inner buried end facing the fourth outer surface of the insulating body and a second right inner buried end facing the third outer surface of the insulating body, the second front exposed terminal electrically contacting the second external electrode layer, the second rear buried terminal is corresponding to the second front exposed terminal and covered in the insulating body, and the second left buried terminal is connected to between the second exposed front end and the second rear embedded end and covered in the insulating body, and the second right embedded end is connected to the second exposed front end and the second embedded end Between the second rear buried ends and covered in the insulating body. The multilayer varistor as described in claim item 3, wherein the insulating carrier meets the following conditions: the ratio of G to T1 is 1:0.3~1.0, the ratio of G to T2 is 1:0.3~1.0, D11 and The ratio of G is 1:0.3~1.0, the ratio of D12 to G is 1:0.3~1.0, the ratio of D21 to G is 1:0.3~1.0, and the ratio of D22 to G is 1:0.3~1.0; Wherein, T1 is the thickness of the insulating upper cover, T2 is the thickness of the insulating lower cover, G is the distance between the adjacent first inner conductive layer and the second inner conductive layer, D11 is the The distance between the first left buried end of the first inner conductive layer and the third outer surface of the insulating body, D12 is the first right buried end of the first inner conductive layer The distance from the fourth outer surface of the insulating body, D21 is the distance between the second left buried end of the second inner conductive layer and the fourth outer surface of the insulating body The distance, D22, is the distance between the second right buried end of the second inner conductive layer and the third outer surface of the insulating body. A method for manufacturing a multilayer varistor, comprising: providing an initial multi-layered structure; sintering the initial multilayer structure to form a sintered multilayer structure; The sintered multi-layer structure is fabricated into a multi-layer stack structure, the multi-layer stack structure includes an insulating carrier, a plurality of first inner conductive layers arranged in the insulating carrier, and a plurality of first inner conductive layers arranged in the insulating carrier a plurality of second inner conductive layers; and forming an external electrode structure to partially cover the multi-layer stack structure, the external electrode structure includes a first external electrode layer electrically contacting a plurality of the first internal conductive layers and electrically contacting a plurality of the first internal conductive layers a second outer electrode layer of the second inner conductive layer; Wherein, the step of making the sintered multilayer structure into the multilayer stacked structure further includes: soaking the sintered multilayer structure in a metal ion solution; taking the sintered multilayer structure out of the metal ion solution and then performing a drying step to form a baked multilayer structure; and At a temperature between 600°C and 800°C, the metal ion diffusion step is performed on the baked multilayer structure. The method for manufacturing a multilayer varistor according to claim 5, wherein, in the step of soaking the sintered multilayer structure in the metal ion solution, the metal ion solution is a first A solution or a second solution, the first solution contains alkali metal at a concentration of 0.1% to 4.9%, and the second solution includes a mixed resin glue containing alkali metal ions at a concentration of 0.1% to 4.9%. The method for manufacturing a multilayer varistor according to Claim 5, wherein, before the step of sintering the initial multilayer structure, the manufacturing method further includes: pre-sintering the initial multilayer structure Heating; wherein, in the step of pre-heating the initial multi-layer structure, the initial multi-layer structure is heated at a temperature between 400°C and 600°C; wherein, the initial In the step of sintering the multilayer structure, the initial multilayer structure is sintered at a temperature between 800°C and 1000°C. A multilayer varistor, the multilayer varistor is made by the manufacturing method described in claim 5, the multilayer varistor includes the multilayer stack structure and the external electrode structure; Wherein, the insulating carrier includes an insulating upper cover, an insulating lower cover, and an insulating body connected between the insulating upper cover and the insulating lower cover, and the surrounding of the insulating body has a first outer surface, a first Two outer surfaces, a third outer surface, and a fourth outer surface, and a plurality of the first inner conductive layers and a plurality of the second inner conductive layers are alternately arranged in the insulating body; Wherein, each of the first inner conductive layers has a first exposed front end exposed from the first outer surface of the insulating body, and a first rear end facing the second outer surface of the insulating body. The buried end, a first left buried end facing the third outer surface of the insulating body, and a first right buried end facing the fourth outer surface of the insulating body, the first The front exposed end electrically contacts the first external electrode layer, the first rear embedded end corresponds to the first front exposed end and is covered in the insulating body, and the first left embedded end The end is connected between the first exposed front end and the first rear embedded end and is covered in the insulating body, and the first right embedded end is connected to the first exposed front end Between the first rear buried end and covered in the insulating body; Wherein, the second inner conductive layer has a second front exposed end exposed from the second outer surface of the insulating body, a second rear embedded end facing the first outer surface of the insulating body end, a second left inner buried end facing the fourth outer surface of the insulating body and a second right inner buried end facing the third outer surface of the insulating body, the second front exposed terminal electrically contacting the second external electrode layer, the second rear buried terminal is corresponding to the second front exposed terminal and covered in the insulating body, and the second left buried terminal is connected to between the second exposed front end and the second rear embedded end and covered in the insulating body, and the second right embedded end is connected to the second exposed front end and the second embedded end Between the second rear buried ends and covered in the insulating body. The multilayer varistor as described in claim item 8, wherein the insulating carrier meets the following conditions: the ratio of G to T1 is 1:0.3~1.0, the ratio of G to T2 is 1:0.3~1.0, D11 and The ratio of G is 1:0.3~1.0, the ratio of D12 to G is 1:0.3~1.0, the ratio of D21 to G is 1:0.3~1.0, and the ratio of D22 to G is 1:0.3~1.0; Wherein, T1 is the thickness of the insulating upper cover, T2 is the thickness of the insulating lower cover, G is the distance between the adjacent first inner conductive layer and the second inner conductive layer, D11 is the The distance between the first left buried end of the first inner conductive layer and the third outer surface of the insulating body, D12 is the first right buried end of the first inner conductive layer The distance from the fourth outer surface of the insulating body, D21 is the distance between the second left buried end of the second inner conductive layer and the fourth outer surface of the insulating body The distance, D22, is the distance between the second right buried end of the second inner conductive layer and the third outer surface of the insulating body. A multilayer varistor comprising: A multi-layer stack structure, the multi-layer stack structure includes an insulating carrier, a plurality of first inner conductive layers arranged in the insulating carrier, and a plurality of second inner conductive layers arranged in the insulating carrier, And a plurality of the first inner conductive layers and a plurality of the second inner conductive layers are alternately arranged; and An external electrode structure, the external electrode structure partially covers the multi-layer stack structure, the external electrode structure includes a first external electrode layer electrically contacting a plurality of the first internal conductive layers and electrically contacting A second outer electrode layer of the plurality of second inner conductive layers, and the first outer electrode layer and the second outer electrode layer cover a first side end and a first side end of the multi-layer stack structure respectively. a second side end; Wherein, the insulating carrier includes an insulating upper cover, an insulating lower cover, and an insulating body connected between the insulating upper cover and the insulating lower cover, and the surrounding of the insulating body has a first outer surface, a first Two outer surfaces, a third outer surface, and a fourth outer surface, and a plurality of the first inner conductive layers and a plurality of the second inner conductive layers are alternately arranged in the insulating body; Wherein, each of the first inner conductive layers has a first exposed front end exposed from the first outer surface of the insulating body, and a first rear end facing the second outer surface of the insulating body. The buried end, a first left buried end facing the third outer surface of the insulating body, and a first right buried end facing the fourth outer surface of the insulating body, the first The front exposed end electrically contacts the first external electrode layer, the first rear embedded end corresponds to the first front exposed end and is covered in the insulating body, and the first left embedded end The end is connected between the first exposed front end and the first rear embedded end and is covered in the insulating body, and the first right embedded end is connected to the first exposed front end Between the first rear buried end and covered in the insulating body; Wherein, the second inner conductive layer has a second front exposed end exposed from the second outer surface of the insulating body, a second rear embedded end facing the first outer surface of the insulating body end, a second left inner buried end facing the fourth outer surface of the insulating body and a second right inner buried end facing the third outer surface of the insulating body, the second front exposed terminal electrically contacting the second external electrode layer, the second rear buried terminal is corresponding to the second front exposed terminal and covered in the insulating body, and the second left buried terminal is connected to between the second exposed front end and the second rear embedded end and covered in the insulating body, and the second right embedded end is connected to the second exposed front end and the second embedded end Between the second rear buried ends and covered in the insulating body; Wherein, the insulating carrier meets the following conditions: the ratio of G to T1 is 1:0.3~1.0, the ratio of G to T2 is 1:0.3~1.0, the ratio of D11 to G is 1:0.3~1.0, and the ratio of D12 to G The ratio of D21 to G is 1:0.3~1.0, the ratio of D21 to G is 1:0.3~1.0, and the ratio of D22 to G is 1:0.3~1.0; Wherein, T1 is the thickness of the insulating upper cover, T2 is the thickness of the insulating lower cover, G is the distance between the adjacent first inner conductive layer and the second inner conductive layer, D11 is the The distance between the first left buried end of the first inner conductive layer and the third outer surface of the insulating body, D12 is the first right buried end of the first inner conductive layer The distance from the fourth outer surface of the insulating body, D21 is the distance between the second left buried end of the second inner conductive layer and the fourth outer surface of the insulating body The distance, D22, is the distance between the second right buried end of the second inner conductive layer and the third outer surface of the insulating body.