CN210776675U - Circuit for solving I2C address conflict in PCB multiplexing design - Google Patents
Circuit for solving I2C address conflict in PCB multiplexing design Download PDFInfo
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- CN210776675U CN210776675U CN201922107734.0U CN201922107734U CN210776675U CN 210776675 U CN210776675 U CN 210776675U CN 201922107734 U CN201922107734 U CN 201922107734U CN 210776675 U CN210776675 U CN 210776675U
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Abstract
The utility model provides a circuit for solving I2C address conflict in multiplexing design of PCB, include first PCB device and second PCB device and the third PCB device as the main installation completely the same as the slave unit, first PCB device includes first PCB and sets up the first device subassembly above that, the second PCB device includes second PCB and sets up the second device subassembly above that, the third PCB device includes third PCB and sets up the CPU above that, be equipped with first connector on the first PCB, be equipped with the second connector on the second PCB, be equipped with third connector and fourth connector on the third PCB, first connector is pegged graft with the third connector, the second connector is pegged graft with the fourth connector. The utility model discloses a master device and the inserting of slave unit connector have realized the automatic problem of I2C address conflict in avoiding the multiplexing design of PCB, need not software control, and it is comparatively simple to use.
Description
Technical Field
The utility model relates to a multiplexing design technical field of PCB specifically is a circuit for solving I2C address conflict in the multiplexing design of PCB.
Background
Multiple devices would typically be required on an I2C bus, but slaves with the same address are not allowed to exist on the same I2C bus. If two identical PCB devices (slave devices) are used in one complete machine, when the two identical PCB devices are hung on the same I2C address, address conflict is inevitably caused if no control is performed, and normal communication is affected.
In the prior art, devices such as a CPU (central processing unit) and the like are added on the same PCB (slave device), and I2C addresses are configured through the CPU in the PCB by using auxiliary tools such as software and the like, so that the transmission of I2C signals in the respective PCBs is completed, and the use is complicated.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a circuit for solving I2C address conflict in the multiplexing design of PCB, this circuit need not just can avoid the problem of I2C address conflict in the multiplexing design of PCB automatically with the help of software.
The technical scheme of the utility model is that:
a circuit for solving I2C address conflict in PCB multiplexing design comprises a first PCB device and a second PCB device as slave equipment and a third PCB device as master equipment, wherein the first PCB device and the second PCB device are completely the same, the first PCB device comprises a first PCB and a first device assembly arranged on the first PCB, the second PCB device comprises a second PCB and a second device assembly arranged on the second PCB, the third PCB device comprises a third PCB and a CPU arranged on the third PCB, the first PCB is further provided with a first connector, the second PCB is further provided with a second connector, the third PCB is further provided with a third connector and a fourth connector, the first connector is plugged with the third connector, and the second connector is plugged with the fourth connector;
the port input pin of the first connector is connected to the I2C variable address pin of the first device component, and a node between the port input pin of the first connector and the I2C variable address pin of the first device component is connected to VCC through a first pull-up resistor provided on the first PCB;
the port input pin of the second connector is connected with the I2C variable address pin of the second device assembly, and a node between the port input pin of the second connector and the I2C variable address pin of the second device assembly is connected with VCC through a second pull-up resistor arranged on the second PCB;
a port input pin of the third connector is grounded, and a port input pin of the fourth connector is suspended; an I2C signal output pin of the CPU is connected with an I2C signal input pin of the first device assembly sequentially through the third connector and the first connector; and the I2C signal output pin of the CPU is connected with the I2C signal input pin of the second device assembly through the fourth connector and the second connector in sequence.
The circuit for solving the I2C address conflict in the PCB multiplexing design adopts FFC connectors as the first connector, the second connector, the third connector and the fourth connector.
The circuit for solving the I2C address conflict in the PCB multiplexing design is characterized in that the device component is a DAC chip.
According to the above technical scheme, the utility model discloses a to inserting of connector between master and the slave unit, realized the automatic problem of avoiding I2C address conflict in the multiplexing design of PCB, need not software control, use comparatively simply.
Drawings
Fig. 1 is a schematic structural diagram of the present invention.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments.
As shown in fig. 1, a circuit for resolving I2C address conflict in PCB multiplexing design includes a first PCB apparatus and a second PCB apparatus as slaves and a third PCB apparatus as a master, the first PCB apparatus and the second PCB apparatus are identical.
The first PCB apparatus includes a first PCB1 and a first device assembly 11, a first connector 12, and a first pull-up resistor 13 disposed on a first PCB1, the second PCB apparatus includes a second PCB2 and a second device assembly 21, a second connector 22, and a second pull-up resistor 23 disposed on a second PCB2, and the third PCB apparatus includes a third PCB3 and a CPU31, a third connector 32, and a fourth connector 33 disposed on a third PCB 3.
The first connector 12 is plugged with the third connector 32, the PINx pin (port input pin) of the third connector 32 is grounded, the PINx pin (port input pin) of the first connector 12 is connected to the I2C variable address pin of the first device assembly 11, and a node between the PINx pin (port input pin) of the first connector 12 and the I2C variable address pin of the first device assembly 11 is connected to VCC through the first pull-up resistor 13.
The second connector 22 is plugged into the fourth connector 33, the PINx pin (port input pin) of the fourth connector 33 is floating, the PINx pin (port input pin) of the second connector 22 is connected to the I2C variable address pin of the second device assembly 21, and a node between the PINx pin (port input pin) of the second connector 22 and the I2C variable address pin of the second device assembly 21 is connected to VCC through the second pull-up resistor 23.
The I2C signal output pin of the CPU31 is connected to the I2C signal input pin of the first device package 11 through the third connector 32 and the first connector 12 in this order; the I2C signal output pin of the CPU31 is connected to the I2C signal input pin of the second device assembly 21 through the fourth connector 33 and the second connector 22 in this order.
The first connector 12, the second connector 22, the third connector 32, and the fourth connector 33 are all common connectors, such as flexible flat cable connectors (FFC connectors), board connectors, and the like. The first device component 11 and the second device component 21 may be various types of chips, such as DAC chips, etc.
The utility model discloses a theory of operation:
since the first connector 12 is plugged into the third connector 32 (the PINx pins of the two are on) and the PINx pin of the third connector 32 is grounded, the I2C variable address pin a0 of the first device assembly 11 is always at a low level, i.e., a0 is 0; since the second connector 22 is plugged into the fourth connector 33 (the PINx pins of the second connector and the fourth connector 33 are on), and the PINx pin of the fourth connector 33 is floating, the I2C variable address pin a0 of the second device component 21 is always at a high level, i.e., a0 is equal to 1; since the I2C variable address pin A0 of the first device assembly 11 and the I2C variable address pin A0 of the second device assembly 21 always have different levels, the problem of I2C address conflicts between the first and second PCB devices is circumvented.
To sum up, the utility model discloses need not only through the interpolation of connector between main equipment and the slave unit with the help of software, just realized controlling the variable address pin of I2C of installing the subassembly on two the same PCB devices and have different levels all the time, and then realized avoiding the problem that I2C address conflicts appears in the multiplex design of PCB.
The above-mentioned embodiments are only to describe the preferred embodiments of the present invention, but not to limit the scope of the present invention, and various modifications and improvements made by those skilled in the art without departing from the design spirit of the present invention should fall into the protection scope defined by the claims of the present invention.
Claims (3)
1. A circuit for resolving I2C address conflict in PCB multiplexing design, comprising a first PCB apparatus and a second PCB apparatus as a slave device and a third PCB apparatus as a master device, the first PCB apparatus and the second PCB apparatus being identical, the first PCB apparatus comprising a first PCB and a first apparatus assembly disposed on the first PCB, the second PCB apparatus comprising a second PCB and a second apparatus assembly disposed on the second PCB, the third PCB apparatus comprising a third PCB and a CPU disposed on the third PCB, characterized in that:
the first PCB is also provided with a first connector, the second PCB is also provided with a second connector, the third PCB is also provided with a third connector and a fourth connector, the first connector is spliced with the third connector, and the second connector is spliced with the fourth connector;
the port input pin of the first connector is connected to the I2C variable address pin of the first device component, and a node between the port input pin of the first connector and the I2C variable address pin of the first device component is connected to VCC through a first pull-up resistor provided on the first PCB;
the port input pin of the second connector is connected with the I2C variable address pin of the second device assembly, and a node between the port input pin of the second connector and the I2C variable address pin of the second device assembly is connected with VCC through a second pull-up resistor arranged on the second PCB;
a port input pin of the third connector is grounded, and a port input pin of the fourth connector is suspended; an I2C signal output pin of the CPU is connected with an I2C signal input pin of the first device assembly sequentially through the third connector and the first connector; and the I2C signal output pin of the CPU is connected with the I2C signal input pin of the second device assembly through the fourth connector and the second connector in sequence.
2. The circuit for resolving I2C address conflicts in PCB mux designs of claim 1, wherein: the first connector, the second connector, the third connector and the fourth connector are all FFC connectors.
3. The circuit for resolving I2C address conflicts in PCB mux designs of claim 1, wherein: the device component is a DAC chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922107734.0U CN210776675U (en) | 2019-11-29 | 2019-11-29 | Circuit for solving I2C address conflict in PCB multiplexing design |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922107734.0U CN210776675U (en) | 2019-11-29 | 2019-11-29 | Circuit for solving I2C address conflict in PCB multiplexing design |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210776675U true CN210776675U (en) | 2020-06-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922107734.0U Active CN210776675U (en) | 2019-11-29 | 2019-11-29 | Circuit for solving I2C address conflict in PCB multiplexing design |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210776675U (en) |
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2019
- 2019-11-29 CN CN201922107734.0U patent/CN210776675U/en active Active
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Address after: Fuhuang New Vision Building, No. 77 Wutaishan Road, Baohe Economic Development Zone, Hefei City, Anhui Province, 230051 Patentee after: Hefei Zhongke Junda Vision Technology Co.,Ltd. Address before: 230088 Room 107, Building 3, Tiandao 10 Software Park, Hefei High-tech Zone, Anhui Province Patentee before: HEFEI FUHUANG JUNDA HIGH-TECH INFORMATION TECHNOLOGY Co.,Ltd. |