CN210724552U - Drive circuit with adjustable pulse width - Google Patents
Drive circuit with adjustable pulse width Download PDFInfo
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- CN210724552U CN210724552U CN201922309670.2U CN201922309670U CN210724552U CN 210724552 U CN210724552 U CN 210724552U CN 201922309670 U CN201922309670 U CN 201922309670U CN 210724552 U CN210724552 U CN 210724552U
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Abstract
The utility model discloses a drive circuit of adjustable pulse width IN power field, swing circuit and totem pole circuit including the self-excitation, swing the circuit mainly by two NAND gates U1A, U1D and a set of charging and discharging circuit and constitute from the self-excitation, totem pole circuit mainly comprises two pairs of triode Q1, Q2, the signal end of DRV IN is connected with U1A's 1 foot, U1A's 3 feet and U1D's 12, 13 feet reach charging and discharging circuit's one end is connected, U1D's 11 feet and charging and discharging circuit's other end connecting resistance R7's one end, resistance R7's the other end is connected with parallelly connected triode Q1, Q2's base, triode Q1, Q2's projecting pole is connected with DRV IN's signal end, has higher duty cycle control range, can realize under fixed switching frequency that the duty cycle is adjustable. And the larger the difference of the time constants of charging and discharging is, the wider the duty ratio adjustable range is.
Description
Technical Field
The utility model relates to a power technical field specifically is a drive circuit of adjustable pulsewidth.
Background
In the power supply industry, most of the analog open-loop control needs to be realized by using an analog IC power management chip (UC38XX series, SG3525, etc.) to shield the voltage and current loops of the chip, so that the chip works in the maximum pulse width state, thereby realizing the open-loop control.
Based on this, the utility model designs an adjustable pulse width's drive circuit to solve the above-mentioned problem.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a drive circuit of adjustable pulse width is applicable to the drive circuit among the open loop control circuit, and drive signal's pulse width is adjusted to the accessible reaches a fixed duty cycle, and switching frequency is adjustable to solve the problem that proposes among the above-mentioned background art.
In order to achieve the above object, the utility model provides a following technical scheme: a driving circuit with adjustable pulse width comprises a self-oscillation circuit and a totem-pole circuit, wherein the self-oscillation circuit mainly comprises two NAND gates U1A, U1D and a group of charging and discharging circuits, the totem-pole circuit mainly comprises two pairs of triodes Q1 and Q2, a signal end of DRVIN is connected with a pin 1 of U1A, a pin 3 of U1A is connected with pins 12 and 13 of U1D and one end of the charging and discharging circuits, a pin 11 of U1D and the other end of the charging and discharging circuits are connected with one end of a resistor R7, the other end of the resistor R7 is connected with bases of triodes Q1 and Q2 which are connected IN parallel, and emitting electrodes of the triodes Q1 and Q2 are connected with a signal end of DRV IN.
Preferably, the device further includes a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a diode D3, and a diode D4, wherein the signal terminal of the DRV IN is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the capacitor C1, one end of the resistor R2, the anode of the diode D4, and the cathode of the diode D3, the other end of the capacitor C1 is connected to the anode of the diode D3, the anode of the diode D3 is connected to the input ground, the cathode of the diode D4 is connected to the positive electrode of the 12V power supply, the other end of the resistor R68642 is connected to one end of the resistor R635928, one end of the capacitor C9, and the 1 pin of U1A, the other end of the resistor R3 is connected to the other end of the capacitor C2, and the other end of the.
Preferably, the charging and discharging circuit comprises a charging circuit and a discharging circuit, the charging circuit is formed by sequentially connecting the pins 3, D5, R5 and C4 of U1A in series, the discharging circuit is formed by sequentially connecting the pins 3 of C4, R6, D6 and U1A in series, and the pins 12 and 13 of U1D are respectively connected with the anode of the diode D5 and the cathode of the diode D6.
Preferably, the pin 2 of the U1A is connected to one end of a resistor R4, and the other end of the resistor R4 is connected to the charge and discharge circuit.
Preferably, the 7 pins of the U1D are connected to the input ground, the 14 pins of the U1D are respectively connected to the positive electrode of the 12V power supply and one end of a capacitor C3, and the other end of the capacitor C3 is connected to the input ground.
Preferably, the collector of the transistor Q1 is connected to the positive electrode of the 12V power supply and one end of a capacitor C5, the other end of the capacitor C5 is connected to the input ground, and the collector of the transistor Q1 is connected to the input ground.
Compared with the prior art, the beneficial effects of the utility model are that: the duty cycle adjusting range is high, and the duty cycle adjusting range can be realized only by two groups of logic gates (NAND gates) and one group of charging and discharging circuits. The duty ratio can be adjusted under a fixed switching frequency by adjusting the charging time T1 and the discharging time T2 of the charging and discharging loop and making T1+ T2 equal to T (switching period). And the larger the difference of the time constants of charging and discharging is, the wider the duty ratio adjustable range is.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
Referring to fig. 1, the present invention provides a technical solution: a driving circuit with adjustable pulse width comprises a self-oscillation circuit and a totem-pole circuit, wherein the self-oscillation circuit mainly comprises two NAND gates U1A, U1D and a group of charging and discharging circuits, the totem-pole circuit mainly comprises two pairs of triodes Q1 and Q2, a signal end of DRV IN is connected with a pin 1 of U1A, a pin 3 of U1A is connected with pins 12 and 13 of U1D and one end of the charging and discharging circuits, a pin 11 of U1D and the other end of the charging and discharging circuits are connected with one end of a resistor R7, the other end of the resistor R7 is connected with bases of the triodes Q1 and Q2 which are connected IN parallel, emitting electrodes of the triodes Q1 and Q2 are connected with the signal end of the DRV IN, a pin 2 of the U1A is connected with one end of a resistor R4, and the other end of the resistor R4 is connected into the charging and discharging circuits.
The high-voltage power supply further comprises a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a diode D3 and a diode D4, wherein the signal end of the DRV IN is connected with one end of the resistor R1, the other end of the resistor R1 is respectively connected with one end of the capacitor C1, one end of the resistor R2, the anode of the diode D4 and the cathode of the diode D3, the other end of the capacitor C1 is connected with the anode of the diode D3, the anode of the diode D3 is connected with an input ground, the cathode of the diode D4 is connected with the anode of a 12V power supply, the other end of the resistor R2 is connected with one end of the resistor R3, one end of the capacitor C9 and the pin 1 of U1A, the other end of the resistor R3 is connected with the other end of the capacitor C2, and the other end of the capacitor.
The charging and discharging circuit comprises a charging circuit and a discharging circuit, the charging circuit is formed by sequentially connecting a pin 3 of U1A, a pin D5, a pin R5 and a pin C4 in series, the discharging circuit is formed by sequentially connecting a pin 3 of C4, a pin R6, a pin D6 and a pin 3 of U1A in series, and the pins 12 and 13 of U1D are respectively connected with an anode of a diode D5 and a cathode of the diode D6.
The 7 pins of the U1D are connected with the input ground, the 14 pins of the U1D are respectively connected with the anode of a 12V power supply and one end of a capacitor C3, and the other end of the capacitor C3 is connected with the input ground. The collector of the transistor Q1 is connected to the positive electrode of the 12V power supply and one end of a capacitor C5, the other end of the capacitor C5 is connected to the input ground, and the collector of the transistor Q1 is connected to the input ground.
The specific working principle is as follows:
when the DRV IN signal is at low level, pin 1 of U1A is at low level, pin 3 output of U1A is at high level (0 goes OUT of 1), and is inverted to low level through U1D level, transistor Q2 under totem pole is turned on, DRV OUT is grounded through transistor Q2 and output is zero, and at this time, the output is locked no matter how the 2-pin level state of U1A.
When the DRV IN signal is high, pin 1 of U1A is high, U1A is turned on and oscillation begins. Assuming that the pin 3 output of U1A is high, totem-pole transistor Q2 is on after U1D level flip to low, and DRV OUT is low after transistor Q2 ground. At this time, the 3 pins-D5-R5-C4 of U1A form a charging loop, the Ua potential rises, when the Ua rises to the high level of U1A, the 3 pin output of U1A is at low level, and the level is inverted to high level through U1D, and the totem-pole transistor Q1 turns on DRVOUT to be high through the transistor Q1, and then the 12V output is high. At the moment, pins C4-R6-D6-U1A-3 form a discharge loop, the potential of Ua drops, when the Ua drops to the low level of U1A, the output of the pin U1A3 is at the high level, the pin U1A3 is inverted to be at the low level through the level U1D, a triode Q2 is conducted under a totem pole, DRV OUT is grounded and output to be at the low level through the triode Q2, and the circuit starts to oscillate repeatedly.
In summary, it can be seen that the charging time T1 of the capacitor C4 is the low level duration of the driving signal, the discharging time T2 of the capacitor C4 is the high level duration of the driving signal, and the charging and discharging time of the capacitor C4 can be changed by changing the resistances of the capacitors R5 and R6, so long as T1+ T2 is T (switching period), the duty ratio can be adjusted at a fixed switching frequency.
In the description herein, references to the description of "one embodiment," "an example," "a specific example," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The preferred embodiments of the present invention disclosed above are intended only to help illustrate the present invention. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best understand the invention for and utilize the invention. The present invention is limited only by the claims and their full scope and equivalents.
Claims (6)
1. A drive circuit with adjustable pulse width, comprising: the self-excited oscillation circuit mainly comprises two NAND gates U1A, U1D and a group of charging and discharging circuits, the totem pole circuit mainly comprises two pairs of triodes Q1 and Q2, the signal end of the DRV IN is connected with a pin 1 of U1A, a pin 3 of U1A is connected with pins 12 and 13 of U1D and one end of the charging and discharging circuits, a pin 11 of U1D and the other end of the charging and discharging circuits are connected with one end of a resistor R7, the other end of the resistor R7 is connected with bases of triodes Q1 and Q2 which are connected IN parallel, and emitting electrodes of the triodes Q1 and Q2 are connected with the signal end of the DRVIN.
2. The adjustable pulse width driver circuit of claim 1, wherein: the signal end of the DRV IN is connected with one end of the resistor R1, the other end of the resistor R1 is connected with one end of the capacitor C1, one end of the resistor R2, the anode of the diode D4 and the cathode of the diode D3, the other end of the capacitor C1 is connected with the anode of the diode D3, the anode of the diode D3 is connected with the input ground, the cathode of the diode D4 is connected with the anode of a 12V power supply, the other end of the resistor R2 is connected with one end of the resistor R3, one end of the capacitor C2 and the pin 1 of U1A, the other end of the resistor R3 is connected with the other end of the capacitor C2, and the other end of the capacitor C2 is connected with the input ground.
3. The adjustable pulse width driver circuit of claim 1, wherein: the charging and discharging circuit comprises a charging circuit and a discharging circuit, the charging circuit is formed by sequentially connecting a pin 3, a pin D5, a pin R5 and a pin C4 of U1A in series, the discharging circuit is formed by sequentially connecting pins C4, a pin R6, a pin D6 and a pin 3 of U1A in series, and the pins 12 and 13 of U1D are respectively connected with an anode of a diode D5 and a cathode of the diode D6.
4. The adjustable pulse width driver circuit of claim 3, wherein: the pin 2 of the U1A is connected with one end of a resistor R4, and the other end of the resistor R4 is connected in a charging and discharging circuit.
5. The adjustable pulse width driver circuit of claim 4, wherein: the 7 pins of the U1D are connected with the input ground, the 14 pins of the U1D are respectively connected with the anode of a 12V power supply and one end of a capacitor C3, and the other end of the capacitor C3 is connected with the input ground.
6. The adjustable pulse width driver circuit of claim 5, wherein: the collector of the transistor Q1 is connected to the positive electrode of the 12V power supply and one end of a capacitor C5, the other end of the capacitor C5 is connected to the input ground, and the collector of the transistor Q1 is connected to the input ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922309670.2U CN210724552U (en) | 2019-12-20 | 2019-12-20 | Drive circuit with adjustable pulse width |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922309670.2U CN210724552U (en) | 2019-12-20 | 2019-12-20 | Drive circuit with adjustable pulse width |
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| Publication Number | Publication Date |
|---|---|
| CN210724552U true CN210724552U (en) | 2020-06-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN201922309670.2U Active CN210724552U (en) | 2019-12-20 | 2019-12-20 | Drive circuit with adjustable pulse width |
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|---|---|
| CN (1) | CN210724552U (en) |
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- 2019-12-20 CN CN201922309670.2U patent/CN210724552U/en active Active
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