CN210724306U - Power failure emergency processing system and chip - Google Patents
Power failure emergency processing system and chip Download PDFInfo
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- CN210724306U CN210724306U CN201921692153.1U CN201921692153U CN210724306U CN 210724306 U CN210724306 U CN 210724306U CN 201921692153 U CN201921692153 U CN 201921692153U CN 210724306 U CN210724306 U CN 210724306U
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Abstract
The utility model provides a fall electric emergency treatment system and chip, it includes: the power failure detection module is used for generating a timing enabling signal when detecting that the power supply is powered down; the power failure timing module is connected with the power failure detection module and used for starting timing according to the timing enabling signal and generating a control enabling signal; and the power-off control module is connected with the power-down timing module and used for transmitting the electric energy stored in the power-on state to the power supply according to the control enabling signal. The utility model discloses make other module extension operating time such as smart electric meter's power consumption detection module, storage module and wireless communication module, and then realize that smart electric meter in time reports the purpose of power consumption information after falling the electricity.
Description
Technical Field
The utility model relates to a power-down control technical field indicates a power-down emergency processing system and chip especially.
Background
With the development of national economic technology and the improvement of living standard of people, electric energy becomes essential energy in production and life of people, and electric energy metering is an important function of an electric power system.
However, the current electricity consumption information detected by the intelligent electric meter needs to be reported to the intelligent electric meter through a wireless communication module of the intelligent electric meter, once the intelligent electric meter is powered off, the electricity consumption information can be reported only after the intelligent electric meter is powered on again, and the situations of time delay and the like exist.
Therefore, how to fall the power back and in time report power consumption information is the utility model discloses the problem that needs to solve urgently.
Disclosure of Invention
The utility model aims at providing a fall electric emergency treatment system and chip for other module extension operating time such as smart electric meter's power consumption detection module, storage module and wireless communication module, and then realize that smart electric meter in time reports the purpose of power consumption information after falling the electricity.
The utility model provides a technical scheme as follows:
the utility model provides a power down emergency processing system, include:
the power failure detection module is used for generating a timing enabling signal when detecting that the power supply is powered down;
the power failure timing module is connected with the power failure detection module and used for starting timing according to the timing enabling signal and generating a control enabling signal;
and the power-off control module is connected with the power-down timing module and used for transmitting the electric energy stored in the power-on state to the power supply according to the control enabling signal.
Further, the power down control module includes: the LDO circuit, the voltage stabilizing capacitor, the super capacitor, the inductor, the diode and the BOOST circuit;
the first end of the LDO circuit is respectively connected with the first end of the voltage stabilizing capacitor and the power supply, and the second end of the voltage stabilizing capacitor is grounded;
the second end of the LDO circuit is respectively connected with the first end of the inductor, the first end of the super capacitor and the power failure detection module;
the BOOST circuit is connected to the control enabling signal, the BOOST circuit is respectively connected with the second end of the inductor and the anode of the diode, the cathode of the diode is connected with the power supply, and the second end of the super capacitor is grounded.
Further, the power down detection module includes: the device comprises a first sampling resistor, a second sampling resistor and a first comparator;
the first end of the first sampling resistor is connected to a power supply, the second end of the first sampling resistor is connected with the first end of the second sampling resistor, and the second end of the second sampling resistor is grounded;
the inverting input end of the first comparator is respectively connected with the second end of the first resistor and the first end of the second resistor;
the positive input end of the first comparator inputs a first reference voltage, and the output end of the first comparator outputs the timing enabling signal.
Further, the power down timing module includes: the device comprises a phase inverter, a first N-type MOS (metal oxide semiconductor) transistor, a first P-type MOS transistor, an off-chip capacitor and a second comparator;
the input end of the phase inverter is connected with the timing enabling signal, and the output end of the phase inverter is respectively connected with the grid electrodes of the first N-type MOS tube and the first P-type MOS tube;
the source of the first P-type MOS tube is connected with a current source, and the source of the first N-type MOS tube is grounded;
the reverse input end of the second comparator is respectively connected with the drain electrode of the first P-type MOS tube, the drain electrode of the first N-type MOS tube and the first end of the off-chip capacitor, and the second end of the off-chip capacitor is grounded;
and a second reference voltage is input to a positive input end of the second comparator, and the control enabling signal is output from an output end of the second comparator.
The invention also provides a chip integrated with the power failure emergency processing system, and the power failure emergency processing system comprises:
the power failure detection module is used for generating a timing enabling signal when detecting that the power supply is powered down;
the power failure timing module is connected with the power failure detection module and used for starting timing according to the timing enabling signal and generating a control enabling signal;
and the power-off control module is connected with the power-down timing module and used for transmitting the electric energy stored in the power-on state to the power supply according to the control enabling signal.
Further, the power down control module includes: the LDO circuit, the voltage stabilizing capacitor, the super capacitor, the inductor, the diode and the BOOST circuit;
the first end of the LDO circuit is respectively connected with the first end of the voltage stabilizing capacitor and the power supply, and the second end of the voltage stabilizing capacitor is grounded;
the second end of the LDO circuit is respectively connected with the first end of the inductor, the first end of the super capacitor and the power failure detection module;
the BOOST circuit is connected to the control enabling signal, the BOOST circuit is respectively connected with the second end of the inductor and the anode of the diode, the cathode of the diode is connected with the power supply, and the second end of the super capacitor is grounded.
Further, the power down detection module includes: the device comprises a first sampling resistor, a second sampling resistor and a first comparator;
the first end of the first sampling resistor is connected to a power supply, the second end of the first sampling resistor is connected with the first end of the second sampling resistor, and the second end of the second sampling resistor is grounded;
the inverting input end of the first comparator is respectively connected with the second end of the first resistor and the first end of the second resistor;
the positive input end of the first comparator inputs a first reference voltage, and the output end of the first comparator outputs the timing enabling signal.
Further, the power down timing module includes: the device comprises a phase inverter, a first N-type MOS (metal oxide semiconductor) transistor, a first P-type MOS transistor, an off-chip capacitor and a second comparator;
the input end of the phase inverter is connected with the timing enabling signal, and the output end of the phase inverter is respectively connected with the grid electrodes of the first N-type MOS tube and the first P-type MOS tube;
the source of the first P-type MOS tube is connected with a current source, and the source of the first N-type MOS tube is grounded;
the reverse input end of the second comparator is respectively connected with the drain electrode of the first P-type MOS tube, the drain electrode of the first N-type MOS tube and the first end of the off-chip capacitor, and the second end of the off-chip capacitor is grounded;
and a second reference voltage is input to a positive input end of the second comparator, and the control enabling signal is output from an output end of the second comparator.
Through the utility model provides a pair of fall electric emergency treatment system and chip can make other module extension operating time such as smart electric meter's power consumption detection module, storage module and wireless communication module, and then realize that smart electric meter in time reports the purpose of power consumption information after falling the electricity.
Drawings
The above features, technical features, advantages and implementations of a power down emergency processing system and chip will be further described in the following detailed description of preferred embodiments in a clearly understandable manner with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an embodiment of a power-down emergency processing system and a chip of the present invention;
fig. 2 is a schematic structural diagram of another embodiment of a power-down emergency processing system and chip of the present invention;
fig. 3 is a schematic structural diagram of another embodiment of a power-down emergency processing system and chip of the present invention;
fig. 4 is a schematic structural diagram of another embodiment of the power-down emergency processing system and chip of the present invention.
Detailed Description
In order to more clearly illustrate embodiments of the present invention or technical solutions in the prior art, specific embodiments of the present invention will be described below with reference to the accompanying drawings. It is obvious that the drawings in the following description are only examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be obtained from these drawings without inventive effort.
For the sake of simplicity, only the parts relevant to the present invention are schematically shown in the drawings, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
The utility model discloses an embodiment, as shown in FIG. 1, a fall electric emergency treatment system or integrated chip that has electricity electric emergency treatment system that has, fall electric emergency treatment system and include:
the power failure detection module 100 is configured to generate a timing enable signal EN _ count when detecting that the power supply VIN is powered down;
a power-down timing module 200, connected to the power-down detection module 100, configured to start timing according to the timing enable signal EN _ count, and generate a control enable signal EN _ BOOST;
and the power-off control module 300 is connected to the power-down timing module 200, and configured to transmit the electric energy stored in the power-on state to the power supply VIN according to the control enable signal EN _ BOOST.
Specifically, current smart electric meter detects load current voltage information including the power consumption detection function through power consumption detection module promptly to store the power consumption information that obtains to memory module, then show the power consumption information through the display screen, and in addition, current smart electric meter still includes power consumption information and reports the function, and power company is uploaded the power consumption information promptly through smart electric meter's wireless communication module. The current smart electric meter realizes converting the voltage current that can not directly measure in the electric wire netting into the voltage current that can be used to measure and handle, detect and in time store the electric quantity information that the user used, the electric quantity information upload notice power supply company that will store, it is timely to be convenient for power supply company, clearly master user's power consumption information, liberation personnel's that check meter the work load of checking meter, realize intelligence and check meter, reduce a large amount of labour cost of hiring the personnel of checking meter, and detect by smart electric meter by oneself and check meter, do not need the personnel of checking meter to check meter by adjacent family, promote the detection efficiency of power consumption information, promote user and power supply company's use experience.
However, the above functions must be realized only when the smart meter is powered on, and once a power supply VIN (a battery, a voltage conversion module that converts commercial power into a suitable voltage) of the smart meter is powered off, the smart meter cannot report power consumption information to a power supply company in time, and the smart meter can recover to a normal reporting state only after being powered on again. However, in this embodiment, the power-down control module 300 stores the electric energy during the process that the smart meter is in the power-up state, the power-down detection module 100 detects whether a power-down event occurs in the power supply VIN in real time, once the power-down detection module 100 detects that the power supply VIN is powered down, the power-down detection module 100 generates a timing enable signal EN _ count and transmits the timing enable signal EN _ count to the power-down timing module 200, the power-down timing module 200 generates a control enable signal EN _ BOOST after receiving the timing enable signal EN _ count, so that the power-down timing module 200 starts timing according to the timing enable signal EN _ count, and transmits the generated control enable signal EN _ BOOST to the power-down control module 300, and after receiving the control enable signal EN _ BOOST, the power-down control module 300 transmits the electric energy stored during the power-up process of the smart meter to the power supply VIN to supply VIN for supplying power, therefore, the power-off time of the power supply VIN is prolonged, and further, after the intelligent electric meter is powered down, the working time of other modules such as the power consumption detection module, the storage module and the wireless communication module of the intelligent electric meter is prolonged, and the purpose that the intelligent electric meter timely reports the power consumption information after the power failure is realized.
Based on the foregoing embodiment, as shown in fig. 2, the power-off control module 300 includes: the LDO circuit 310, the voltage stabilizing capacitor Cin, the super capacitor C3, the inductor L3, the diode D1 and the BOOST circuit 320;
a first end of the LDO circuit 310 is connected to a first end of the voltage stabilizing capacitor Cin and the power supply VIN, respectively, and a second end of the voltage stabilizing capacitor Cin is grounded;
a second end of the LDO circuit 310 is connected to the first end of the inductor L3, the first end of the super capacitor C3, and the power down detection module 100, respectively;
the BOOST circuit 320 is connected to the control enable signal EN _ BOOST, the BOOST circuit 320 is respectively connected to the second terminal of the inductor L3 and the anode of the diode D1, the cathode of the diode D1 is connected to the power supply VIN, and the second terminal of the super capacitor C3 is grounded.
Specifically, the capacitance value of the voltage stabilizing capacitor Cin is set according to the manual according to the requirement, and generally, the capacitance value of the voltage stabilizing capacitor Cin is UF level. The super capacitor C3 is a power source with special performance between the traditional capacitor and battery, and mainly depends on the electric double layer and the oxidation reduction pseudo capacitor to store electric energy, and the capacitance value of the super capacitor C3 is about 10F. The LDO circuit 310 is used to control the charging voltage of the super capacitor C3, and the super capacitor C3 is used to store the electric energy of the smart meter in the power-on state, and generally provides the required energy for processing the power-down event. The BOOST circuit 320 is used for supplying power to the power supply VIN to maintain the power required by the smart meter when the power is lost. The power failure detection module 100 is configured to detect a power failure event, that is, a power failure of the power supply VIN, and when the power failure event occurs, output a feedback signal PD to a controller (a single chip or a control chip) in the smart meter so as to indicate a power failure, and the power failure detection module 100 further outputs a timing enable signal EN _ count so as to start timing. The power down timing module 200 is configured to start timing when a power down event occurs and receives a timing enable signal EN _ count, and output a control enable signal EN _ BOOST to control the start and the shutdown of the BOOST circuit 320.
Based on the foregoing embodiments, as shown in fig. 3, the power down detection module 100 includes: a first sampling resistor R1, a second sampling resistor R2, a first Comparator 1;
a first end of the first sampling resistor R1 is connected to a power supply VIN, a second end of the first sampling resistor R1 is connected to a first end of the second sampling resistor R2, and a second end of the second sampling resistor R2 is grounded;
the inverting input (-) of the first Comparator1 is connected to the second terminal of the first resistor and the first terminal of the second resistor, respectively;
a positive input terminal (+) of the first Comparator1 inputs the first reference voltage Vref1, and an output terminal of the first Comparator1 outputs the timing enable signal EN _ count.
Specifically, as shown in FIG. 3, when
The timing enable signal EN _ count is 0. When in use
The timing enable signal EN _ count is 1V. As an example, the power supply VIN is typically 12V in the power-up state. The voltage value of the power supply VIN detected by the power loss detection module 100 is 9V. That is, when the power supply VIN is lower than 9V, the timing enable signal EN _ count is 1V.
At this time, R1 ═ 8MOhm, R2 ═ 1MOhm, and the first reference voltage Vref1 ═ 1V.
When the power supply VIN is smaller than 9V, the sampled voltage VA1 inputted to the inverting input (-) of the first Comparator1 is smaller than 1V, and the first Comparator1 determines and outputs the clock enable signal EN _ count to be 1V.
Based on the foregoing embodiment, as shown in fig. 4, the power down timing module 200 includes: the inverter FX, the first N-type MOS tube, the first P-type MOS tube, the off-chip capacitor Ccount and the second Comparator 2;
the input end of the phase inverter FX is connected to the timing enable signal EN _ count, and the output end of the phase inverter FX is connected to the gates G of the first N-type MOS transistor and the first P-type MOS transistor respectively;
a source S of the first P-type MOS tube is connected to a current source I1, and a source S of the first N-type MOS tube is grounded;
an inverting input terminal (-) of the second Comparator2 is respectively connected to the drain D of the first P-type MOS transistor, the drain D of the first N-type MOS transistor, and a first terminal of the off-chip capacitor Ccount, and a second terminal of the off-chip capacitor Ccount is grounded;
a positive input terminal (+) of the second Comparator2 inputs the second reference voltage Vref2, and an output terminal of the second Comparator2 outputs the control enable signal EN _ BOOST.
Specifically, the timing enable signal EN _ count is input to the previous stage power down detection module 100 for output. Ccount is the off-chip and in-time capacitance, and the capacitance value is in direct proportion to the timing time. As an example, the power supply VIN is typically 12V in the power-up state. When the power voltage is 12V, the timing enable signal EN _ count is 0V, and at this time, the first voltage value V1 output by the timing enable signal EN _ count through the inverter FX is 1V, so that the first P-type MOS transistor is turned off and the first N-type MOS transistor is turned on. The second voltage value V2 is 0V at this time. Assuming that the second reference voltage Vref2 is set to 1V, the control enable signal EN _ BOOST is 0V at this time.
When the power voltage is less than 9V, continuing the above example, the previous stage power down detection module 100 outputs the timing enable signal EN _ count of 1V, and at this time, the first voltage value V1 output by the timing enable signal EN _ count through the inverter FX is 0V, so that the first P-type MOS transistor is turned on and the first N-type MOS transistor is turned off. The current source I1I1 then charges the off-chip capacitor Ccount, while the voltage of the second voltage value V2 continues to increase, and when the second voltage value V2 exceeds the second reference voltage Vref2, the second Comparator2 asserts and outputs the control enable signal EN _ BOOST to 1.
The specific time calculation formula is
Assuming that the current value I1 of the current source I1 is 1uA, the capacity value of the off-chip capacitor Ccount is 1uF, and the second reference voltage Vref2 is 1V, the timing time Tcount of the power-down timing module 200 is 1 s. Also assuming the remaining conditions are unchanged, the capacitance value of the off-chip capacitor Ccount becomes 10uF, and the timing time of the power down timing module 200 becomes 10 s.
As shown in fig. 2, 3 and 4, when the power supply VIN is powered on, the electric energy is stored in the super capacitor C3 through the LDO circuit 310 for use in power down; when the power supply VIN loses power, the voltage value of the power supply VIN decreases, the power failure detection module 100 detects that the power supply VIN loses power, the output feedback signal PD is high, and tells other parts of the system that a power failure event occurs, in addition, a timing enable signal EN _ count is output to the power failure timing module 200 to start power failure timing, the power failure timing time is determined by the off-chip capacitor Ccount of the power failure timing module 200, and the larger the capacitance value of the off-chip capacitor Ccount is, the larger the timing time is. The power down timing module 200 starts timing after powering down and receiving the timing enable signal EN _ count, and outputs a control enable signal EN _ BOOST to control the operating time of the BOOST circuit 320 when a power down event occurs. The BOOST circuit 320 transfers the energy stored in the super capacitor C3 to the power supply VIN through the super capacitor C3 and the inductor L3, so as to delay the power-down time of the power supply VIN, so that the smart meter can process the power-down event in a short time and report the power-down event to the control center of the power supply company. When the smart meter is powered on again, the power supply VIN is high, and Vout is high, the feedback signal PD output by the power failure detection module 100 becomes zero, and the power failure event is cancelled.
It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (8)
1. A power failure emergency processing system, comprising:
the power failure detection module is used for generating a timing enabling signal when detecting that the power supply is powered down;
the power failure timing module is connected with the power failure detection module and used for starting timing according to the timing enabling signal and generating a control enabling signal;
and the power-off control module is connected with the power-down timing module and used for transmitting the electric energy stored in the power-on state to the power supply according to the control enabling signal.
2. The power-fail emergency processing system according to claim 1, wherein the power-fail control module includes: the LDO circuit, the voltage stabilizing capacitor, the super capacitor, the inductor, the diode and the BOOST circuit;
the first end of the LDO circuit is respectively connected with the first end of the voltage stabilizing capacitor and the power supply, and the second end of the voltage stabilizing capacitor is grounded;
the second end of the LDO circuit is respectively connected with the first end of the inductor, the first end of the super capacitor and the power failure detection module;
the BOOST circuit is connected to the control enabling signal, the BOOST circuit is respectively connected with the second end of the inductor and the anode of the diode, the cathode of the diode is connected with the power supply, and the second end of the super capacitor is grounded.
3. The power-down emergency processing system according to claim 1, wherein the power-down detection module includes: the device comprises a first sampling resistor, a second sampling resistor and a first comparator;
the first end of the first sampling resistor is connected to a power supply, the second end of the first sampling resistor is connected with the first end of the second sampling resistor, and the second end of the second sampling resistor is grounded;
the reverse input end of the first comparator is respectively connected with the second end of the first sampling resistor and the first end of the second sampling resistor;
the positive input end of the first comparator inputs a first reference voltage, and the output end of the first comparator outputs the timing enabling signal.
4. The power-down emergency processing system according to claim 1, wherein the power-down timing module comprises: the device comprises a phase inverter, a first N-type MOS (metal oxide semiconductor) transistor, a first P-type MOS transistor, an off-chip capacitor and a second comparator;
the input end of the phase inverter is connected with the timing enabling signal, and the output end of the phase inverter is respectively connected with the grid electrodes of the first N-type MOS tube and the first P-type MOS tube;
the source of the first P-type MOS tube is connected with a current source, and the source of the first N-type MOS tube is grounded;
the reverse input end of the second comparator is respectively connected with the drain electrode of the first P-type MOS tube, the drain electrode of the first N-type MOS tube and the first end of the off-chip capacitor, and the second end of the off-chip capacitor is grounded;
and a second reference voltage is input to a positive input end of the second comparator, and the control enabling signal is output from an output end of the second comparator.
5. A chip integrated with the power-down emergency processing system according to any one of claims 1 to 4, the power-down emergency processing system comprising:
the power failure detection module is used for generating a timing enabling signal when detecting that the power supply is powered down;
the power failure timing module is connected with the power failure detection module and used for starting timing according to the timing enabling signal and generating a control enabling signal;
and the power-off control module is connected with the power-down timing module and used for transmitting the electric energy stored in the power-on state to the power supply according to the control enabling signal.
6. The chip of claim 5, wherein the power-down control module comprises: the LDO circuit, the voltage stabilizing capacitor, the super capacitor, the inductor, the diode and the BOOST circuit;
the first end of the LDO circuit is respectively connected with the first end of the voltage stabilizing capacitor and the power supply, and the second end of the voltage stabilizing capacitor is grounded;
the second end of the LDO circuit is respectively connected with the first end of the inductor, the first end of the super capacitor and the power failure detection module;
the BOOST circuit is connected to the control enabling signal, the BOOST circuit is respectively connected with the second end of the inductor and the anode of the diode, the cathode of the diode is connected with the power supply, and the second end of the super capacitor is grounded.
7. The chip of claim 5, wherein the power down detection module comprises: the device comprises a first sampling resistor, a second sampling resistor and a first comparator;
the first end of the first sampling resistor is connected to a power supply, the second end of the first sampling resistor is connected with the first end of the second sampling resistor, and the second end of the second sampling resistor is grounded;
the reverse input end of the first comparator is respectively connected with the second end of the first sampling resistor and the first end of the second sampling resistor;
the positive input end of the first comparator inputs a first reference voltage, and the output end of the first comparator outputs the timing enabling signal.
8. The chip of claim 5, wherein the power down timing module comprises: the device comprises a phase inverter, a first N-type MOS (metal oxide semiconductor) transistor, a first P-type MOS transistor, an off-chip capacitor and a second comparator;
the input end of the phase inverter is connected with the timing enabling signal, and the output end of the phase inverter is respectively connected with the grid electrodes of the first N-type MOS tube and the first P-type MOS tube;
the source of the first P-type MOS tube is connected with a current source, and the source of the first N-type MOS tube is grounded;
the reverse input end of the second comparator is respectively connected with the drain electrode of the first P-type MOS tube, the drain electrode of the first N-type MOS tube and the first end of the off-chip capacitor, and the second end of the off-chip capacitor is grounded;
and a second reference voltage is input to a positive input end of the second comparator, and the control enabling signal is output from an output end of the second comparator.
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| CN201921692153.1U CN210724306U (en) | 2019-10-11 | 2019-10-11 | Power failure emergency processing system and chip |
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| CN201921692153.1U CN210724306U (en) | 2019-10-11 | 2019-10-11 | Power failure emergency processing system and chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112583246A (en) * | 2020-12-17 | 2021-03-30 | 英麦科（厦门）微电子科技有限公司 | Chip enabling circuit |
| CN117595652A (en) * | 2024-01-19 | 2024-02-23 | 芯北电子科技(南京)有限公司 | Power management circuit, chip, communication unit and equipment |
-
2019
- 2019-10-11 CN CN201921692153.1U patent/CN210724306U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112583246A (en) * | 2020-12-17 | 2021-03-30 | 英麦科（厦门）微电子科技有限公司 | Chip enabling circuit |
| CN112583246B (en) * | 2020-12-17 | 2024-05-10 | 拓尔微电子股份有限公司 | Chip enabling circuit |
| CN117595652A (en) * | 2024-01-19 | 2024-02-23 | 芯北电子科技(南京)有限公司 | Power management circuit, chip, communication unit and equipment |
| CN117595652B (en) * | 2024-01-19 | 2024-05-10 | 芯北电子科技(南京)有限公司 | Power management circuit, chip and control module |
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